1 #include <linux/atomic.h> 2 #include <linux/clk.h> 3 #include <linux/delay.h> 4 #include <linux/device.h> 5 #include <linux/i2c.h> 6 #include <linux/i2c-smbus.h> 7 #include <linux/io.h> 8 #include <linux/iopoll.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 12 /* Controller command patterns */ 13 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ 14 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */ 15 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */ 16 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */ 17 #define SW_TWSI_SIZE_SHIFT 52 18 #define SW_TWSI_ADDR_SHIFT 40 19 #define SW_TWSI_IA_SHIFT 32 /* Internal address */ 20 21 /* Controller opcode word (bits 60:57) */ 22 #define SW_TWSI_OP_SHIFT 57 23 #define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT) 24 #define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT) 25 #define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT) 26 #define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT) 27 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT) 28 #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */ 29 30 /* Controller extended opcode word (bits 34:32) */ 31 #define SW_TWSI_EOP_SHIFT 32 32 #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT) 33 #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT) 34 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) 35 #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) 36 #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT) 37 38 /* Controller command and status bits */ 39 #define TWSI_CTL_CE 0x80 /* High level controller enable */ 40 #define TWSI_CTL_ENAB 0x40 /* Bus enable */ 41 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */ 42 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */ 43 #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */ 44 #define TWSI_CTL_AAK 0x04 /* Assert ACK */ 45 46 /* Status values */ 47 #define STAT_ERROR 0x00 48 #define STAT_START 0x08 49 #define STAT_REP_START 0x10 50 #define STAT_TXADDR_ACK 0x18 51 #define STAT_TXADDR_NAK 0x20 52 #define STAT_TXDATA_ACK 0x28 53 #define STAT_TXDATA_NAK 0x30 54 #define STAT_LOST_ARB_38 0x38 55 #define STAT_RXADDR_ACK 0x40 56 #define STAT_RXADDR_NAK 0x48 57 #define STAT_RXDATA_ACK 0x50 58 #define STAT_RXDATA_NAK 0x58 59 #define STAT_SLAVE_60 0x60 60 #define STAT_LOST_ARB_68 0x68 61 #define STAT_SLAVE_70 0x70 62 #define STAT_LOST_ARB_78 0x78 63 #define STAT_SLAVE_80 0x80 64 #define STAT_SLAVE_88 0x88 65 #define STAT_GENDATA_ACK 0x90 66 #define STAT_GENDATA_NAK 0x98 67 #define STAT_SLAVE_A0 0xA0 68 #define STAT_SLAVE_A8 0xA8 69 #define STAT_LOST_ARB_B0 0xB0 70 #define STAT_SLAVE_LOST 0xB8 71 #define STAT_SLAVE_NAK 0xC0 72 #define STAT_SLAVE_ACK 0xC8 73 #define STAT_AD2W_ACK 0xD0 74 #define STAT_AD2W_NAK 0xD8 75 #define STAT_IDLE 0xF8 76 77 /* TWSI_INT values */ 78 #define TWSI_INT_ST_INT BIT_ULL(0) 79 #define TWSI_INT_TS_INT BIT_ULL(1) 80 #define TWSI_INT_CORE_INT BIT_ULL(2) 81 #define TWSI_INT_ST_EN BIT_ULL(4) 82 #define TWSI_INT_TS_EN BIT_ULL(5) 83 #define TWSI_INT_CORE_EN BIT_ULL(6) 84 #define TWSI_INT_SDA_OVR BIT_ULL(8) 85 #define TWSI_INT_SCL_OVR BIT_ULL(9) 86 #define TWSI_INT_SDA BIT_ULL(10) 87 #define TWSI_INT_SCL BIT_ULL(11) 88 89 #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */ 90 91 /* Register offsets */ 92 struct octeon_i2c_reg_offset { 93 unsigned int sw_twsi; 94 unsigned int twsi_int; 95 unsigned int sw_twsi_ext; 96 }; 97 98 #define SW_TWSI(x) (x->roff.sw_twsi) 99 #define TWSI_INT(x) (x->roff.twsi_int) 100 #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) 101 102 struct octeon_i2c { 103 wait_queue_head_t queue; 104 struct i2c_adapter adap; 105 struct octeon_i2c_reg_offset roff; 106 struct clk *clk; 107 int irq; 108 int hlc_irq; /* For cn7890 only */ 109 u32 twsi_freq; 110 int sys_freq; 111 void __iomem *twsi_base; 112 struct device *dev; 113 bool hlc_enabled; 114 bool broken_irq_mode; 115 bool broken_irq_check; 116 void (*int_enable)(struct octeon_i2c *); 117 void (*int_disable)(struct octeon_i2c *); 118 void (*hlc_int_enable)(struct octeon_i2c *); 119 void (*hlc_int_disable)(struct octeon_i2c *); 120 atomic_t int_enable_cnt; 121 atomic_t hlc_int_enable_cnt; 122 #if IS_ENABLED(CONFIG_I2C_THUNDERX) 123 struct msix_entry i2c_msix; 124 #endif 125 struct i2c_smbus_alert_setup alert_data; 126 struct i2c_client *ara; 127 }; 128 129 static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr) 130 { 131 __raw_writeq(val, addr); 132 __raw_readq(addr); /* wait for write to land */ 133 } 134 135 /** 136 * octeon_i2c_reg_write - write an I2C core register 137 * @i2c: The struct octeon_i2c 138 * @eop_reg: Register selector 139 * @data: Value to be written 140 * 141 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 142 */ 143 static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data) 144 { 145 u64 tmp; 146 147 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c)); 148 149 readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, tmp & SW_TWSI_V, 150 I2C_OCTEON_EVENT_WAIT, i2c->adap.timeout); 151 } 152 153 #define octeon_i2c_ctl_write(i2c, val) \ 154 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val) 155 #define octeon_i2c_data_write(i2c, val) \ 156 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val) 157 158 /** 159 * octeon_i2c_reg_read - read lower bits of an I2C core register 160 * @i2c: The struct octeon_i2c 161 * @eop_reg: Register selector 162 * 163 * Returns the data. 164 * 165 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 166 */ 167 static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, 168 int *error) 169 { 170 u64 tmp; 171 int ret; 172 173 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c)); 174 175 ret = readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, 176 tmp & SW_TWSI_V, I2C_OCTEON_EVENT_WAIT, 177 i2c->adap.timeout); 178 if (error) 179 *error = ret; 180 return tmp & 0xFF; 181 } 182 183 #define octeon_i2c_ctl_read(i2c) \ 184 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL) 185 #define octeon_i2c_data_read(i2c, error) \ 186 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error) 187 #define octeon_i2c_stat_read(i2c) \ 188 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL) 189 190 /** 191 * octeon_i2c_read_int - read the TWSI_INT register 192 * @i2c: The struct octeon_i2c 193 * 194 * Returns the value of the register. 195 */ 196 static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c) 197 { 198 return __raw_readq(i2c->twsi_base + TWSI_INT(i2c)); 199 } 200 201 /** 202 * octeon_i2c_write_int - write the TWSI_INT register 203 * @i2c: The struct octeon_i2c 204 * @data: Value to be written 205 */ 206 static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) 207 { 208 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); 209 } 210 211 /* Prototypes */ 212 irqreturn_t octeon_i2c_isr(int irq, void *dev_id); 213 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); 214 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c); 215 void octeon_i2c_set_clock(struct octeon_i2c *i2c); 216 extern struct i2c_bus_recovery_info octeon_i2c_recovery_info; 217