1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 4 * (https://opencores.org/project/i2c/overview) 5 * 6 * Peter Korsgaard <peter@korsgaard.com> 7 * 8 * Support for the GRLIB port of the controller by 9 * Andreas Larsson <andreas@gaisler.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/errno.h> 18 #include <linux/platform_device.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/wait.h> 22 #include <linux/platform_data/i2c-ocores.h> 23 #include <linux/slab.h> 24 #include <linux/io.h> 25 #include <linux/log2.h> 26 #include <linux/spinlock.h> 27 #include <linux/jiffies.h> 28 29 /* 30 * 'process_lock' exists because ocores_process() and ocores_process_timeout() 31 * can't run in parallel. 32 */ 33 struct ocores_i2c { 34 void __iomem *base; 35 int iobase; 36 u32 reg_shift; 37 u32 reg_io_width; 38 unsigned long flags; 39 wait_queue_head_t wait; 40 struct i2c_adapter adap; 41 struct i2c_msg *msg; 42 int pos; 43 int nmsgs; 44 int state; /* see STATE_ */ 45 spinlock_t process_lock; 46 struct clk *clk; 47 int ip_clock_khz; 48 int bus_clock_khz; 49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 50 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 51 }; 52 53 /* registers */ 54 #define OCI2C_PRELOW 0 55 #define OCI2C_PREHIGH 1 56 #define OCI2C_CONTROL 2 57 #define OCI2C_DATA 3 58 #define OCI2C_CMD 4 /* write only */ 59 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 60 61 #define OCI2C_CTRL_IEN 0x40 62 #define OCI2C_CTRL_EN 0x80 63 64 #define OCI2C_CMD_START 0x91 65 #define OCI2C_CMD_STOP 0x41 66 #define OCI2C_CMD_READ 0x21 67 #define OCI2C_CMD_WRITE 0x11 68 #define OCI2C_CMD_READ_ACK 0x21 69 #define OCI2C_CMD_READ_NACK 0x29 70 #define OCI2C_CMD_IACK 0x01 71 72 #define OCI2C_STAT_IF 0x01 73 #define OCI2C_STAT_TIP 0x02 74 #define OCI2C_STAT_ARBLOST 0x20 75 #define OCI2C_STAT_BUSY 0x40 76 #define OCI2C_STAT_NACK 0x80 77 78 #define STATE_DONE 0 79 #define STATE_START 1 80 #define STATE_WRITE 2 81 #define STATE_READ 3 82 #define STATE_ERROR 4 83 84 #define TYPE_OCORES 0 85 #define TYPE_GRLIB 1 86 87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ 88 89 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) 90 { 91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 92 } 93 94 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) 95 { 96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 97 } 98 99 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) 100 { 101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 102 } 103 104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) 105 { 106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); 107 } 108 109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) 110 { 111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); 112 } 113 114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) 115 { 116 return ioread8(i2c->base + (reg << i2c->reg_shift)); 117 } 118 119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) 120 { 121 return ioread16(i2c->base + (reg << i2c->reg_shift)); 122 } 123 124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) 125 { 126 return ioread32(i2c->base + (reg << i2c->reg_shift)); 127 } 128 129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) 130 { 131 return ioread16be(i2c->base + (reg << i2c->reg_shift)); 132 } 133 134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) 135 { 136 return ioread32be(i2c->base + (reg << i2c->reg_shift)); 137 } 138 139 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value) 140 { 141 outb(value, i2c->iobase + reg); 142 } 143 144 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg) 145 { 146 return inb(i2c->iobase + reg); 147 } 148 149 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 150 { 151 i2c->setreg(i2c, reg, value); 152 } 153 154 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 155 { 156 return i2c->getreg(i2c, reg); 157 } 158 159 static void ocores_process(struct ocores_i2c *i2c, u8 stat) 160 { 161 struct i2c_msg *msg = i2c->msg; 162 unsigned long flags; 163 164 /* 165 * If we spin here is because we are in timeout, so we are going 166 * to be in STATE_ERROR. See ocores_process_timeout() 167 */ 168 spin_lock_irqsave(&i2c->process_lock, flags); 169 170 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 171 /* stop has been sent */ 172 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 173 wake_up(&i2c->wait); 174 goto out; 175 } 176 177 /* error? */ 178 if (stat & OCI2C_STAT_ARBLOST) { 179 i2c->state = STATE_ERROR; 180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 181 goto out; 182 } 183 184 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 185 i2c->state = 186 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 187 188 if (stat & OCI2C_STAT_NACK) { 189 i2c->state = STATE_ERROR; 190 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 191 goto out; 192 } 193 } else { 194 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 195 } 196 197 /* end of msg? */ 198 if (i2c->pos == msg->len) { 199 i2c->nmsgs--; 200 i2c->msg++; 201 i2c->pos = 0; 202 msg = i2c->msg; 203 204 if (i2c->nmsgs) { /* end? */ 205 /* send start? */ 206 if (!(msg->flags & I2C_M_NOSTART)) { 207 u8 addr = i2c_8bit_addr_from_msg(msg); 208 209 i2c->state = STATE_START; 210 211 oc_setreg(i2c, OCI2C_DATA, addr); 212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 213 goto out; 214 } 215 i2c->state = (msg->flags & I2C_M_RD) 216 ? STATE_READ : STATE_WRITE; 217 } else { 218 i2c->state = STATE_DONE; 219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 220 goto out; 221 } 222 } 223 224 if (i2c->state == STATE_READ) { 225 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 226 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 227 } else { 228 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 229 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 230 } 231 232 out: 233 spin_unlock_irqrestore(&i2c->process_lock, flags); 234 } 235 236 static irqreturn_t ocores_isr(int irq, void *dev_id) 237 { 238 struct ocores_i2c *i2c = dev_id; 239 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 240 241 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { 242 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) 243 return IRQ_NONE; 244 } else if (!(stat & OCI2C_STAT_IF)) { 245 return IRQ_NONE; 246 } 247 ocores_process(i2c, stat); 248 249 return IRQ_HANDLED; 250 } 251 252 /** 253 * ocores_process_timeout() - Process timeout event 254 * @i2c: ocores I2C device instance 255 */ 256 static void ocores_process_timeout(struct ocores_i2c *i2c) 257 { 258 unsigned long flags; 259 260 spin_lock_irqsave(&i2c->process_lock, flags); 261 i2c->state = STATE_ERROR; 262 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 263 spin_unlock_irqrestore(&i2c->process_lock, flags); 264 } 265 266 /** 267 * ocores_wait() - Wait until something change in a given register 268 * @i2c: ocores I2C device instance 269 * @reg: register to query 270 * @mask: bitmask to apply on register value 271 * @val: expected result 272 * @timeout: timeout in jiffies 273 * 274 * Timeout is necessary to avoid to stay here forever when the chip 275 * does not answer correctly. 276 * 277 * Return: 0 on success, -ETIMEDOUT on timeout 278 */ 279 static int ocores_wait(struct ocores_i2c *i2c, 280 int reg, u8 mask, u8 val, 281 const unsigned long timeout) 282 { 283 unsigned long j; 284 285 j = jiffies + timeout; 286 while (1) { 287 u8 status = oc_getreg(i2c, reg); 288 289 if ((status & mask) == val) 290 break; 291 292 if (time_after(jiffies, j)) 293 return -ETIMEDOUT; 294 } 295 return 0; 296 } 297 298 /** 299 * ocores_poll_wait() - Wait until is possible to process some data 300 * @i2c: ocores I2C device instance 301 * 302 * Used when the device is in polling mode (interrupts disabled). 303 * 304 * Return: 0 on success, -ETIMEDOUT on timeout 305 */ 306 static int ocores_poll_wait(struct ocores_i2c *i2c) 307 { 308 u8 mask; 309 int err; 310 311 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { 312 /* transfer is over */ 313 mask = OCI2C_STAT_BUSY; 314 } else { 315 /* on going transfer */ 316 mask = OCI2C_STAT_TIP; 317 /* 318 * We wait for the data to be transferred (8bit), 319 * then we start polling on the ACK/NACK bit 320 */ 321 udelay((8 * 1000) / i2c->bus_clock_khz); 322 } 323 324 /* 325 * once we are here we expect to get the expected result immediately 326 * so if after 1ms we timeout then something is broken. 327 */ 328 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); 329 if (err) 330 dev_warn(i2c->adap.dev.parent, 331 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", 332 __func__, mask); 333 return err; 334 } 335 336 /** 337 * ocores_process_polling() - It handles an IRQ-less transfer 338 * @i2c: ocores I2C device instance 339 * 340 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same 341 * (only that IRQ are not produced). This means that we can re-use entirely 342 * ocores_isr(), we just add our polling code around it. 343 * 344 * It can run in atomic context 345 * 346 * Return: 0 on success, -ETIMEDOUT on timeout 347 */ 348 static int ocores_process_polling(struct ocores_i2c *i2c) 349 { 350 irqreturn_t ret; 351 int err = 0; 352 353 while (1) { 354 err = ocores_poll_wait(i2c); 355 if (err) 356 break; /* timeout */ 357 358 ret = ocores_isr(-1, i2c); 359 if (ret == IRQ_NONE) 360 break; /* all messages have been transferred */ 361 else { 362 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) 363 if (i2c->state == STATE_DONE) 364 break; 365 } 366 } 367 368 return err; 369 } 370 371 static int ocores_xfer_core(struct ocores_i2c *i2c, 372 struct i2c_msg *msgs, int num, 373 bool polling) 374 { 375 int ret = 0; 376 u8 ctrl; 377 378 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 379 if (polling) 380 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); 381 else 382 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); 383 384 i2c->msg = msgs; 385 i2c->pos = 0; 386 i2c->nmsgs = num; 387 i2c->state = STATE_START; 388 389 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); 390 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 391 392 if (polling) { 393 ret = ocores_process_polling(i2c); 394 } else { 395 if (wait_event_timeout(i2c->wait, 396 (i2c->state == STATE_ERROR) || 397 (i2c->state == STATE_DONE), HZ) == 0) 398 ret = -ETIMEDOUT; 399 } 400 if (ret) { 401 ocores_process_timeout(i2c); 402 return ret; 403 } 404 405 return (i2c->state == STATE_DONE) ? num : -EIO; 406 } 407 408 static int ocores_xfer_polling(struct i2c_adapter *adap, 409 struct i2c_msg *msgs, int num) 410 { 411 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); 412 } 413 414 static int ocores_xfer(struct i2c_adapter *adap, 415 struct i2c_msg *msgs, int num) 416 { 417 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false); 418 } 419 420 static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 421 { 422 int prescale; 423 int diff; 424 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 425 426 /* make sure the device is disabled */ 427 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 428 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 429 430 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 431 prescale = clamp(prescale, 0, 0xffff); 432 433 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; 434 if (abs(diff) > i2c->bus_clock_khz / 10) { 435 dev_err(dev, 436 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", 437 i2c->ip_clock_khz, i2c->bus_clock_khz); 438 return -EINVAL; 439 } 440 441 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 442 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 443 444 /* Init the device */ 445 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 446 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); 447 448 return 0; 449 } 450 451 452 static u32 ocores_func(struct i2c_adapter *adap) 453 { 454 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 455 } 456 457 static struct i2c_algorithm ocores_algorithm = { 458 .master_xfer = ocores_xfer, 459 .master_xfer_atomic = ocores_xfer_polling, 460 .functionality = ocores_func, 461 }; 462 463 static const struct i2c_adapter ocores_adapter = { 464 .owner = THIS_MODULE, 465 .name = "i2c-ocores", 466 .class = I2C_CLASS_DEPRECATED, 467 .algo = &ocores_algorithm, 468 }; 469 470 static const struct of_device_id ocores_i2c_match[] = { 471 { 472 .compatible = "opencores,i2c-ocores", 473 .data = (void *)TYPE_OCORES, 474 }, 475 { 476 .compatible = "aeroflexgaisler,i2cmst", 477 .data = (void *)TYPE_GRLIB, 478 }, 479 { 480 .compatible = "sifive,fu540-c000-i2c", 481 }, 482 { 483 .compatible = "sifive,i2c0", 484 }, 485 {}, 486 }; 487 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 488 489 #ifdef CONFIG_OF 490 /* 491 * Read and write functions for the GRLIB port of the controller. Registers are 492 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one 493 * register. The subsequent registers have their offsets decreased accordingly. 494 */ 495 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) 496 { 497 u32 rd; 498 int rreg = reg; 499 500 if (reg != OCI2C_PRELOW) 501 rreg--; 502 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 503 if (reg == OCI2C_PREHIGH) 504 return (u8)(rd >> 8); 505 else 506 return (u8)rd; 507 } 508 509 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) 510 { 511 u32 curr, wr; 512 int rreg = reg; 513 514 if (reg != OCI2C_PRELOW) 515 rreg--; 516 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { 517 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 518 if (reg == OCI2C_PRELOW) 519 wr = (curr & 0xff00) | value; 520 else 521 wr = (((u32)value) << 8) | (curr & 0xff); 522 } else { 523 wr = value; 524 } 525 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); 526 } 527 528 static int ocores_i2c_of_probe(struct platform_device *pdev, 529 struct ocores_i2c *i2c) 530 { 531 struct device_node *np = pdev->dev.of_node; 532 const struct of_device_id *match; 533 u32 val; 534 u32 clock_frequency; 535 bool clock_frequency_present; 536 537 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 538 /* no 'reg-shift', check for deprecated 'regstep' */ 539 if (!of_property_read_u32(np, "regstep", &val)) { 540 if (!is_power_of_2(val)) { 541 dev_err(&pdev->dev, "invalid regstep %d\n", 542 val); 543 return -EINVAL; 544 } 545 i2c->reg_shift = ilog2(val); 546 dev_warn(&pdev->dev, 547 "regstep property deprecated, use reg-shift\n"); 548 } 549 } 550 551 clock_frequency_present = !of_property_read_u32(np, "clock-frequency", 552 &clock_frequency); 553 i2c->bus_clock_khz = 100; 554 555 i2c->clk = devm_clk_get(&pdev->dev, NULL); 556 557 if (!IS_ERR(i2c->clk)) { 558 int ret = clk_prepare_enable(i2c->clk); 559 560 if (ret) { 561 dev_err(&pdev->dev, 562 "clk_prepare_enable failed: %d\n", ret); 563 return ret; 564 } 565 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; 566 if (clock_frequency_present) 567 i2c->bus_clock_khz = clock_frequency / 1000; 568 } 569 570 if (i2c->ip_clock_khz == 0) { 571 if (of_property_read_u32(np, "opencores,ip-clock-frequency", 572 &val)) { 573 if (!clock_frequency_present) { 574 dev_err(&pdev->dev, 575 "Missing required parameter 'opencores,ip-clock-frequency'\n"); 576 clk_disable_unprepare(i2c->clk); 577 return -ENODEV; 578 } 579 i2c->ip_clock_khz = clock_frequency / 1000; 580 dev_warn(&pdev->dev, 581 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); 582 } else { 583 i2c->ip_clock_khz = val / 1000; 584 if (clock_frequency_present) 585 i2c->bus_clock_khz = clock_frequency / 1000; 586 } 587 } 588 589 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 590 &i2c->reg_io_width); 591 592 match = of_match_node(ocores_i2c_match, pdev->dev.of_node); 593 if (match && (long)match->data == TYPE_GRLIB) { 594 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); 595 i2c->setreg = oc_setreg_grlib; 596 i2c->getreg = oc_getreg_grlib; 597 } 598 599 return 0; 600 } 601 #else 602 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV 603 #endif 604 605 static int ocores_i2c_probe(struct platform_device *pdev) 606 { 607 struct ocores_i2c *i2c; 608 struct ocores_i2c_platform_data *pdata; 609 struct resource *res; 610 int irq; 611 int ret; 612 int i; 613 614 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 615 if (!i2c) 616 return -ENOMEM; 617 618 spin_lock_init(&i2c->process_lock); 619 620 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 621 if (res) { 622 i2c->base = devm_ioremap_resource(&pdev->dev, res); 623 if (IS_ERR(i2c->base)) 624 return PTR_ERR(i2c->base); 625 } else { 626 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 627 if (!res) 628 return -EINVAL; 629 i2c->iobase = res->start; 630 if (!devm_request_region(&pdev->dev, res->start, 631 resource_size(res), 632 pdev->name)) { 633 dev_err(&pdev->dev, "Can't get I/O resource.\n"); 634 return -EBUSY; 635 } 636 i2c->setreg = oc_setreg_io_8; 637 i2c->getreg = oc_getreg_io_8; 638 } 639 640 pdata = dev_get_platdata(&pdev->dev); 641 if (pdata) { 642 i2c->reg_shift = pdata->reg_shift; 643 i2c->reg_io_width = pdata->reg_io_width; 644 i2c->ip_clock_khz = pdata->clock_khz; 645 if (pdata->bus_khz) 646 i2c->bus_clock_khz = pdata->bus_khz; 647 else 648 i2c->bus_clock_khz = 100; 649 } else { 650 ret = ocores_i2c_of_probe(pdev, i2c); 651 if (ret) 652 return ret; 653 } 654 655 if (i2c->reg_io_width == 0) 656 i2c->reg_io_width = 1; /* Set to default value */ 657 658 if (!i2c->setreg || !i2c->getreg) { 659 bool be = pdata ? pdata->big_endian : 660 of_device_is_big_endian(pdev->dev.of_node); 661 662 switch (i2c->reg_io_width) { 663 case 1: 664 i2c->setreg = oc_setreg_8; 665 i2c->getreg = oc_getreg_8; 666 break; 667 668 case 2: 669 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; 670 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; 671 break; 672 673 case 4: 674 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; 675 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; 676 break; 677 678 default: 679 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", 680 i2c->reg_io_width); 681 ret = -EINVAL; 682 goto err_clk; 683 } 684 } 685 686 init_waitqueue_head(&i2c->wait); 687 688 irq = platform_get_irq_optional(pdev, 0); 689 /* 690 * Since the SoC does have an interrupt, its DT has an interrupt 691 * property - But this should be bypassed as the IRQ logic in this 692 * SoC is broken. 693 */ 694 if (of_device_is_compatible(pdev->dev.of_node, 695 "sifive,fu540-c000-i2c")) { 696 i2c->flags |= OCORES_FLAG_BROKEN_IRQ; 697 irq = -ENXIO; 698 } 699 700 if (irq == -ENXIO) { 701 ocores_algorithm.master_xfer = ocores_xfer_polling; 702 } else { 703 if (irq < 0) 704 return irq; 705 } 706 707 if (ocores_algorithm.master_xfer != ocores_xfer_polling) { 708 ret = devm_request_any_context_irq(&pdev->dev, irq, 709 ocores_isr, 0, 710 pdev->name, i2c); 711 if (ret) { 712 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 713 goto err_clk; 714 } 715 } 716 717 ret = ocores_init(&pdev->dev, i2c); 718 if (ret) 719 goto err_clk; 720 721 /* hook up driver to tree */ 722 platform_set_drvdata(pdev, i2c); 723 i2c->adap = ocores_adapter; 724 i2c_set_adapdata(&i2c->adap, i2c); 725 i2c->adap.dev.parent = &pdev->dev; 726 i2c->adap.dev.of_node = pdev->dev.of_node; 727 728 /* add i2c adapter to i2c tree */ 729 ret = i2c_add_adapter(&i2c->adap); 730 if (ret) 731 goto err_clk; 732 733 /* add in known devices to the bus */ 734 if (pdata) { 735 for (i = 0; i < pdata->num_devices; i++) 736 i2c_new_client_device(&i2c->adap, pdata->devices + i); 737 } 738 739 return 0; 740 741 err_clk: 742 clk_disable_unprepare(i2c->clk); 743 return ret; 744 } 745 746 static int ocores_i2c_remove(struct platform_device *pdev) 747 { 748 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 749 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 750 751 /* disable i2c logic */ 752 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 753 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 754 755 /* remove adapter & data */ 756 i2c_del_adapter(&i2c->adap); 757 758 if (!IS_ERR(i2c->clk)) 759 clk_disable_unprepare(i2c->clk); 760 761 return 0; 762 } 763 764 #ifdef CONFIG_PM_SLEEP 765 static int ocores_i2c_suspend(struct device *dev) 766 { 767 struct ocores_i2c *i2c = dev_get_drvdata(dev); 768 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 769 770 /* make sure the device is disabled */ 771 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 772 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 773 774 if (!IS_ERR(i2c->clk)) 775 clk_disable_unprepare(i2c->clk); 776 return 0; 777 } 778 779 static int ocores_i2c_resume(struct device *dev) 780 { 781 struct ocores_i2c *i2c = dev_get_drvdata(dev); 782 783 if (!IS_ERR(i2c->clk)) { 784 unsigned long rate; 785 int ret = clk_prepare_enable(i2c->clk); 786 787 if (ret) { 788 dev_err(dev, 789 "clk_prepare_enable failed: %d\n", ret); 790 return ret; 791 } 792 rate = clk_get_rate(i2c->clk) / 1000; 793 if (rate) 794 i2c->ip_clock_khz = rate; 795 } 796 return ocores_init(dev, i2c); 797 } 798 799 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 800 #define OCORES_I2C_PM (&ocores_i2c_pm) 801 #else 802 #define OCORES_I2C_PM NULL 803 #endif 804 805 static struct platform_driver ocores_i2c_driver = { 806 .probe = ocores_i2c_probe, 807 .remove = ocores_i2c_remove, 808 .driver = { 809 .name = "ocores-i2c", 810 .of_match_table = ocores_i2c_match, 811 .pm = OCORES_I2C_PM, 812 }, 813 }; 814 815 module_platform_driver(ocores_i2c_driver); 816 817 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>"); 818 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 819 MODULE_LICENSE("GPL"); 820 MODULE_ALIAS("platform:ocores-i2c"); 821