1 /* 2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 3 * (http://www.opencores.org/projects.cgi/web/i2c/overview). 4 * 5 * Peter Korsgaard <jacmet@sunsite.dk> 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 /* 13 * This driver can be used from the device tree, see 14 * Documentation/devicetree/bindings/i2c/ocore-i2c.txt 15 */ 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/errno.h> 20 #include <linux/platform_device.h> 21 #include <linux/i2c.h> 22 #include <linux/interrupt.h> 23 #include <linux/wait.h> 24 #include <linux/i2c-ocores.h> 25 #include <linux/slab.h> 26 #include <linux/io.h> 27 #include <linux/of_i2c.h> 28 #include <linux/log2.h> 29 30 struct ocores_i2c { 31 void __iomem *base; 32 u32 reg_shift; 33 u32 reg_io_width; 34 wait_queue_head_t wait; 35 struct i2c_adapter adap; 36 struct i2c_msg *msg; 37 int pos; 38 int nmsgs; 39 int state; /* see STATE_ */ 40 int clock_khz; 41 }; 42 43 /* registers */ 44 #define OCI2C_PRELOW 0 45 #define OCI2C_PREHIGH 1 46 #define OCI2C_CONTROL 2 47 #define OCI2C_DATA 3 48 #define OCI2C_CMD 4 /* write only */ 49 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 50 51 #define OCI2C_CTRL_IEN 0x40 52 #define OCI2C_CTRL_EN 0x80 53 54 #define OCI2C_CMD_START 0x91 55 #define OCI2C_CMD_STOP 0x41 56 #define OCI2C_CMD_READ 0x21 57 #define OCI2C_CMD_WRITE 0x11 58 #define OCI2C_CMD_READ_ACK 0x21 59 #define OCI2C_CMD_READ_NACK 0x29 60 #define OCI2C_CMD_IACK 0x01 61 62 #define OCI2C_STAT_IF 0x01 63 #define OCI2C_STAT_TIP 0x02 64 #define OCI2C_STAT_ARBLOST 0x20 65 #define OCI2C_STAT_BUSY 0x40 66 #define OCI2C_STAT_NACK 0x80 67 68 #define STATE_DONE 0 69 #define STATE_START 1 70 #define STATE_WRITE 2 71 #define STATE_READ 3 72 #define STATE_ERROR 4 73 74 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 75 { 76 if (i2c->reg_io_width == 4) 77 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 78 else if (i2c->reg_io_width == 2) 79 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 80 else 81 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 82 } 83 84 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 85 { 86 if (i2c->reg_io_width == 4) 87 return ioread32(i2c->base + (reg << i2c->reg_shift)); 88 else if (i2c->reg_io_width == 2) 89 return ioread16(i2c->base + (reg << i2c->reg_shift)); 90 else 91 return ioread8(i2c->base + (reg << i2c->reg_shift)); 92 } 93 94 static void ocores_process(struct ocores_i2c *i2c) 95 { 96 struct i2c_msg *msg = i2c->msg; 97 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 98 99 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 100 /* stop has been sent */ 101 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 102 wake_up(&i2c->wait); 103 return; 104 } 105 106 /* error? */ 107 if (stat & OCI2C_STAT_ARBLOST) { 108 i2c->state = STATE_ERROR; 109 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 110 return; 111 } 112 113 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 114 i2c->state = 115 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 116 117 if (stat & OCI2C_STAT_NACK) { 118 i2c->state = STATE_ERROR; 119 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 120 return; 121 } 122 } else 123 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 124 125 /* end of msg? */ 126 if (i2c->pos == msg->len) { 127 i2c->nmsgs--; 128 i2c->msg++; 129 i2c->pos = 0; 130 msg = i2c->msg; 131 132 if (i2c->nmsgs) { /* end? */ 133 /* send start? */ 134 if (!(msg->flags & I2C_M_NOSTART)) { 135 u8 addr = (msg->addr << 1); 136 137 if (msg->flags & I2C_M_RD) 138 addr |= 1; 139 140 i2c->state = STATE_START; 141 142 oc_setreg(i2c, OCI2C_DATA, addr); 143 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 144 return; 145 } else 146 i2c->state = (msg->flags & I2C_M_RD) 147 ? STATE_READ : STATE_WRITE; 148 } else { 149 i2c->state = STATE_DONE; 150 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 151 return; 152 } 153 } 154 155 if (i2c->state == STATE_READ) { 156 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 157 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 158 } else { 159 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 160 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 161 } 162 } 163 164 static irqreturn_t ocores_isr(int irq, void *dev_id) 165 { 166 struct ocores_i2c *i2c = dev_id; 167 168 ocores_process(i2c); 169 170 return IRQ_HANDLED; 171 } 172 173 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 174 { 175 struct ocores_i2c *i2c = i2c_get_adapdata(adap); 176 177 i2c->msg = msgs; 178 i2c->pos = 0; 179 i2c->nmsgs = num; 180 i2c->state = STATE_START; 181 182 oc_setreg(i2c, OCI2C_DATA, 183 (i2c->msg->addr << 1) | 184 ((i2c->msg->flags & I2C_M_RD) ? 1:0)); 185 186 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 187 188 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 189 (i2c->state == STATE_DONE), HZ)) 190 return (i2c->state == STATE_DONE) ? num : -EIO; 191 else 192 return -ETIMEDOUT; 193 } 194 195 static void ocores_init(struct ocores_i2c *i2c) 196 { 197 int prescale; 198 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 199 200 /* make sure the device is disabled */ 201 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 202 203 prescale = (i2c->clock_khz / (5*100)) - 1; 204 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 205 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 206 207 /* Init the device */ 208 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 209 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); 210 } 211 212 213 static u32 ocores_func(struct i2c_adapter *adap) 214 { 215 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 216 } 217 218 static const struct i2c_algorithm ocores_algorithm = { 219 .master_xfer = ocores_xfer, 220 .functionality = ocores_func, 221 }; 222 223 static struct i2c_adapter ocores_adapter = { 224 .owner = THIS_MODULE, 225 .name = "i2c-ocores", 226 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 227 .algo = &ocores_algorithm, 228 }; 229 230 #ifdef CONFIG_OF 231 static int ocores_i2c_of_probe(struct platform_device *pdev, 232 struct ocores_i2c *i2c) 233 { 234 struct device_node *np = pdev->dev.of_node; 235 u32 val; 236 237 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 238 /* no 'reg-shift', check for deprecated 'regstep' */ 239 if (!of_property_read_u32(np, "regstep", &val)) { 240 if (!is_power_of_2(val)) { 241 dev_err(&pdev->dev, "invalid regstep %d\n", 242 val); 243 return -EINVAL; 244 } 245 i2c->reg_shift = ilog2(val); 246 dev_warn(&pdev->dev, 247 "regstep property deprecated, use reg-shift\n"); 248 } 249 } 250 251 if (of_property_read_u32(np, "clock-frequency", &val)) { 252 dev_err(&pdev->dev, 253 "Missing required parameter 'clock-frequency'\n"); 254 return -ENODEV; 255 } 256 i2c->clock_khz = val / 1000; 257 258 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 259 &i2c->reg_io_width); 260 return 0; 261 } 262 #else 263 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV 264 #endif 265 266 static int __devinit ocores_i2c_probe(struct platform_device *pdev) 267 { 268 struct ocores_i2c *i2c; 269 struct ocores_i2c_platform_data *pdata; 270 struct resource *res, *res2; 271 int ret; 272 int i; 273 274 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 275 if (!res) 276 return -ENODEV; 277 278 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 279 if (!res2) 280 return -ENODEV; 281 282 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 283 if (!i2c) 284 return -ENOMEM; 285 286 if (!devm_request_mem_region(&pdev->dev, res->start, 287 resource_size(res), pdev->name)) { 288 dev_err(&pdev->dev, "Memory region busy\n"); 289 return -EBUSY; 290 } 291 292 i2c->base = devm_ioremap_nocache(&pdev->dev, res->start, 293 resource_size(res)); 294 if (!i2c->base) { 295 dev_err(&pdev->dev, "Unable to map registers\n"); 296 return -EIO; 297 } 298 299 pdata = pdev->dev.platform_data; 300 if (pdata) { 301 i2c->reg_shift = pdata->reg_shift; 302 i2c->reg_io_width = pdata->reg_io_width; 303 i2c->clock_khz = pdata->clock_khz; 304 } else { 305 ret = ocores_i2c_of_probe(pdev, i2c); 306 if (ret) 307 return ret; 308 } 309 310 if (i2c->reg_io_width == 0) 311 i2c->reg_io_width = 1; /* Set to default value */ 312 313 ocores_init(i2c); 314 315 init_waitqueue_head(&i2c->wait); 316 ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0, 317 pdev->name, i2c); 318 if (ret) { 319 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 320 return ret; 321 } 322 323 /* hook up driver to tree */ 324 platform_set_drvdata(pdev, i2c); 325 i2c->adap = ocores_adapter; 326 i2c_set_adapdata(&i2c->adap, i2c); 327 i2c->adap.dev.parent = &pdev->dev; 328 i2c->adap.dev.of_node = pdev->dev.of_node; 329 330 /* add i2c adapter to i2c tree */ 331 ret = i2c_add_adapter(&i2c->adap); 332 if (ret) { 333 dev_err(&pdev->dev, "Failed to add adapter\n"); 334 return ret; 335 } 336 337 /* add in known devices to the bus */ 338 if (pdata) { 339 for (i = 0; i < pdata->num_devices; i++) 340 i2c_new_device(&i2c->adap, pdata->devices + i); 341 } else { 342 of_i2c_register_devices(&i2c->adap); 343 } 344 345 return 0; 346 } 347 348 static int __devexit ocores_i2c_remove(struct platform_device *pdev) 349 { 350 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 351 352 /* disable i2c logic */ 353 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) 354 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 355 356 /* remove adapter & data */ 357 i2c_del_adapter(&i2c->adap); 358 platform_set_drvdata(pdev, NULL); 359 360 return 0; 361 } 362 363 #ifdef CONFIG_PM 364 static int ocores_i2c_suspend(struct device *dev) 365 { 366 struct ocores_i2c *i2c = dev_get_drvdata(dev); 367 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 368 369 /* make sure the device is disabled */ 370 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 371 372 return 0; 373 } 374 375 static int ocores_i2c_resume(struct device *dev) 376 { 377 struct ocores_i2c *i2c = dev_get_drvdata(dev); 378 379 ocores_init(i2c); 380 381 return 0; 382 } 383 384 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 385 #define OCORES_I2C_PM (&ocores_i2c_pm) 386 #else 387 #define OCORES_I2C_PM NULL 388 #endif 389 390 static struct of_device_id ocores_i2c_match[] = { 391 { .compatible = "opencores,i2c-ocores", }, 392 {}, 393 }; 394 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 395 396 static struct platform_driver ocores_i2c_driver = { 397 .probe = ocores_i2c_probe, 398 .remove = __devexit_p(ocores_i2c_remove), 399 .driver = { 400 .owner = THIS_MODULE, 401 .name = "ocores-i2c", 402 .of_match_table = ocores_i2c_match, 403 .pm = OCORES_I2C_PM, 404 }, 405 }; 406 407 module_platform_driver(ocores_i2c_driver); 408 409 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 410 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 411 MODULE_LICENSE("GPL"); 412 MODULE_ALIAS("platform:ocores-i2c"); 413