1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 4 * (https://opencores.org/project/i2c/overview) 5 * 6 * Peter Korsgaard <peter@korsgaard.com> 7 * 8 * Support for the GRLIB port of the controller by 9 * Andreas Larsson <andreas@gaisler.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/errno.h> 18 #include <linux/platform_device.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/wait.h> 22 #include <linux/platform_data/i2c-ocores.h> 23 #include <linux/slab.h> 24 #include <linux/io.h> 25 #include <linux/log2.h> 26 #include <linux/spinlock.h> 27 #include <linux/jiffies.h> 28 29 /* 30 * 'process_lock' exists because ocores_process() and ocores_process_timeout() 31 * can't run in parallel. 32 */ 33 struct ocores_i2c { 34 void __iomem *base; 35 int iobase; 36 u32 reg_shift; 37 u32 reg_io_width; 38 unsigned long flags; 39 wait_queue_head_t wait; 40 struct i2c_adapter adap; 41 struct i2c_msg *msg; 42 int pos; 43 int nmsgs; 44 int state; /* see STATE_ */ 45 spinlock_t process_lock; 46 struct clk *clk; 47 int ip_clock_khz; 48 int bus_clock_khz; 49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 50 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 51 }; 52 53 /* registers */ 54 #define OCI2C_PRELOW 0 55 #define OCI2C_PREHIGH 1 56 #define OCI2C_CONTROL 2 57 #define OCI2C_DATA 3 58 #define OCI2C_CMD 4 /* write only */ 59 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 60 61 #define OCI2C_CTRL_IEN 0x40 62 #define OCI2C_CTRL_EN 0x80 63 64 #define OCI2C_CMD_START 0x91 65 #define OCI2C_CMD_STOP 0x41 66 #define OCI2C_CMD_READ 0x21 67 #define OCI2C_CMD_WRITE 0x11 68 #define OCI2C_CMD_READ_ACK 0x21 69 #define OCI2C_CMD_READ_NACK 0x29 70 #define OCI2C_CMD_IACK 0x01 71 72 #define OCI2C_STAT_IF 0x01 73 #define OCI2C_STAT_TIP 0x02 74 #define OCI2C_STAT_ARBLOST 0x20 75 #define OCI2C_STAT_BUSY 0x40 76 #define OCI2C_STAT_NACK 0x80 77 78 #define STATE_DONE 0 79 #define STATE_START 1 80 #define STATE_WRITE 2 81 #define STATE_READ 3 82 #define STATE_ERROR 4 83 84 #define TYPE_OCORES 0 85 #define TYPE_GRLIB 1 86 87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ 88 89 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) 90 { 91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 92 } 93 94 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) 95 { 96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 97 } 98 99 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) 100 { 101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 102 } 103 104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) 105 { 106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); 107 } 108 109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) 110 { 111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); 112 } 113 114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) 115 { 116 return ioread8(i2c->base + (reg << i2c->reg_shift)); 117 } 118 119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) 120 { 121 return ioread16(i2c->base + (reg << i2c->reg_shift)); 122 } 123 124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) 125 { 126 return ioread32(i2c->base + (reg << i2c->reg_shift)); 127 } 128 129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) 130 { 131 return ioread16be(i2c->base + (reg << i2c->reg_shift)); 132 } 133 134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) 135 { 136 return ioread32be(i2c->base + (reg << i2c->reg_shift)); 137 } 138 139 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value) 140 { 141 outb(value, i2c->iobase + reg); 142 } 143 144 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg) 145 { 146 return inb(i2c->iobase + reg); 147 } 148 149 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 150 { 151 i2c->setreg(i2c, reg, value); 152 } 153 154 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 155 { 156 return i2c->getreg(i2c, reg); 157 } 158 159 static void ocores_process(struct ocores_i2c *i2c, u8 stat) 160 { 161 struct i2c_msg *msg = i2c->msg; 162 unsigned long flags; 163 164 /* 165 * If we spin here is because we are in timeout, so we are going 166 * to be in STATE_ERROR. See ocores_process_timeout() 167 */ 168 spin_lock_irqsave(&i2c->process_lock, flags); 169 170 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 171 /* stop has been sent */ 172 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 173 wake_up(&i2c->wait); 174 goto out; 175 } 176 177 /* error? */ 178 if (stat & OCI2C_STAT_ARBLOST) { 179 i2c->state = STATE_ERROR; 180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 181 goto out; 182 } 183 184 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 185 i2c->state = 186 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 187 188 if (stat & OCI2C_STAT_NACK) { 189 i2c->state = STATE_ERROR; 190 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 191 goto out; 192 } 193 } else { 194 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 195 } 196 197 /* end of msg? */ 198 if (i2c->pos == msg->len) { 199 i2c->nmsgs--; 200 i2c->msg++; 201 i2c->pos = 0; 202 msg = i2c->msg; 203 204 if (i2c->nmsgs) { /* end? */ 205 /* send start? */ 206 if (!(msg->flags & I2C_M_NOSTART)) { 207 u8 addr = i2c_8bit_addr_from_msg(msg); 208 209 i2c->state = STATE_START; 210 211 oc_setreg(i2c, OCI2C_DATA, addr); 212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 213 goto out; 214 } 215 i2c->state = (msg->flags & I2C_M_RD) 216 ? STATE_READ : STATE_WRITE; 217 } else { 218 i2c->state = STATE_DONE; 219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 220 goto out; 221 } 222 } 223 224 if (i2c->state == STATE_READ) { 225 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 226 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 227 } else { 228 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 229 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 230 } 231 232 out: 233 spin_unlock_irqrestore(&i2c->process_lock, flags); 234 } 235 236 static irqreturn_t ocores_isr(int irq, void *dev_id) 237 { 238 struct ocores_i2c *i2c = dev_id; 239 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 240 241 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { 242 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) 243 return IRQ_NONE; 244 } else if (!(stat & OCI2C_STAT_IF)) { 245 return IRQ_NONE; 246 } 247 ocores_process(i2c, stat); 248 249 return IRQ_HANDLED; 250 } 251 252 /** 253 * Process timeout event 254 * @i2c: ocores I2C device instance 255 */ 256 static void ocores_process_timeout(struct ocores_i2c *i2c) 257 { 258 unsigned long flags; 259 260 spin_lock_irqsave(&i2c->process_lock, flags); 261 i2c->state = STATE_ERROR; 262 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 263 spin_unlock_irqrestore(&i2c->process_lock, flags); 264 } 265 266 /** 267 * Wait until something change in a given register 268 * @i2c: ocores I2C device instance 269 * @reg: register to query 270 * @mask: bitmask to apply on register value 271 * @val: expected result 272 * @timeout: timeout in jiffies 273 * 274 * Timeout is necessary to avoid to stay here forever when the chip 275 * does not answer correctly. 276 * 277 * Return: 0 on success, -ETIMEDOUT on timeout 278 */ 279 static int ocores_wait(struct ocores_i2c *i2c, 280 int reg, u8 mask, u8 val, 281 const unsigned long timeout) 282 { 283 unsigned long j; 284 285 j = jiffies + timeout; 286 while (1) { 287 u8 status = oc_getreg(i2c, reg); 288 289 if ((status & mask) == val) 290 break; 291 292 if (time_after(jiffies, j)) 293 return -ETIMEDOUT; 294 } 295 return 0; 296 } 297 298 /** 299 * Wait until is possible to process some data 300 * @i2c: ocores I2C device instance 301 * 302 * Used when the device is in polling mode (interrupts disabled). 303 * 304 * Return: 0 on success, -ETIMEDOUT on timeout 305 */ 306 static int ocores_poll_wait(struct ocores_i2c *i2c) 307 { 308 u8 mask; 309 int err; 310 311 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { 312 /* transfer is over */ 313 mask = OCI2C_STAT_BUSY; 314 } else { 315 /* on going transfer */ 316 mask = OCI2C_STAT_TIP; 317 /* 318 * We wait for the data to be transferred (8bit), 319 * then we start polling on the ACK/NACK bit 320 */ 321 udelay((8 * 1000) / i2c->bus_clock_khz); 322 } 323 324 /* 325 * once we are here we expect to get the expected result immediately 326 * so if after 1ms we timeout then something is broken. 327 */ 328 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); 329 if (err) 330 dev_warn(i2c->adap.dev.parent, 331 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", 332 __func__, mask); 333 return err; 334 } 335 336 /** 337 * It handles an IRQ-less transfer 338 * @i2c: ocores I2C device instance 339 * 340 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same 341 * (only that IRQ are not produced). This means that we can re-use entirely 342 * ocores_isr(), we just add our polling code around it. 343 * 344 * It can run in atomic context 345 */ 346 static void ocores_process_polling(struct ocores_i2c *i2c) 347 { 348 while (1) { 349 irqreturn_t ret; 350 int err; 351 352 err = ocores_poll_wait(i2c); 353 if (err) { 354 i2c->state = STATE_ERROR; 355 break; /* timeout */ 356 } 357 358 ret = ocores_isr(-1, i2c); 359 if (ret == IRQ_NONE) 360 break; /* all messages have been transferred */ 361 else { 362 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) 363 if (i2c->state == STATE_DONE) 364 break; 365 } 366 } 367 } 368 369 static int ocores_xfer_core(struct ocores_i2c *i2c, 370 struct i2c_msg *msgs, int num, 371 bool polling) 372 { 373 int ret; 374 u8 ctrl; 375 376 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 377 if (polling) 378 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); 379 else 380 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); 381 382 i2c->msg = msgs; 383 i2c->pos = 0; 384 i2c->nmsgs = num; 385 i2c->state = STATE_START; 386 387 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); 388 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 389 390 if (polling) { 391 ocores_process_polling(i2c); 392 } else { 393 ret = wait_event_timeout(i2c->wait, 394 (i2c->state == STATE_ERROR) || 395 (i2c->state == STATE_DONE), HZ); 396 if (ret == 0) { 397 ocores_process_timeout(i2c); 398 return -ETIMEDOUT; 399 } 400 } 401 402 return (i2c->state == STATE_DONE) ? num : -EIO; 403 } 404 405 static int ocores_xfer_polling(struct i2c_adapter *adap, 406 struct i2c_msg *msgs, int num) 407 { 408 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); 409 } 410 411 static int ocores_xfer(struct i2c_adapter *adap, 412 struct i2c_msg *msgs, int num) 413 { 414 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false); 415 } 416 417 static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 418 { 419 int prescale; 420 int diff; 421 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 422 423 /* make sure the device is disabled */ 424 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 425 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 426 427 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 428 prescale = clamp(prescale, 0, 0xffff); 429 430 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; 431 if (abs(diff) > i2c->bus_clock_khz / 10) { 432 dev_err(dev, 433 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", 434 i2c->ip_clock_khz, i2c->bus_clock_khz); 435 return -EINVAL; 436 } 437 438 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 439 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 440 441 /* Init the device */ 442 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 443 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); 444 445 return 0; 446 } 447 448 449 static u32 ocores_func(struct i2c_adapter *adap) 450 { 451 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 452 } 453 454 static struct i2c_algorithm ocores_algorithm = { 455 .master_xfer = ocores_xfer, 456 .master_xfer_atomic = ocores_xfer_polling, 457 .functionality = ocores_func, 458 }; 459 460 static const struct i2c_adapter ocores_adapter = { 461 .owner = THIS_MODULE, 462 .name = "i2c-ocores", 463 .class = I2C_CLASS_DEPRECATED, 464 .algo = &ocores_algorithm, 465 }; 466 467 static const struct of_device_id ocores_i2c_match[] = { 468 { 469 .compatible = "opencores,i2c-ocores", 470 .data = (void *)TYPE_OCORES, 471 }, 472 { 473 .compatible = "aeroflexgaisler,i2cmst", 474 .data = (void *)TYPE_GRLIB, 475 }, 476 { 477 .compatible = "sifive,fu540-c000-i2c", 478 }, 479 { 480 .compatible = "sifive,i2c0", 481 }, 482 {}, 483 }; 484 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 485 486 #ifdef CONFIG_OF 487 /* 488 * Read and write functions for the GRLIB port of the controller. Registers are 489 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one 490 * register. The subsequent registers have their offsets decreased accordingly. 491 */ 492 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) 493 { 494 u32 rd; 495 int rreg = reg; 496 497 if (reg != OCI2C_PRELOW) 498 rreg--; 499 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 500 if (reg == OCI2C_PREHIGH) 501 return (u8)(rd >> 8); 502 else 503 return (u8)rd; 504 } 505 506 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) 507 { 508 u32 curr, wr; 509 int rreg = reg; 510 511 if (reg != OCI2C_PRELOW) 512 rreg--; 513 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { 514 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 515 if (reg == OCI2C_PRELOW) 516 wr = (curr & 0xff00) | value; 517 else 518 wr = (((u32)value) << 8) | (curr & 0xff); 519 } else { 520 wr = value; 521 } 522 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); 523 } 524 525 static int ocores_i2c_of_probe(struct platform_device *pdev, 526 struct ocores_i2c *i2c) 527 { 528 struct device_node *np = pdev->dev.of_node; 529 const struct of_device_id *match; 530 u32 val; 531 u32 clock_frequency; 532 bool clock_frequency_present; 533 534 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 535 /* no 'reg-shift', check for deprecated 'regstep' */ 536 if (!of_property_read_u32(np, "regstep", &val)) { 537 if (!is_power_of_2(val)) { 538 dev_err(&pdev->dev, "invalid regstep %d\n", 539 val); 540 return -EINVAL; 541 } 542 i2c->reg_shift = ilog2(val); 543 dev_warn(&pdev->dev, 544 "regstep property deprecated, use reg-shift\n"); 545 } 546 } 547 548 clock_frequency_present = !of_property_read_u32(np, "clock-frequency", 549 &clock_frequency); 550 i2c->bus_clock_khz = 100; 551 552 i2c->clk = devm_clk_get(&pdev->dev, NULL); 553 554 if (!IS_ERR(i2c->clk)) { 555 int ret = clk_prepare_enable(i2c->clk); 556 557 if (ret) { 558 dev_err(&pdev->dev, 559 "clk_prepare_enable failed: %d\n", ret); 560 return ret; 561 } 562 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; 563 if (clock_frequency_present) 564 i2c->bus_clock_khz = clock_frequency / 1000; 565 } 566 567 if (i2c->ip_clock_khz == 0) { 568 if (of_property_read_u32(np, "opencores,ip-clock-frequency", 569 &val)) { 570 if (!clock_frequency_present) { 571 dev_err(&pdev->dev, 572 "Missing required parameter 'opencores,ip-clock-frequency'\n"); 573 clk_disable_unprepare(i2c->clk); 574 return -ENODEV; 575 } 576 i2c->ip_clock_khz = clock_frequency / 1000; 577 dev_warn(&pdev->dev, 578 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); 579 } else { 580 i2c->ip_clock_khz = val / 1000; 581 if (clock_frequency_present) 582 i2c->bus_clock_khz = clock_frequency / 1000; 583 } 584 } 585 586 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 587 &i2c->reg_io_width); 588 589 match = of_match_node(ocores_i2c_match, pdev->dev.of_node); 590 if (match && (long)match->data == TYPE_GRLIB) { 591 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); 592 i2c->setreg = oc_setreg_grlib; 593 i2c->getreg = oc_getreg_grlib; 594 } 595 596 return 0; 597 } 598 #else 599 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV 600 #endif 601 602 static int ocores_i2c_probe(struct platform_device *pdev) 603 { 604 struct ocores_i2c *i2c; 605 struct ocores_i2c_platform_data *pdata; 606 struct resource *res; 607 int irq; 608 int ret; 609 int i; 610 611 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 612 if (!i2c) 613 return -ENOMEM; 614 615 spin_lock_init(&i2c->process_lock); 616 617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 618 if (res) { 619 i2c->base = devm_ioremap_resource(&pdev->dev, res); 620 if (IS_ERR(i2c->base)) 621 return PTR_ERR(i2c->base); 622 } else { 623 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 624 if (!res) 625 return -EINVAL; 626 i2c->iobase = res->start; 627 if (!devm_request_region(&pdev->dev, res->start, 628 resource_size(res), 629 pdev->name)) { 630 dev_err(&pdev->dev, "Can't get I/O resource.\n"); 631 return -EBUSY; 632 } 633 i2c->setreg = oc_setreg_io_8; 634 i2c->getreg = oc_getreg_io_8; 635 } 636 637 pdata = dev_get_platdata(&pdev->dev); 638 if (pdata) { 639 i2c->reg_shift = pdata->reg_shift; 640 i2c->reg_io_width = pdata->reg_io_width; 641 i2c->ip_clock_khz = pdata->clock_khz; 642 if (pdata->bus_khz) 643 i2c->bus_clock_khz = pdata->bus_khz; 644 else 645 i2c->bus_clock_khz = 100; 646 } else { 647 ret = ocores_i2c_of_probe(pdev, i2c); 648 if (ret) 649 return ret; 650 } 651 652 if (i2c->reg_io_width == 0) 653 i2c->reg_io_width = 1; /* Set to default value */ 654 655 if (!i2c->setreg || !i2c->getreg) { 656 bool be = pdata ? pdata->big_endian : 657 of_device_is_big_endian(pdev->dev.of_node); 658 659 switch (i2c->reg_io_width) { 660 case 1: 661 i2c->setreg = oc_setreg_8; 662 i2c->getreg = oc_getreg_8; 663 break; 664 665 case 2: 666 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; 667 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; 668 break; 669 670 case 4: 671 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; 672 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; 673 break; 674 675 default: 676 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", 677 i2c->reg_io_width); 678 ret = -EINVAL; 679 goto err_clk; 680 } 681 } 682 683 init_waitqueue_head(&i2c->wait); 684 685 irq = platform_get_irq_optional(pdev, 0); 686 /* 687 * Since the SoC does have an interrupt, its DT has an interrupt 688 * property - But this should be bypassed as the IRQ logic in this 689 * SoC is broken. 690 */ 691 if (of_device_is_compatible(pdev->dev.of_node, 692 "sifive,fu540-c000-i2c")) { 693 i2c->flags |= OCORES_FLAG_BROKEN_IRQ; 694 irq = -ENXIO; 695 } 696 697 if (irq == -ENXIO) { 698 ocores_algorithm.master_xfer = ocores_xfer_polling; 699 } else { 700 if (irq < 0) 701 return irq; 702 } 703 704 if (ocores_algorithm.master_xfer != ocores_xfer_polling) { 705 ret = devm_request_any_context_irq(&pdev->dev, irq, 706 ocores_isr, 0, 707 pdev->name, i2c); 708 if (ret) { 709 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 710 goto err_clk; 711 } 712 } 713 714 ret = ocores_init(&pdev->dev, i2c); 715 if (ret) 716 goto err_clk; 717 718 /* hook up driver to tree */ 719 platform_set_drvdata(pdev, i2c); 720 i2c->adap = ocores_adapter; 721 i2c_set_adapdata(&i2c->adap, i2c); 722 i2c->adap.dev.parent = &pdev->dev; 723 i2c->adap.dev.of_node = pdev->dev.of_node; 724 725 /* add i2c adapter to i2c tree */ 726 ret = i2c_add_adapter(&i2c->adap); 727 if (ret) 728 goto err_clk; 729 730 /* add in known devices to the bus */ 731 if (pdata) { 732 for (i = 0; i < pdata->num_devices; i++) 733 i2c_new_client_device(&i2c->adap, pdata->devices + i); 734 } 735 736 return 0; 737 738 err_clk: 739 clk_disable_unprepare(i2c->clk); 740 return ret; 741 } 742 743 static int ocores_i2c_remove(struct platform_device *pdev) 744 { 745 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 746 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 747 748 /* disable i2c logic */ 749 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 750 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 751 752 /* remove adapter & data */ 753 i2c_del_adapter(&i2c->adap); 754 755 if (!IS_ERR(i2c->clk)) 756 clk_disable_unprepare(i2c->clk); 757 758 return 0; 759 } 760 761 #ifdef CONFIG_PM_SLEEP 762 static int ocores_i2c_suspend(struct device *dev) 763 { 764 struct ocores_i2c *i2c = dev_get_drvdata(dev); 765 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 766 767 /* make sure the device is disabled */ 768 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 769 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 770 771 if (!IS_ERR(i2c->clk)) 772 clk_disable_unprepare(i2c->clk); 773 return 0; 774 } 775 776 static int ocores_i2c_resume(struct device *dev) 777 { 778 struct ocores_i2c *i2c = dev_get_drvdata(dev); 779 780 if (!IS_ERR(i2c->clk)) { 781 unsigned long rate; 782 int ret = clk_prepare_enable(i2c->clk); 783 784 if (ret) { 785 dev_err(dev, 786 "clk_prepare_enable failed: %d\n", ret); 787 return ret; 788 } 789 rate = clk_get_rate(i2c->clk) / 1000; 790 if (rate) 791 i2c->ip_clock_khz = rate; 792 } 793 return ocores_init(dev, i2c); 794 } 795 796 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 797 #define OCORES_I2C_PM (&ocores_i2c_pm) 798 #else 799 #define OCORES_I2C_PM NULL 800 #endif 801 802 static struct platform_driver ocores_i2c_driver = { 803 .probe = ocores_i2c_probe, 804 .remove = ocores_i2c_remove, 805 .driver = { 806 .name = "ocores-i2c", 807 .of_match_table = ocores_i2c_match, 808 .pm = OCORES_I2C_PM, 809 }, 810 }; 811 812 module_platform_driver(ocores_i2c_driver); 813 814 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>"); 815 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 816 MODULE_LICENSE("GPL"); 817 MODULE_ALIAS("platform:ocores-i2c"); 818