1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 4 * (https://opencores.org/project/i2c/overview) 5 * 6 * Peter Korsgaard <peter@korsgaard.com> 7 * 8 * Support for the GRLIB port of the controller by 9 * Andreas Larsson <andreas@gaisler.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/errno.h> 18 #include <linux/platform_device.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/wait.h> 22 #include <linux/platform_data/i2c-ocores.h> 23 #include <linux/slab.h> 24 #include <linux/io.h> 25 #include <linux/log2.h> 26 #include <linux/spinlock.h> 27 #include <linux/jiffies.h> 28 29 #define OCORES_FLAG_POLL BIT(0) 30 31 /* 32 * 'process_lock' exists because ocores_process() and ocores_process_timeout() 33 * can't run in parallel. 34 */ 35 struct ocores_i2c { 36 void __iomem *base; 37 int iobase; 38 u32 reg_shift; 39 u32 reg_io_width; 40 unsigned long flags; 41 wait_queue_head_t wait; 42 struct i2c_adapter adap; 43 struct i2c_msg *msg; 44 int pos; 45 int nmsgs; 46 int state; /* see STATE_ */ 47 spinlock_t process_lock; 48 struct clk *clk; 49 int ip_clock_khz; 50 int bus_clock_khz; 51 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 52 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 53 }; 54 55 /* registers */ 56 #define OCI2C_PRELOW 0 57 #define OCI2C_PREHIGH 1 58 #define OCI2C_CONTROL 2 59 #define OCI2C_DATA 3 60 #define OCI2C_CMD 4 /* write only */ 61 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 62 63 #define OCI2C_CTRL_IEN 0x40 64 #define OCI2C_CTRL_EN 0x80 65 66 #define OCI2C_CMD_START 0x91 67 #define OCI2C_CMD_STOP 0x41 68 #define OCI2C_CMD_READ 0x21 69 #define OCI2C_CMD_WRITE 0x11 70 #define OCI2C_CMD_READ_ACK 0x21 71 #define OCI2C_CMD_READ_NACK 0x29 72 #define OCI2C_CMD_IACK 0x01 73 74 #define OCI2C_STAT_IF 0x01 75 #define OCI2C_STAT_TIP 0x02 76 #define OCI2C_STAT_ARBLOST 0x20 77 #define OCI2C_STAT_BUSY 0x40 78 #define OCI2C_STAT_NACK 0x80 79 80 #define STATE_DONE 0 81 #define STATE_START 1 82 #define STATE_WRITE 2 83 #define STATE_READ 3 84 #define STATE_ERROR 4 85 86 #define TYPE_OCORES 0 87 #define TYPE_GRLIB 1 88 89 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) 90 { 91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 92 } 93 94 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) 95 { 96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 97 } 98 99 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) 100 { 101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 102 } 103 104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) 105 { 106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); 107 } 108 109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) 110 { 111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); 112 } 113 114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) 115 { 116 return ioread8(i2c->base + (reg << i2c->reg_shift)); 117 } 118 119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) 120 { 121 return ioread16(i2c->base + (reg << i2c->reg_shift)); 122 } 123 124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) 125 { 126 return ioread32(i2c->base + (reg << i2c->reg_shift)); 127 } 128 129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) 130 { 131 return ioread16be(i2c->base + (reg << i2c->reg_shift)); 132 } 133 134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) 135 { 136 return ioread32be(i2c->base + (reg << i2c->reg_shift)); 137 } 138 139 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value) 140 { 141 outb(value, i2c->iobase + reg); 142 } 143 144 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg) 145 { 146 return inb(i2c->iobase + reg); 147 } 148 149 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 150 { 151 i2c->setreg(i2c, reg, value); 152 } 153 154 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 155 { 156 return i2c->getreg(i2c, reg); 157 } 158 159 static void ocores_process(struct ocores_i2c *i2c, u8 stat) 160 { 161 struct i2c_msg *msg = i2c->msg; 162 unsigned long flags; 163 164 /* 165 * If we spin here is because we are in timeout, so we are going 166 * to be in STATE_ERROR. See ocores_process_timeout() 167 */ 168 spin_lock_irqsave(&i2c->process_lock, flags); 169 170 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 171 /* stop has been sent */ 172 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 173 wake_up(&i2c->wait); 174 goto out; 175 } 176 177 /* error? */ 178 if (stat & OCI2C_STAT_ARBLOST) { 179 i2c->state = STATE_ERROR; 180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 181 goto out; 182 } 183 184 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 185 i2c->state = 186 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 187 188 if (stat & OCI2C_STAT_NACK) { 189 i2c->state = STATE_ERROR; 190 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 191 goto out; 192 } 193 } else { 194 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 195 } 196 197 /* end of msg? */ 198 if (i2c->pos == msg->len) { 199 i2c->nmsgs--; 200 i2c->msg++; 201 i2c->pos = 0; 202 msg = i2c->msg; 203 204 if (i2c->nmsgs) { /* end? */ 205 /* send start? */ 206 if (!(msg->flags & I2C_M_NOSTART)) { 207 u8 addr = i2c_8bit_addr_from_msg(msg); 208 209 i2c->state = STATE_START; 210 211 oc_setreg(i2c, OCI2C_DATA, addr); 212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 213 goto out; 214 } 215 i2c->state = (msg->flags & I2C_M_RD) 216 ? STATE_READ : STATE_WRITE; 217 } else { 218 i2c->state = STATE_DONE; 219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 220 goto out; 221 } 222 } 223 224 if (i2c->state == STATE_READ) { 225 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 226 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 227 } else { 228 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 229 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 230 } 231 232 out: 233 spin_unlock_irqrestore(&i2c->process_lock, flags); 234 } 235 236 static irqreturn_t ocores_isr(int irq, void *dev_id) 237 { 238 struct ocores_i2c *i2c = dev_id; 239 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 240 241 if (!(stat & OCI2C_STAT_IF)) 242 return IRQ_NONE; 243 244 ocores_process(i2c, stat); 245 246 return IRQ_HANDLED; 247 } 248 249 /** 250 * Process timeout event 251 * @i2c: ocores I2C device instance 252 */ 253 static void ocores_process_timeout(struct ocores_i2c *i2c) 254 { 255 unsigned long flags; 256 257 spin_lock_irqsave(&i2c->process_lock, flags); 258 i2c->state = STATE_ERROR; 259 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 260 spin_unlock_irqrestore(&i2c->process_lock, flags); 261 } 262 263 /** 264 * Wait until something change in a given register 265 * @i2c: ocores I2C device instance 266 * @reg: register to query 267 * @mask: bitmask to apply on register value 268 * @val: expected result 269 * @timeout: timeout in jiffies 270 * 271 * Timeout is necessary to avoid to stay here forever when the chip 272 * does not answer correctly. 273 * 274 * Return: 0 on success, -ETIMEDOUT on timeout 275 */ 276 static int ocores_wait(struct ocores_i2c *i2c, 277 int reg, u8 mask, u8 val, 278 const unsigned long timeout) 279 { 280 unsigned long j; 281 282 j = jiffies + timeout; 283 while (1) { 284 u8 status = oc_getreg(i2c, reg); 285 286 if ((status & mask) == val) 287 break; 288 289 if (time_after(jiffies, j)) 290 return -ETIMEDOUT; 291 } 292 return 0; 293 } 294 295 /** 296 * Wait until is possible to process some data 297 * @i2c: ocores I2C device instance 298 * 299 * Used when the device is in polling mode (interrupts disabled). 300 * 301 * Return: 0 on success, -ETIMEDOUT on timeout 302 */ 303 static int ocores_poll_wait(struct ocores_i2c *i2c) 304 { 305 u8 mask; 306 int err; 307 308 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { 309 /* transfer is over */ 310 mask = OCI2C_STAT_BUSY; 311 } else { 312 /* on going transfer */ 313 mask = OCI2C_STAT_TIP; 314 /* 315 * We wait for the data to be transferred (8bit), 316 * then we start polling on the ACK/NACK bit 317 */ 318 udelay((8 * 1000) / i2c->bus_clock_khz); 319 } 320 321 /* 322 * once we are here we expect to get the expected result immediately 323 * so if after 1ms we timeout then something is broken. 324 */ 325 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); 326 if (err) 327 dev_warn(i2c->adap.dev.parent, 328 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", 329 __func__, mask); 330 return err; 331 } 332 333 /** 334 * It handles an IRQ-less transfer 335 * @i2c: ocores I2C device instance 336 * 337 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same 338 * (only that IRQ are not produced). This means that we can re-use entirely 339 * ocores_isr(), we just add our polling code around it. 340 * 341 * It can run in atomic context 342 */ 343 static void ocores_process_polling(struct ocores_i2c *i2c) 344 { 345 while (1) { 346 irqreturn_t ret; 347 int err; 348 349 err = ocores_poll_wait(i2c); 350 if (err) { 351 i2c->state = STATE_ERROR; 352 break; /* timeout */ 353 } 354 355 ret = ocores_isr(-1, i2c); 356 if (ret == IRQ_NONE) 357 break; /* all messages have been transferred */ 358 } 359 } 360 361 static int ocores_xfer_core(struct ocores_i2c *i2c, 362 struct i2c_msg *msgs, int num, 363 bool polling) 364 { 365 int ret; 366 u8 ctrl; 367 368 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 369 if (polling) 370 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); 371 else 372 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); 373 374 i2c->msg = msgs; 375 i2c->pos = 0; 376 i2c->nmsgs = num; 377 i2c->state = STATE_START; 378 379 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); 380 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 381 382 if (polling) { 383 ocores_process_polling(i2c); 384 } else { 385 ret = wait_event_timeout(i2c->wait, 386 (i2c->state == STATE_ERROR) || 387 (i2c->state == STATE_DONE), HZ); 388 if (ret == 0) { 389 ocores_process_timeout(i2c); 390 return -ETIMEDOUT; 391 } 392 } 393 394 return (i2c->state == STATE_DONE) ? num : -EIO; 395 } 396 397 static int ocores_xfer_polling(struct i2c_adapter *adap, 398 struct i2c_msg *msgs, int num) 399 { 400 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); 401 } 402 403 static int ocores_xfer(struct i2c_adapter *adap, 404 struct i2c_msg *msgs, int num) 405 { 406 struct ocores_i2c *i2c = i2c_get_adapdata(adap); 407 408 if (i2c->flags & OCORES_FLAG_POLL) 409 return ocores_xfer_polling(adap, msgs, num); 410 return ocores_xfer_core(i2c, msgs, num, false); 411 } 412 413 static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 414 { 415 int prescale; 416 int diff; 417 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 418 419 /* make sure the device is disabled */ 420 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 421 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 422 423 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 424 prescale = clamp(prescale, 0, 0xffff); 425 426 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; 427 if (abs(diff) > i2c->bus_clock_khz / 10) { 428 dev_err(dev, 429 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", 430 i2c->ip_clock_khz, i2c->bus_clock_khz); 431 return -EINVAL; 432 } 433 434 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 435 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 436 437 /* Init the device */ 438 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 439 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); 440 441 return 0; 442 } 443 444 445 static u32 ocores_func(struct i2c_adapter *adap) 446 { 447 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 448 } 449 450 static const struct i2c_algorithm ocores_algorithm = { 451 .master_xfer = ocores_xfer, 452 .functionality = ocores_func, 453 }; 454 455 static const struct i2c_adapter ocores_adapter = { 456 .owner = THIS_MODULE, 457 .name = "i2c-ocores", 458 .class = I2C_CLASS_DEPRECATED, 459 .algo = &ocores_algorithm, 460 }; 461 462 static const struct of_device_id ocores_i2c_match[] = { 463 { 464 .compatible = "opencores,i2c-ocores", 465 .data = (void *)TYPE_OCORES, 466 }, 467 { 468 .compatible = "aeroflexgaisler,i2cmst", 469 .data = (void *)TYPE_GRLIB, 470 }, 471 {}, 472 }; 473 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 474 475 #ifdef CONFIG_OF 476 /* 477 * Read and write functions for the GRLIB port of the controller. Registers are 478 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one 479 * register. The subsequent registers have their offsets decreased accordingly. 480 */ 481 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) 482 { 483 u32 rd; 484 int rreg = reg; 485 486 if (reg != OCI2C_PRELOW) 487 rreg--; 488 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 489 if (reg == OCI2C_PREHIGH) 490 return (u8)(rd >> 8); 491 else 492 return (u8)rd; 493 } 494 495 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) 496 { 497 u32 curr, wr; 498 int rreg = reg; 499 500 if (reg != OCI2C_PRELOW) 501 rreg--; 502 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { 503 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 504 if (reg == OCI2C_PRELOW) 505 wr = (curr & 0xff00) | value; 506 else 507 wr = (((u32)value) << 8) | (curr & 0xff); 508 } else { 509 wr = value; 510 } 511 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); 512 } 513 514 static int ocores_i2c_of_probe(struct platform_device *pdev, 515 struct ocores_i2c *i2c) 516 { 517 struct device_node *np = pdev->dev.of_node; 518 const struct of_device_id *match; 519 u32 val; 520 u32 clock_frequency; 521 bool clock_frequency_present; 522 523 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 524 /* no 'reg-shift', check for deprecated 'regstep' */ 525 if (!of_property_read_u32(np, "regstep", &val)) { 526 if (!is_power_of_2(val)) { 527 dev_err(&pdev->dev, "invalid regstep %d\n", 528 val); 529 return -EINVAL; 530 } 531 i2c->reg_shift = ilog2(val); 532 dev_warn(&pdev->dev, 533 "regstep property deprecated, use reg-shift\n"); 534 } 535 } 536 537 clock_frequency_present = !of_property_read_u32(np, "clock-frequency", 538 &clock_frequency); 539 i2c->bus_clock_khz = 100; 540 541 i2c->clk = devm_clk_get(&pdev->dev, NULL); 542 543 if (!IS_ERR(i2c->clk)) { 544 int ret = clk_prepare_enable(i2c->clk); 545 546 if (ret) { 547 dev_err(&pdev->dev, 548 "clk_prepare_enable failed: %d\n", ret); 549 return ret; 550 } 551 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; 552 if (clock_frequency_present) 553 i2c->bus_clock_khz = clock_frequency / 1000; 554 } 555 556 if (i2c->ip_clock_khz == 0) { 557 if (of_property_read_u32(np, "opencores,ip-clock-frequency", 558 &val)) { 559 if (!clock_frequency_present) { 560 dev_err(&pdev->dev, 561 "Missing required parameter 'opencores,ip-clock-frequency'\n"); 562 clk_disable_unprepare(i2c->clk); 563 return -ENODEV; 564 } 565 i2c->ip_clock_khz = clock_frequency / 1000; 566 dev_warn(&pdev->dev, 567 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); 568 } else { 569 i2c->ip_clock_khz = val / 1000; 570 if (clock_frequency_present) 571 i2c->bus_clock_khz = clock_frequency / 1000; 572 } 573 } 574 575 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 576 &i2c->reg_io_width); 577 578 match = of_match_node(ocores_i2c_match, pdev->dev.of_node); 579 if (match && (long)match->data == TYPE_GRLIB) { 580 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); 581 i2c->setreg = oc_setreg_grlib; 582 i2c->getreg = oc_getreg_grlib; 583 } 584 585 return 0; 586 } 587 #else 588 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV 589 #endif 590 591 static int ocores_i2c_probe(struct platform_device *pdev) 592 { 593 struct ocores_i2c *i2c; 594 struct ocores_i2c_platform_data *pdata; 595 struct resource *res; 596 int irq; 597 int ret; 598 int i; 599 600 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 601 if (!i2c) 602 return -ENOMEM; 603 604 spin_lock_init(&i2c->process_lock); 605 606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 607 if (res) { 608 i2c->base = devm_ioremap_resource(&pdev->dev, res); 609 if (IS_ERR(i2c->base)) 610 return PTR_ERR(i2c->base); 611 } else { 612 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 613 if (!res) 614 return -EINVAL; 615 i2c->iobase = res->start; 616 if (!devm_request_region(&pdev->dev, res->start, 617 resource_size(res), 618 pdev->name)) { 619 dev_err(&pdev->dev, "Can't get I/O resource.\n"); 620 return -EBUSY; 621 } 622 i2c->setreg = oc_setreg_io_8; 623 i2c->getreg = oc_getreg_io_8; 624 } 625 626 pdata = dev_get_platdata(&pdev->dev); 627 if (pdata) { 628 i2c->reg_shift = pdata->reg_shift; 629 i2c->reg_io_width = pdata->reg_io_width; 630 i2c->ip_clock_khz = pdata->clock_khz; 631 if (pdata->bus_khz) 632 i2c->bus_clock_khz = pdata->bus_khz; 633 else 634 i2c->bus_clock_khz = 100; 635 } else { 636 ret = ocores_i2c_of_probe(pdev, i2c); 637 if (ret) 638 return ret; 639 } 640 641 if (i2c->reg_io_width == 0) 642 i2c->reg_io_width = 1; /* Set to default value */ 643 644 if (!i2c->setreg || !i2c->getreg) { 645 bool be = pdata ? pdata->big_endian : 646 of_device_is_big_endian(pdev->dev.of_node); 647 648 switch (i2c->reg_io_width) { 649 case 1: 650 i2c->setreg = oc_setreg_8; 651 i2c->getreg = oc_getreg_8; 652 break; 653 654 case 2: 655 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; 656 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; 657 break; 658 659 case 4: 660 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; 661 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; 662 break; 663 664 default: 665 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", 666 i2c->reg_io_width); 667 ret = -EINVAL; 668 goto err_clk; 669 } 670 } 671 672 init_waitqueue_head(&i2c->wait); 673 674 irq = platform_get_irq(pdev, 0); 675 if (irq == -ENXIO) { 676 i2c->flags |= OCORES_FLAG_POLL; 677 } else { 678 if (irq < 0) 679 return irq; 680 } 681 682 if (!(i2c->flags & OCORES_FLAG_POLL)) { 683 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, 684 pdev->name, i2c); 685 if (ret) { 686 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 687 goto err_clk; 688 } 689 } 690 691 ret = ocores_init(&pdev->dev, i2c); 692 if (ret) 693 goto err_clk; 694 695 /* hook up driver to tree */ 696 platform_set_drvdata(pdev, i2c); 697 i2c->adap = ocores_adapter; 698 i2c_set_adapdata(&i2c->adap, i2c); 699 i2c->adap.dev.parent = &pdev->dev; 700 i2c->adap.dev.of_node = pdev->dev.of_node; 701 702 /* add i2c adapter to i2c tree */ 703 ret = i2c_add_adapter(&i2c->adap); 704 if (ret) 705 goto err_clk; 706 707 /* add in known devices to the bus */ 708 if (pdata) { 709 for (i = 0; i < pdata->num_devices; i++) 710 i2c_new_device(&i2c->adap, pdata->devices + i); 711 } 712 713 return 0; 714 715 err_clk: 716 clk_disable_unprepare(i2c->clk); 717 return ret; 718 } 719 720 static int ocores_i2c_remove(struct platform_device *pdev) 721 { 722 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 723 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 724 725 /* disable i2c logic */ 726 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 727 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 728 729 /* remove adapter & data */ 730 i2c_del_adapter(&i2c->adap); 731 732 if (!IS_ERR(i2c->clk)) 733 clk_disable_unprepare(i2c->clk); 734 735 return 0; 736 } 737 738 #ifdef CONFIG_PM_SLEEP 739 static int ocores_i2c_suspend(struct device *dev) 740 { 741 struct ocores_i2c *i2c = dev_get_drvdata(dev); 742 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 743 744 /* make sure the device is disabled */ 745 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 746 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 747 748 if (!IS_ERR(i2c->clk)) 749 clk_disable_unprepare(i2c->clk); 750 return 0; 751 } 752 753 static int ocores_i2c_resume(struct device *dev) 754 { 755 struct ocores_i2c *i2c = dev_get_drvdata(dev); 756 757 if (!IS_ERR(i2c->clk)) { 758 unsigned long rate; 759 int ret = clk_prepare_enable(i2c->clk); 760 761 if (ret) { 762 dev_err(dev, 763 "clk_prepare_enable failed: %d\n", ret); 764 return ret; 765 } 766 rate = clk_get_rate(i2c->clk) / 1000; 767 if (rate) 768 i2c->ip_clock_khz = rate; 769 } 770 return ocores_init(dev, i2c); 771 } 772 773 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 774 #define OCORES_I2C_PM (&ocores_i2c_pm) 775 #else 776 #define OCORES_I2C_PM NULL 777 #endif 778 779 static struct platform_driver ocores_i2c_driver = { 780 .probe = ocores_i2c_probe, 781 .remove = ocores_i2c_remove, 782 .driver = { 783 .name = "ocores-i2c", 784 .of_match_table = ocores_i2c_match, 785 .pm = OCORES_I2C_PM, 786 }, 787 }; 788 789 module_platform_driver(ocores_i2c_driver); 790 791 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>"); 792 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 793 MODULE_LICENSE("GPL"); 794 MODULE_ALIAS("platform:ocores-i2c"); 795