1c71bcdcbSAjay Gupta // SPDX-License-Identifier: GPL-2.0 2c71bcdcbSAjay Gupta /* 3c71bcdcbSAjay Gupta * Nvidia GPU I2C controller Driver 4c71bcdcbSAjay Gupta * 5c71bcdcbSAjay Gupta * Copyright (C) 2018 NVIDIA Corporation. All rights reserved. 6c71bcdcbSAjay Gupta * Author: Ajay Gupta <ajayg@nvidia.com> 7c71bcdcbSAjay Gupta */ 8c71bcdcbSAjay Gupta #include <linux/delay.h> 9c71bcdcbSAjay Gupta #include <linux/i2c.h> 10c71bcdcbSAjay Gupta #include <linux/interrupt.h> 11d944b27dSKai-Heng Feng #include <linux/iopoll.h> 12c71bcdcbSAjay Gupta #include <linux/module.h> 13c71bcdcbSAjay Gupta #include <linux/pci.h> 14c71bcdcbSAjay Gupta #include <linux/platform_device.h> 15c71bcdcbSAjay Gupta #include <linux/pm.h> 16c71bcdcbSAjay Gupta #include <linux/pm_runtime.h> 17c71bcdcbSAjay Gupta 18c71bcdcbSAjay Gupta #include <asm/unaligned.h> 19c71bcdcbSAjay Gupta 20*2079563dSAndy Shevchenko #include "i2c-ccgx-ucsi.h" 21*2079563dSAndy Shevchenko 22c71bcdcbSAjay Gupta /* I2C definitions */ 23c71bcdcbSAjay Gupta #define I2C_MST_CNTL 0x00 24c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_START BIT(0) 25c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_STOP BIT(1) 26c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CMD_READ (1 << 2) 27c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CMD_WRITE (2 << 2) 28c71bcdcbSAjay Gupta #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6 29c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_NACK BIT(28) 30c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS GENMASK(30, 29) 31c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_OKAY (0 << 29) 32c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29) 33c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29) 34c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29) 35c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31) 36c71bcdcbSAjay Gupta 37c71bcdcbSAjay Gupta #define I2C_MST_ADDR 0x04 38c71bcdcbSAjay Gupta 39c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING 0x08 40c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e 41c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16 42c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255 43c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24) 44c71bcdcbSAjay Gupta 45c71bcdcbSAjay Gupta #define I2C_MST_DATA 0x0c 46c71bcdcbSAjay Gupta 47c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL 0x20 48c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0) 49c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14) 50c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15) 51c71bcdcbSAjay Gupta 52c71bcdcbSAjay Gupta struct gpu_i2c_dev { 53c71bcdcbSAjay Gupta struct device *dev; 54c71bcdcbSAjay Gupta void __iomem *regs; 55c71bcdcbSAjay Gupta struct i2c_adapter adapter; 56c71bcdcbSAjay Gupta struct i2c_board_info *gpu_ccgx_ucsi; 579f2e244dSAjay Gupta struct i2c_client *ccgx_client; 58c71bcdcbSAjay Gupta }; 59c71bcdcbSAjay Gupta 60c71bcdcbSAjay Gupta static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd) 61c71bcdcbSAjay Gupta { 62c71bcdcbSAjay Gupta u32 val; 63c71bcdcbSAjay Gupta 64c71bcdcbSAjay Gupta /* enable I2C */ 65c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL); 66c71bcdcbSAjay Gupta val |= I2C_MST_HYBRID_PADCTL_MODE_I2C | 67c71bcdcbSAjay Gupta I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | 68c71bcdcbSAjay Gupta I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV; 69c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL); 70c71bcdcbSAjay Gupta 71c71bcdcbSAjay Gupta /* enable 100KHZ mode */ 72c71bcdcbSAjay Gupta val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ; 73c71bcdcbSAjay Gupta val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 74c71bcdcbSAjay Gupta << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT); 75c71bcdcbSAjay Gupta val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK; 76c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_I2C0_TIMING); 77c71bcdcbSAjay Gupta } 78c71bcdcbSAjay Gupta 79c71bcdcbSAjay Gupta static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd) 80c71bcdcbSAjay Gupta { 81c71bcdcbSAjay Gupta u32 val; 82d944b27dSKai-Heng Feng int ret; 83c71bcdcbSAjay Gupta 84d944b27dSKai-Heng Feng ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val, 85d944b27dSKai-Heng Feng !(val & I2C_MST_CNTL_CYCLE_TRIGGER) || 86d944b27dSKai-Heng Feng (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY, 87d944b27dSKai-Heng Feng 500, 1000 * USEC_PER_MSEC); 88c71bcdcbSAjay Gupta 89d944b27dSKai-Heng Feng if (ret) { 90c71bcdcbSAjay Gupta dev_err(i2cd->dev, "i2c timeout error %x\n", val); 9198be694bSWolfram Sang return -ETIMEDOUT; 92c71bcdcbSAjay Gupta } 93c71bcdcbSAjay Gupta 94c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_CNTL); 95c71bcdcbSAjay Gupta switch (val & I2C_MST_CNTL_STATUS) { 96c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_OKAY: 97c71bcdcbSAjay Gupta return 0; 98c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_NO_ACK: 9998be694bSWolfram Sang return -ENXIO; 100c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_TIMEOUT: 10198be694bSWolfram Sang return -ETIMEDOUT; 102c71bcdcbSAjay Gupta default: 103c71bcdcbSAjay Gupta return 0; 104c71bcdcbSAjay Gupta } 105c71bcdcbSAjay Gupta } 106c71bcdcbSAjay Gupta 107c71bcdcbSAjay Gupta static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len) 108c71bcdcbSAjay Gupta { 109c71bcdcbSAjay Gupta int status; 110c71bcdcbSAjay Gupta u32 val; 111c71bcdcbSAjay Gupta 112c71bcdcbSAjay Gupta val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ | 113c71bcdcbSAjay Gupta (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) | 114c71bcdcbSAjay Gupta I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK; 115c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_CNTL); 116c71bcdcbSAjay Gupta 117c71bcdcbSAjay Gupta status = gpu_i2c_check_status(i2cd); 118c71bcdcbSAjay Gupta if (status < 0) 119c71bcdcbSAjay Gupta return status; 120c71bcdcbSAjay Gupta 121c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_DATA); 122c71bcdcbSAjay Gupta switch (len) { 123c71bcdcbSAjay Gupta case 1: 124c71bcdcbSAjay Gupta data[0] = val; 125c71bcdcbSAjay Gupta break; 126c71bcdcbSAjay Gupta case 2: 127c71bcdcbSAjay Gupta put_unaligned_be16(val, data); 128c71bcdcbSAjay Gupta break; 129c71bcdcbSAjay Gupta case 3: 1309b65b020SAndy Shevchenko put_unaligned_be24(val, data); 131c71bcdcbSAjay Gupta break; 132c71bcdcbSAjay Gupta case 4: 133c71bcdcbSAjay Gupta put_unaligned_be32(val, data); 134c71bcdcbSAjay Gupta break; 135c71bcdcbSAjay Gupta default: 136c71bcdcbSAjay Gupta break; 137c71bcdcbSAjay Gupta } 138c71bcdcbSAjay Gupta return status; 139c71bcdcbSAjay Gupta } 140c71bcdcbSAjay Gupta 141c71bcdcbSAjay Gupta static int gpu_i2c_start(struct gpu_i2c_dev *i2cd) 142c71bcdcbSAjay Gupta { 143c71bcdcbSAjay Gupta writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL); 144c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd); 145c71bcdcbSAjay Gupta } 146c71bcdcbSAjay Gupta 147c71bcdcbSAjay Gupta static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd) 148c71bcdcbSAjay Gupta { 149c71bcdcbSAjay Gupta writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL); 150c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd); 151c71bcdcbSAjay Gupta } 152c71bcdcbSAjay Gupta 153c71bcdcbSAjay Gupta static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data) 154c71bcdcbSAjay Gupta { 155c71bcdcbSAjay Gupta u32 val; 156c71bcdcbSAjay Gupta 157c71bcdcbSAjay Gupta writel(data, i2cd->regs + I2C_MST_DATA); 158c71bcdcbSAjay Gupta 159c71bcdcbSAjay Gupta val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT); 160c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_CNTL); 161c71bcdcbSAjay Gupta 162c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd); 163c71bcdcbSAjay Gupta } 164c71bcdcbSAjay Gupta 165c71bcdcbSAjay Gupta static int gpu_i2c_master_xfer(struct i2c_adapter *adap, 166c71bcdcbSAjay Gupta struct i2c_msg *msgs, int num) 167c71bcdcbSAjay Gupta { 168c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap); 169c71bcdcbSAjay Gupta int status, status2; 170cb7302fbSAjay Gupta bool send_stop = true; 171c71bcdcbSAjay Gupta int i, j; 172c71bcdcbSAjay Gupta 173c71bcdcbSAjay Gupta /* 174c71bcdcbSAjay Gupta * The controller supports maximum 4 byte read due to known 175c71bcdcbSAjay Gupta * limitation of sending STOP after every read. 176c71bcdcbSAjay Gupta */ 177d4a4f927SAjay Gupta pm_runtime_get_sync(i2cd->dev); 178c71bcdcbSAjay Gupta for (i = 0; i < num; i++) { 179c71bcdcbSAjay Gupta if (msgs[i].flags & I2C_M_RD) { 180c71bcdcbSAjay Gupta /* program client address before starting read */ 181c71bcdcbSAjay Gupta writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR); 182c71bcdcbSAjay Gupta /* gpu_i2c_read has implicit start */ 183c71bcdcbSAjay Gupta status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len); 184c71bcdcbSAjay Gupta if (status < 0) 185cb7302fbSAjay Gupta goto exit; 186c71bcdcbSAjay Gupta } else { 187c71bcdcbSAjay Gupta u8 addr = i2c_8bit_addr_from_msg(msgs + i); 188c71bcdcbSAjay Gupta 189c71bcdcbSAjay Gupta status = gpu_i2c_start(i2cd); 190c71bcdcbSAjay Gupta if (status < 0) { 191c71bcdcbSAjay Gupta if (i == 0) 192cb7302fbSAjay Gupta send_stop = false; 193cb7302fbSAjay Gupta goto exit; 194c71bcdcbSAjay Gupta } 195c71bcdcbSAjay Gupta 196c71bcdcbSAjay Gupta status = gpu_i2c_write(i2cd, addr); 197c71bcdcbSAjay Gupta if (status < 0) 198cb7302fbSAjay Gupta goto exit; 199c71bcdcbSAjay Gupta 200c71bcdcbSAjay Gupta for (j = 0; j < msgs[i].len; j++) { 201c71bcdcbSAjay Gupta status = gpu_i2c_write(i2cd, msgs[i].buf[j]); 202c71bcdcbSAjay Gupta if (status < 0) 203cb7302fbSAjay Gupta goto exit; 204c71bcdcbSAjay Gupta } 205c71bcdcbSAjay Gupta } 206c71bcdcbSAjay Gupta } 207cb7302fbSAjay Gupta send_stop = false; 208c71bcdcbSAjay Gupta status = gpu_i2c_stop(i2cd); 209c71bcdcbSAjay Gupta if (status < 0) 210cb7302fbSAjay Gupta goto exit; 211c71bcdcbSAjay Gupta 212cb7302fbSAjay Gupta status = i; 213cb7302fbSAjay Gupta exit: 214cb7302fbSAjay Gupta if (send_stop) { 215c71bcdcbSAjay Gupta status2 = gpu_i2c_stop(i2cd); 216c71bcdcbSAjay Gupta if (status2 < 0) 217c71bcdcbSAjay Gupta dev_err(i2cd->dev, "i2c stop failed %d\n", status2); 218cb7302fbSAjay Gupta } 219d4a4f927SAjay Gupta pm_runtime_mark_last_busy(i2cd->dev); 220d4a4f927SAjay Gupta pm_runtime_put_autosuspend(i2cd->dev); 221c71bcdcbSAjay Gupta return status; 222c71bcdcbSAjay Gupta } 223c71bcdcbSAjay Gupta 224c71bcdcbSAjay Gupta static const struct i2c_adapter_quirks gpu_i2c_quirks = { 225c71bcdcbSAjay Gupta .max_read_len = 4, 22639129f28SWolfram Sang .max_comb_2nd_msg_len = 4, 227c71bcdcbSAjay Gupta .flags = I2C_AQ_COMB_WRITE_THEN_READ, 228c71bcdcbSAjay Gupta }; 229c71bcdcbSAjay Gupta 230c71bcdcbSAjay Gupta static u32 gpu_i2c_functionality(struct i2c_adapter *adap) 231c71bcdcbSAjay Gupta { 232c71bcdcbSAjay Gupta return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 233c71bcdcbSAjay Gupta } 234c71bcdcbSAjay Gupta 235c71bcdcbSAjay Gupta static const struct i2c_algorithm gpu_i2c_algorithm = { 236c71bcdcbSAjay Gupta .master_xfer = gpu_i2c_master_xfer, 237c71bcdcbSAjay Gupta .functionality = gpu_i2c_functionality, 238c71bcdcbSAjay Gupta }; 239c71bcdcbSAjay Gupta 240c71bcdcbSAjay Gupta /* 241c71bcdcbSAjay Gupta * This driver is for Nvidia GPU cards with USB Type-C interface. 242c71bcdcbSAjay Gupta * We want to identify the cards using vendor ID and class code only 243c71bcdcbSAjay Gupta * to avoid dependency of adding product id for any new card which 244c71bcdcbSAjay Gupta * requires this driver. 245c71bcdcbSAjay Gupta * Currently there is no class code defined for UCSI device over PCI 246c71bcdcbSAjay Gupta * so using UNKNOWN class for now and it will be updated when UCSI 247c71bcdcbSAjay Gupta * over PCI gets a class code. 248c71bcdcbSAjay Gupta * There is no other NVIDIA cards with UNKNOWN class code. Even if the 249c71bcdcbSAjay Gupta * driver gets loaded for an undesired card then eventually i2c_read() 250c71bcdcbSAjay Gupta * (initiated from UCSI i2c_client) will timeout or UCSI commands will 251c71bcdcbSAjay Gupta * timeout. 252c71bcdcbSAjay Gupta */ 253c71bcdcbSAjay Gupta #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 254c71bcdcbSAjay Gupta static const struct pci_device_id gpu_i2c_ids[] = { 255c71bcdcbSAjay Gupta { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 256c71bcdcbSAjay Gupta PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00}, 257c71bcdcbSAjay Gupta { } 258c71bcdcbSAjay Gupta }; 259c71bcdcbSAjay Gupta MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); 260c71bcdcbSAjay Gupta 2615fd958a4SAjay Gupta static const struct property_entry ccgx_props[] = { 2625fd958a4SAjay Gupta /* Use FW built for NVIDIA (nv) only */ 2635fd958a4SAjay Gupta PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), 2645fd958a4SAjay Gupta { } 2655fd958a4SAjay Gupta }; 2665fd958a4SAjay Gupta 267239798f5SHeikki Krogerus static const struct software_node ccgx_node = { 268239798f5SHeikki Krogerus .properties = ccgx_props, 269239798f5SHeikki Krogerus }; 270239798f5SHeikki Krogerus 271c71bcdcbSAjay Gupta static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id) 272c71bcdcbSAjay Gupta { 273c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd; 274c71bcdcbSAjay Gupta int status; 275c71bcdcbSAjay Gupta 276c71bcdcbSAjay Gupta i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL); 277c71bcdcbSAjay Gupta if (!i2cd) 278c71bcdcbSAjay Gupta return -ENOMEM; 279c71bcdcbSAjay Gupta 280c71bcdcbSAjay Gupta i2cd->dev = &pdev->dev; 281c71bcdcbSAjay Gupta dev_set_drvdata(&pdev->dev, i2cd); 282c71bcdcbSAjay Gupta 283c71bcdcbSAjay Gupta status = pcim_enable_device(pdev); 284c71bcdcbSAjay Gupta if (status < 0) { 285c71bcdcbSAjay Gupta dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status); 286c71bcdcbSAjay Gupta return status; 287c71bcdcbSAjay Gupta } 288c71bcdcbSAjay Gupta 289c71bcdcbSAjay Gupta pci_set_master(pdev); 290c71bcdcbSAjay Gupta 291c71bcdcbSAjay Gupta i2cd->regs = pcim_iomap(pdev, 0, 0); 292c71bcdcbSAjay Gupta if (!i2cd->regs) { 293c71bcdcbSAjay Gupta dev_err(&pdev->dev, "pcim_iomap failed\n"); 294c71bcdcbSAjay Gupta return -ENOMEM; 295c71bcdcbSAjay Gupta } 296c71bcdcbSAjay Gupta 297c71bcdcbSAjay Gupta status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 298c71bcdcbSAjay Gupta if (status < 0) { 299c71bcdcbSAjay Gupta dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status); 300c71bcdcbSAjay Gupta return status; 301c71bcdcbSAjay Gupta } 302c71bcdcbSAjay Gupta 303c71bcdcbSAjay Gupta gpu_enable_i2c_bus(i2cd); 304c71bcdcbSAjay Gupta 305c71bcdcbSAjay Gupta i2c_set_adapdata(&i2cd->adapter, i2cd); 306c71bcdcbSAjay Gupta i2cd->adapter.owner = THIS_MODULE; 307c71bcdcbSAjay Gupta strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", 308c71bcdcbSAjay Gupta sizeof(i2cd->adapter.name)); 309c71bcdcbSAjay Gupta i2cd->adapter.algo = &gpu_i2c_algorithm; 310c71bcdcbSAjay Gupta i2cd->adapter.quirks = &gpu_i2c_quirks; 311c71bcdcbSAjay Gupta i2cd->adapter.dev.parent = &pdev->dev; 312c71bcdcbSAjay Gupta status = i2c_add_adapter(&i2cd->adapter); 313c71bcdcbSAjay Gupta if (status < 0) 314c71bcdcbSAjay Gupta goto free_irq_vectors; 315c71bcdcbSAjay Gupta 316*2079563dSAndy Shevchenko i2cd->ccgx_client = i2c_new_ccgx_ucsi(&i2cd->adapter, pdev->irq, &ccgx_node); 317*2079563dSAndy Shevchenko if (IS_ERR(i2cd->ccgx_client)) { 318*2079563dSAndy Shevchenko status = dev_err_probe(&pdev->dev, PTR_ERR(i2cd->ccgx_client), 319*2079563dSAndy Shevchenko "register UCSI failed\n"); 320c71bcdcbSAjay Gupta goto del_adapter; 321c71bcdcbSAjay Gupta } 322c71bcdcbSAjay Gupta 323d4a4f927SAjay Gupta pm_runtime_set_autosuspend_delay(&pdev->dev, 3000); 324d4a4f927SAjay Gupta pm_runtime_use_autosuspend(&pdev->dev); 325d4a4f927SAjay Gupta pm_runtime_put_autosuspend(&pdev->dev); 326d4a4f927SAjay Gupta pm_runtime_allow(&pdev->dev); 327d4a4f927SAjay Gupta 328c71bcdcbSAjay Gupta return 0; 329c71bcdcbSAjay Gupta 330c71bcdcbSAjay Gupta del_adapter: 331c71bcdcbSAjay Gupta i2c_del_adapter(&i2cd->adapter); 332c71bcdcbSAjay Gupta free_irq_vectors: 333c71bcdcbSAjay Gupta pci_free_irq_vectors(pdev); 334c71bcdcbSAjay Gupta return status; 335c71bcdcbSAjay Gupta } 336c71bcdcbSAjay Gupta 337c71bcdcbSAjay Gupta static void gpu_i2c_remove(struct pci_dev *pdev) 338c71bcdcbSAjay Gupta { 339c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev); 340c71bcdcbSAjay Gupta 341d4a4f927SAjay Gupta pm_runtime_get_noresume(i2cd->dev); 342c71bcdcbSAjay Gupta i2c_del_adapter(&i2cd->adapter); 343c71bcdcbSAjay Gupta pci_free_irq_vectors(pdev); 344c71bcdcbSAjay Gupta } 345c71bcdcbSAjay Gupta 346b4ff421fSVaibhav Gupta #define gpu_i2c_suspend NULL 347d4a4f927SAjay Gupta 34832774a81SArnd Bergmann static __maybe_unused int gpu_i2c_resume(struct device *dev) 349c71bcdcbSAjay Gupta { 350c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev); 351c71bcdcbSAjay Gupta 352c71bcdcbSAjay Gupta gpu_enable_i2c_bus(i2cd); 3539f2e244dSAjay Gupta /* 3549f2e244dSAjay Gupta * Runtime resume ccgx client so that it can see for any 3559f2e244dSAjay Gupta * connector change event. Old ccg firmware has known 3569f2e244dSAjay Gupta * issue of not triggering interrupt when a device is 3579f2e244dSAjay Gupta * connected to runtime resume the controller. 3589f2e244dSAjay Gupta */ 3599f2e244dSAjay Gupta pm_request_resume(&i2cd->ccgx_client->dev); 360c71bcdcbSAjay Gupta return 0; 361c71bcdcbSAjay Gupta } 362c71bcdcbSAjay Gupta 363d4a4f927SAjay Gupta static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume, 364d4a4f927SAjay Gupta NULL); 365c71bcdcbSAjay Gupta 366c71bcdcbSAjay Gupta static struct pci_driver gpu_i2c_driver = { 367c71bcdcbSAjay Gupta .name = "nvidia-gpu", 368c71bcdcbSAjay Gupta .id_table = gpu_i2c_ids, 369c71bcdcbSAjay Gupta .probe = gpu_i2c_probe, 370c71bcdcbSAjay Gupta .remove = gpu_i2c_remove, 371c71bcdcbSAjay Gupta .driver = { 372c71bcdcbSAjay Gupta .pm = &gpu_i2c_driver_pm, 373c71bcdcbSAjay Gupta }, 374c71bcdcbSAjay Gupta }; 375c71bcdcbSAjay Gupta 376c71bcdcbSAjay Gupta module_pci_driver(gpu_i2c_driver); 377c71bcdcbSAjay Gupta 378c71bcdcbSAjay Gupta MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>"); 379c71bcdcbSAjay Gupta MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver"); 380c71bcdcbSAjay Gupta MODULE_LICENSE("GPL v2"); 381