1c71bcdcbSAjay Gupta // SPDX-License-Identifier: GPL-2.0
2c71bcdcbSAjay Gupta /*
3c71bcdcbSAjay Gupta * Nvidia GPU I2C controller Driver
4c71bcdcbSAjay Gupta *
5c71bcdcbSAjay Gupta * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
6c71bcdcbSAjay Gupta * Author: Ajay Gupta <ajayg@nvidia.com>
7c71bcdcbSAjay Gupta */
8c71bcdcbSAjay Gupta #include <linux/delay.h>
9c71bcdcbSAjay Gupta #include <linux/i2c.h>
10c71bcdcbSAjay Gupta #include <linux/interrupt.h>
11d944b27dSKai-Heng Feng #include <linux/iopoll.h>
12c71bcdcbSAjay Gupta #include <linux/module.h>
13c71bcdcbSAjay Gupta #include <linux/pci.h>
14c71bcdcbSAjay Gupta #include <linux/platform_device.h>
15c71bcdcbSAjay Gupta #include <linux/pm.h>
16c71bcdcbSAjay Gupta #include <linux/pm_runtime.h>
17*a7fbfd44SMario Limonciello #include <linux/power_supply.h>
18c71bcdcbSAjay Gupta
19c71bcdcbSAjay Gupta #include <asm/unaligned.h>
20c71bcdcbSAjay Gupta
212079563dSAndy Shevchenko #include "i2c-ccgx-ucsi.h"
222079563dSAndy Shevchenko
23c71bcdcbSAjay Gupta /* I2C definitions */
24c71bcdcbSAjay Gupta #define I2C_MST_CNTL 0x00
25c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_START BIT(0)
26c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_STOP BIT(1)
27c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CMD_READ (1 << 2)
28c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CMD_WRITE (2 << 2)
29c71bcdcbSAjay Gupta #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
30c71bcdcbSAjay Gupta #define I2C_MST_CNTL_GEN_NACK BIT(28)
31c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS GENMASK(30, 29)
32c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
33c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
34c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
35c71bcdcbSAjay Gupta #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
36c71bcdcbSAjay Gupta #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
37c71bcdcbSAjay Gupta
38c71bcdcbSAjay Gupta #define I2C_MST_ADDR 0x04
39c71bcdcbSAjay Gupta
40c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING 0x08
41c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
42c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
43c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
44c71bcdcbSAjay Gupta #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
45c71bcdcbSAjay Gupta
46c71bcdcbSAjay Gupta #define I2C_MST_DATA 0x0c
47c71bcdcbSAjay Gupta
48c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL 0x20
49c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
50c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
51c71bcdcbSAjay Gupta #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
52c71bcdcbSAjay Gupta
53c71bcdcbSAjay Gupta struct gpu_i2c_dev {
54c71bcdcbSAjay Gupta struct device *dev;
55c71bcdcbSAjay Gupta void __iomem *regs;
56c71bcdcbSAjay Gupta struct i2c_adapter adapter;
57c71bcdcbSAjay Gupta struct i2c_board_info *gpu_ccgx_ucsi;
589f2e244dSAjay Gupta struct i2c_client *ccgx_client;
59c71bcdcbSAjay Gupta };
60c71bcdcbSAjay Gupta
gpu_enable_i2c_bus(struct gpu_i2c_dev * i2cd)61c71bcdcbSAjay Gupta static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
62c71bcdcbSAjay Gupta {
63c71bcdcbSAjay Gupta u32 val;
64c71bcdcbSAjay Gupta
65c71bcdcbSAjay Gupta /* enable I2C */
66c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
67c71bcdcbSAjay Gupta val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
68c71bcdcbSAjay Gupta I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
69c71bcdcbSAjay Gupta I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
70c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
71c71bcdcbSAjay Gupta
72c71bcdcbSAjay Gupta /* enable 100KHZ mode */
73c71bcdcbSAjay Gupta val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
74c71bcdcbSAjay Gupta val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
75c71bcdcbSAjay Gupta << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
76c71bcdcbSAjay Gupta val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
77c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
78c71bcdcbSAjay Gupta }
79c71bcdcbSAjay Gupta
gpu_i2c_check_status(struct gpu_i2c_dev * i2cd)80c71bcdcbSAjay Gupta static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
81c71bcdcbSAjay Gupta {
82c71bcdcbSAjay Gupta u32 val;
83d944b27dSKai-Heng Feng int ret;
84c71bcdcbSAjay Gupta
85d944b27dSKai-Heng Feng ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
86d944b27dSKai-Heng Feng !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
87d944b27dSKai-Heng Feng (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
88d944b27dSKai-Heng Feng 500, 1000 * USEC_PER_MSEC);
89c71bcdcbSAjay Gupta
90d944b27dSKai-Heng Feng if (ret) {
91c71bcdcbSAjay Gupta dev_err(i2cd->dev, "i2c timeout error %x\n", val);
9298be694bSWolfram Sang return -ETIMEDOUT;
93c71bcdcbSAjay Gupta }
94c71bcdcbSAjay Gupta
95c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_CNTL);
96c71bcdcbSAjay Gupta switch (val & I2C_MST_CNTL_STATUS) {
97c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_OKAY:
98c71bcdcbSAjay Gupta return 0;
99c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_NO_ACK:
10098be694bSWolfram Sang return -ENXIO;
101c71bcdcbSAjay Gupta case I2C_MST_CNTL_STATUS_TIMEOUT:
10298be694bSWolfram Sang return -ETIMEDOUT;
103c71bcdcbSAjay Gupta default:
104c71bcdcbSAjay Gupta return 0;
105c71bcdcbSAjay Gupta }
106c71bcdcbSAjay Gupta }
107c71bcdcbSAjay Gupta
gpu_i2c_read(struct gpu_i2c_dev * i2cd,u8 * data,u16 len)108c71bcdcbSAjay Gupta static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
109c71bcdcbSAjay Gupta {
110c71bcdcbSAjay Gupta int status;
111c71bcdcbSAjay Gupta u32 val;
112c71bcdcbSAjay Gupta
113c71bcdcbSAjay Gupta val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
114c71bcdcbSAjay Gupta (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
115c71bcdcbSAjay Gupta I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
116c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_CNTL);
117c71bcdcbSAjay Gupta
118c71bcdcbSAjay Gupta status = gpu_i2c_check_status(i2cd);
119c71bcdcbSAjay Gupta if (status < 0)
120c71bcdcbSAjay Gupta return status;
121c71bcdcbSAjay Gupta
122c71bcdcbSAjay Gupta val = readl(i2cd->regs + I2C_MST_DATA);
123c71bcdcbSAjay Gupta switch (len) {
124c71bcdcbSAjay Gupta case 1:
125c71bcdcbSAjay Gupta data[0] = val;
126c71bcdcbSAjay Gupta break;
127c71bcdcbSAjay Gupta case 2:
128c71bcdcbSAjay Gupta put_unaligned_be16(val, data);
129c71bcdcbSAjay Gupta break;
130c71bcdcbSAjay Gupta case 3:
1319b65b020SAndy Shevchenko put_unaligned_be24(val, data);
132c71bcdcbSAjay Gupta break;
133c71bcdcbSAjay Gupta case 4:
134c71bcdcbSAjay Gupta put_unaligned_be32(val, data);
135c71bcdcbSAjay Gupta break;
136c71bcdcbSAjay Gupta default:
137c71bcdcbSAjay Gupta break;
138c71bcdcbSAjay Gupta }
139c71bcdcbSAjay Gupta return status;
140c71bcdcbSAjay Gupta }
141c71bcdcbSAjay Gupta
gpu_i2c_start(struct gpu_i2c_dev * i2cd)142c71bcdcbSAjay Gupta static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
143c71bcdcbSAjay Gupta {
144c71bcdcbSAjay Gupta writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
145c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd);
146c71bcdcbSAjay Gupta }
147c71bcdcbSAjay Gupta
gpu_i2c_stop(struct gpu_i2c_dev * i2cd)148c71bcdcbSAjay Gupta static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
149c71bcdcbSAjay Gupta {
150c71bcdcbSAjay Gupta writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
151c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd);
152c71bcdcbSAjay Gupta }
153c71bcdcbSAjay Gupta
gpu_i2c_write(struct gpu_i2c_dev * i2cd,u8 data)154c71bcdcbSAjay Gupta static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
155c71bcdcbSAjay Gupta {
156c71bcdcbSAjay Gupta u32 val;
157c71bcdcbSAjay Gupta
158c71bcdcbSAjay Gupta writel(data, i2cd->regs + I2C_MST_DATA);
159c71bcdcbSAjay Gupta
160c71bcdcbSAjay Gupta val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
161c71bcdcbSAjay Gupta writel(val, i2cd->regs + I2C_MST_CNTL);
162c71bcdcbSAjay Gupta
163c71bcdcbSAjay Gupta return gpu_i2c_check_status(i2cd);
164c71bcdcbSAjay Gupta }
165c71bcdcbSAjay Gupta
gpu_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)166c71bcdcbSAjay Gupta static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
167c71bcdcbSAjay Gupta struct i2c_msg *msgs, int num)
168c71bcdcbSAjay Gupta {
169c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
170c71bcdcbSAjay Gupta int status, status2;
171cb7302fbSAjay Gupta bool send_stop = true;
172c71bcdcbSAjay Gupta int i, j;
173c71bcdcbSAjay Gupta
174c71bcdcbSAjay Gupta /*
175c71bcdcbSAjay Gupta * The controller supports maximum 4 byte read due to known
176c71bcdcbSAjay Gupta * limitation of sending STOP after every read.
177c71bcdcbSAjay Gupta */
178d4a4f927SAjay Gupta pm_runtime_get_sync(i2cd->dev);
179c71bcdcbSAjay Gupta for (i = 0; i < num; i++) {
180c71bcdcbSAjay Gupta if (msgs[i].flags & I2C_M_RD) {
181c71bcdcbSAjay Gupta /* program client address before starting read */
182c71bcdcbSAjay Gupta writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
183c71bcdcbSAjay Gupta /* gpu_i2c_read has implicit start */
184c71bcdcbSAjay Gupta status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
185c71bcdcbSAjay Gupta if (status < 0)
186cb7302fbSAjay Gupta goto exit;
187c71bcdcbSAjay Gupta } else {
188c71bcdcbSAjay Gupta u8 addr = i2c_8bit_addr_from_msg(msgs + i);
189c71bcdcbSAjay Gupta
190c71bcdcbSAjay Gupta status = gpu_i2c_start(i2cd);
191c71bcdcbSAjay Gupta if (status < 0) {
192c71bcdcbSAjay Gupta if (i == 0)
193cb7302fbSAjay Gupta send_stop = false;
194cb7302fbSAjay Gupta goto exit;
195c71bcdcbSAjay Gupta }
196c71bcdcbSAjay Gupta
197c71bcdcbSAjay Gupta status = gpu_i2c_write(i2cd, addr);
198c71bcdcbSAjay Gupta if (status < 0)
199cb7302fbSAjay Gupta goto exit;
200c71bcdcbSAjay Gupta
201c71bcdcbSAjay Gupta for (j = 0; j < msgs[i].len; j++) {
202c71bcdcbSAjay Gupta status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
203c71bcdcbSAjay Gupta if (status < 0)
204cb7302fbSAjay Gupta goto exit;
205c71bcdcbSAjay Gupta }
206c71bcdcbSAjay Gupta }
207c71bcdcbSAjay Gupta }
208cb7302fbSAjay Gupta send_stop = false;
209c71bcdcbSAjay Gupta status = gpu_i2c_stop(i2cd);
210c71bcdcbSAjay Gupta if (status < 0)
211cb7302fbSAjay Gupta goto exit;
212c71bcdcbSAjay Gupta
213cb7302fbSAjay Gupta status = i;
214cb7302fbSAjay Gupta exit:
215cb7302fbSAjay Gupta if (send_stop) {
216c71bcdcbSAjay Gupta status2 = gpu_i2c_stop(i2cd);
217c71bcdcbSAjay Gupta if (status2 < 0)
218c71bcdcbSAjay Gupta dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
219cb7302fbSAjay Gupta }
220d4a4f927SAjay Gupta pm_runtime_mark_last_busy(i2cd->dev);
221d4a4f927SAjay Gupta pm_runtime_put_autosuspend(i2cd->dev);
222c71bcdcbSAjay Gupta return status;
223c71bcdcbSAjay Gupta }
224c71bcdcbSAjay Gupta
225c71bcdcbSAjay Gupta static const struct i2c_adapter_quirks gpu_i2c_quirks = {
226c71bcdcbSAjay Gupta .max_read_len = 4,
22739129f28SWolfram Sang .max_comb_2nd_msg_len = 4,
228c71bcdcbSAjay Gupta .flags = I2C_AQ_COMB_WRITE_THEN_READ,
229c71bcdcbSAjay Gupta };
230c71bcdcbSAjay Gupta
gpu_i2c_functionality(struct i2c_adapter * adap)231c71bcdcbSAjay Gupta static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
232c71bcdcbSAjay Gupta {
233c71bcdcbSAjay Gupta return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
234c71bcdcbSAjay Gupta }
235c71bcdcbSAjay Gupta
236c71bcdcbSAjay Gupta static const struct i2c_algorithm gpu_i2c_algorithm = {
237c71bcdcbSAjay Gupta .master_xfer = gpu_i2c_master_xfer,
238c71bcdcbSAjay Gupta .functionality = gpu_i2c_functionality,
239c71bcdcbSAjay Gupta };
240c71bcdcbSAjay Gupta
241c71bcdcbSAjay Gupta /*
242c71bcdcbSAjay Gupta * This driver is for Nvidia GPU cards with USB Type-C interface.
243c71bcdcbSAjay Gupta * We want to identify the cards using vendor ID and class code only
244c71bcdcbSAjay Gupta * to avoid dependency of adding product id for any new card which
245c71bcdcbSAjay Gupta * requires this driver.
246c71bcdcbSAjay Gupta * Currently there is no class code defined for UCSI device over PCI
247c71bcdcbSAjay Gupta * so using UNKNOWN class for now and it will be updated when UCSI
248c71bcdcbSAjay Gupta * over PCI gets a class code.
249c71bcdcbSAjay Gupta * There is no other NVIDIA cards with UNKNOWN class code. Even if the
250c71bcdcbSAjay Gupta * driver gets loaded for an undesired card then eventually i2c_read()
251c71bcdcbSAjay Gupta * (initiated from UCSI i2c_client) will timeout or UCSI commands will
252c71bcdcbSAjay Gupta * timeout.
253c71bcdcbSAjay Gupta */
254c71bcdcbSAjay Gupta #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
255c71bcdcbSAjay Gupta static const struct pci_device_id gpu_i2c_ids[] = {
256c71bcdcbSAjay Gupta { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
257c71bcdcbSAjay Gupta PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
258c71bcdcbSAjay Gupta { }
259c71bcdcbSAjay Gupta };
260c71bcdcbSAjay Gupta MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
261c71bcdcbSAjay Gupta
2625fd958a4SAjay Gupta static const struct property_entry ccgx_props[] = {
263430b3876SWayne Chang /* Use FW built for NVIDIA GPU only */
264f510b0a3SWayne Chang PROPERTY_ENTRY_STRING("firmware-name", "nvidia,gpu"),
265*a7fbfd44SMario Limonciello /* USB-C doesn't power the system */
266*a7fbfd44SMario Limonciello PROPERTY_ENTRY_U8("scope", POWER_SUPPLY_SCOPE_DEVICE),
2675fd958a4SAjay Gupta { }
2685fd958a4SAjay Gupta };
2695fd958a4SAjay Gupta
270239798f5SHeikki Krogerus static const struct software_node ccgx_node = {
271239798f5SHeikki Krogerus .properties = ccgx_props,
272239798f5SHeikki Krogerus };
273239798f5SHeikki Krogerus
gpu_i2c_probe(struct pci_dev * pdev,const struct pci_device_id * id)274c71bcdcbSAjay Gupta static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
275c71bcdcbSAjay Gupta {
276c2c25be6SAndy Shevchenko struct device *dev = &pdev->dev;
277c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd;
278c71bcdcbSAjay Gupta int status;
279c71bcdcbSAjay Gupta
280c2c25be6SAndy Shevchenko i2cd = devm_kzalloc(dev, sizeof(*i2cd), GFP_KERNEL);
281c71bcdcbSAjay Gupta if (!i2cd)
282c71bcdcbSAjay Gupta return -ENOMEM;
283c71bcdcbSAjay Gupta
284c2c25be6SAndy Shevchenko i2cd->dev = dev;
285c2c25be6SAndy Shevchenko dev_set_drvdata(dev, i2cd);
286c71bcdcbSAjay Gupta
287c71bcdcbSAjay Gupta status = pcim_enable_device(pdev);
288c74a30ceSAndy Shevchenko if (status < 0)
289c74a30ceSAndy Shevchenko return dev_err_probe(dev, status, "pcim_enable_device failed\n");
290c71bcdcbSAjay Gupta
291c71bcdcbSAjay Gupta pci_set_master(pdev);
292c71bcdcbSAjay Gupta
293c71bcdcbSAjay Gupta i2cd->regs = pcim_iomap(pdev, 0, 0);
294c74a30ceSAndy Shevchenko if (!i2cd->regs)
295c74a30ceSAndy Shevchenko return dev_err_probe(dev, -ENOMEM, "pcim_iomap failed\n");
296c71bcdcbSAjay Gupta
297c71bcdcbSAjay Gupta status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
298c74a30ceSAndy Shevchenko if (status < 0)
299c74a30ceSAndy Shevchenko return dev_err_probe(dev, status, "pci_alloc_irq_vectors err\n");
300c71bcdcbSAjay Gupta
301c71bcdcbSAjay Gupta gpu_enable_i2c_bus(i2cd);
302c71bcdcbSAjay Gupta
303c71bcdcbSAjay Gupta i2c_set_adapdata(&i2cd->adapter, i2cd);
304c71bcdcbSAjay Gupta i2cd->adapter.owner = THIS_MODULE;
305ea1558ceSWolfram Sang strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
306c71bcdcbSAjay Gupta sizeof(i2cd->adapter.name));
307c71bcdcbSAjay Gupta i2cd->adapter.algo = &gpu_i2c_algorithm;
308c71bcdcbSAjay Gupta i2cd->adapter.quirks = &gpu_i2c_quirks;
309c2c25be6SAndy Shevchenko i2cd->adapter.dev.parent = dev;
310c71bcdcbSAjay Gupta status = i2c_add_adapter(&i2cd->adapter);
311c71bcdcbSAjay Gupta if (status < 0)
312c71bcdcbSAjay Gupta goto free_irq_vectors;
313c71bcdcbSAjay Gupta
3142079563dSAndy Shevchenko i2cd->ccgx_client = i2c_new_ccgx_ucsi(&i2cd->adapter, pdev->irq, &ccgx_node);
3152079563dSAndy Shevchenko if (IS_ERR(i2cd->ccgx_client)) {
316c2c25be6SAndy Shevchenko status = dev_err_probe(dev, PTR_ERR(i2cd->ccgx_client), "register UCSI failed\n");
317c71bcdcbSAjay Gupta goto del_adapter;
318c71bcdcbSAjay Gupta }
319c71bcdcbSAjay Gupta
320c2c25be6SAndy Shevchenko pm_runtime_set_autosuspend_delay(dev, 3000);
321c2c25be6SAndy Shevchenko pm_runtime_use_autosuspend(dev);
322c2c25be6SAndy Shevchenko pm_runtime_put_autosuspend(dev);
323c2c25be6SAndy Shevchenko pm_runtime_allow(dev);
324d4a4f927SAjay Gupta
325c71bcdcbSAjay Gupta return 0;
326c71bcdcbSAjay Gupta
327c71bcdcbSAjay Gupta del_adapter:
328c71bcdcbSAjay Gupta i2c_del_adapter(&i2cd->adapter);
329c71bcdcbSAjay Gupta free_irq_vectors:
330c71bcdcbSAjay Gupta pci_free_irq_vectors(pdev);
331c71bcdcbSAjay Gupta return status;
332c71bcdcbSAjay Gupta }
333c71bcdcbSAjay Gupta
gpu_i2c_remove(struct pci_dev * pdev)334c71bcdcbSAjay Gupta static void gpu_i2c_remove(struct pci_dev *pdev)
335c71bcdcbSAjay Gupta {
336c2c25be6SAndy Shevchenko struct gpu_i2c_dev *i2cd = pci_get_drvdata(pdev);
337c71bcdcbSAjay Gupta
338d4a4f927SAjay Gupta pm_runtime_get_noresume(i2cd->dev);
339c71bcdcbSAjay Gupta i2c_del_adapter(&i2cd->adapter);
340c71bcdcbSAjay Gupta pci_free_irq_vectors(pdev);
341c71bcdcbSAjay Gupta }
342c71bcdcbSAjay Gupta
343b4ff421fSVaibhav Gupta #define gpu_i2c_suspend NULL
344d4a4f927SAjay Gupta
gpu_i2c_resume(struct device * dev)34532774a81SArnd Bergmann static __maybe_unused int gpu_i2c_resume(struct device *dev)
346c71bcdcbSAjay Gupta {
347c71bcdcbSAjay Gupta struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
348c71bcdcbSAjay Gupta
349c71bcdcbSAjay Gupta gpu_enable_i2c_bus(i2cd);
3509f2e244dSAjay Gupta /*
3519f2e244dSAjay Gupta * Runtime resume ccgx client so that it can see for any
3529f2e244dSAjay Gupta * connector change event. Old ccg firmware has known
3539f2e244dSAjay Gupta * issue of not triggering interrupt when a device is
3549f2e244dSAjay Gupta * connected to runtime resume the controller.
3559f2e244dSAjay Gupta */
3569f2e244dSAjay Gupta pm_request_resume(&i2cd->ccgx_client->dev);
357c71bcdcbSAjay Gupta return 0;
358c71bcdcbSAjay Gupta }
359c71bcdcbSAjay Gupta
360d4a4f927SAjay Gupta static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
361d4a4f927SAjay Gupta NULL);
362c71bcdcbSAjay Gupta
363c71bcdcbSAjay Gupta static struct pci_driver gpu_i2c_driver = {
364c71bcdcbSAjay Gupta .name = "nvidia-gpu",
365c71bcdcbSAjay Gupta .id_table = gpu_i2c_ids,
366c71bcdcbSAjay Gupta .probe = gpu_i2c_probe,
367c71bcdcbSAjay Gupta .remove = gpu_i2c_remove,
368c71bcdcbSAjay Gupta .driver = {
369c71bcdcbSAjay Gupta .pm = &gpu_i2c_driver_pm,
370c71bcdcbSAjay Gupta },
371c71bcdcbSAjay Gupta };
372c71bcdcbSAjay Gupta
373c71bcdcbSAjay Gupta module_pci_driver(gpu_i2c_driver);
374c71bcdcbSAjay Gupta
375c71bcdcbSAjay Gupta MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
376c71bcdcbSAjay Gupta MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
377c71bcdcbSAjay Gupta MODULE_LICENSE("GPL v2");
378