1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/delay.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/i2c.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 26 #include <plat/i2c.h> 27 28 #define DRIVER_NAME "nmk-i2c" 29 30 /* I2C Controller register offsets */ 31 #define I2C_CR (0x000) 32 #define I2C_SCR (0x004) 33 #define I2C_HSMCR (0x008) 34 #define I2C_MCR (0x00C) 35 #define I2C_TFR (0x010) 36 #define I2C_SR (0x014) 37 #define I2C_RFR (0x018) 38 #define I2C_TFTR (0x01C) 39 #define I2C_RFTR (0x020) 40 #define I2C_DMAR (0x024) 41 #define I2C_BRCR (0x028) 42 #define I2C_IMSCR (0x02C) 43 #define I2C_RISR (0x030) 44 #define I2C_MISR (0x034) 45 #define I2C_ICR (0x038) 46 47 /* Control registers */ 48 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 49 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 50 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 51 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 52 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 53 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 54 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 55 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 56 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 57 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 58 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 59 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 60 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 61 62 /* Master controller (MCR) register */ 63 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 64 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 65 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 66 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 67 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 68 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 69 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 70 71 /* Status register (SR) */ 72 #define I2C_SR_OP (0x3 << 0) /* Operation */ 73 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 74 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 75 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 76 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 77 78 /* Interrupt mask set/clear (IMSCR) bits */ 79 #define I2C_IT_TXFE (0x1 << 0) 80 #define I2C_IT_TXFNE (0x1 << 1) 81 #define I2C_IT_TXFF (0x1 << 2) 82 #define I2C_IT_TXFOVR (0x1 << 3) 83 #define I2C_IT_RXFE (0x1 << 4) 84 #define I2C_IT_RXFNF (0x1 << 5) 85 #define I2C_IT_RXFF (0x1 << 6) 86 #define I2C_IT_RFSR (0x1 << 16) 87 #define I2C_IT_RFSE (0x1 << 17) 88 #define I2C_IT_WTSR (0x1 << 18) 89 #define I2C_IT_MTD (0x1 << 19) 90 #define I2C_IT_STD (0x1 << 20) 91 #define I2C_IT_MAL (0x1 << 24) 92 #define I2C_IT_BERR (0x1 << 25) 93 #define I2C_IT_MTDWS (0x1 << 28) 94 95 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 96 97 /* some bits in ICR are reserved */ 98 #define I2C_CLEAR_ALL_INTS 0x131f007f 99 100 /* first three msb bits are reserved */ 101 #define IRQ_MASK(mask) (mask & 0x1fffffff) 102 103 /* maximum threshold value */ 104 #define MAX_I2C_FIFO_THRESHOLD 15 105 106 /* per-transfer delay, required for the hardware to stabilize */ 107 #define I2C_DELAY 150 108 109 enum i2c_status { 110 I2C_NOP, 111 I2C_ON_GOING, 112 I2C_OK, 113 I2C_ABORT 114 }; 115 116 /* operation */ 117 enum i2c_operation { 118 I2C_NO_OPERATION = 0xff, 119 I2C_WRITE = 0x00, 120 I2C_READ = 0x01 121 }; 122 123 /* controller response timeout in ms */ 124 #define I2C_TIMEOUT_MS 2000 125 126 /** 127 * struct i2c_nmk_client - client specific data 128 * @slave_adr: 7-bit slave address 129 * @count: no. bytes to be transfered 130 * @buffer: client data buffer 131 * @xfer_bytes: bytes transfered till now 132 * @operation: current I2C operation 133 */ 134 struct i2c_nmk_client { 135 unsigned short slave_adr; 136 unsigned long count; 137 unsigned char *buffer; 138 unsigned long xfer_bytes; 139 enum i2c_operation operation; 140 }; 141 142 /** 143 * struct nmk_i2c_dev - private data structure of the controller 144 * @pdev: parent platform device 145 * @adap: corresponding I2C adapter 146 * @irq: interrupt line for the controller 147 * @virtbase: virtual io memory area 148 * @clk: hardware i2c block clock 149 * @cfg: machine provided controller configuration 150 * @cli: holder of client specific data 151 * @stop: stop condition 152 * @xfer_complete: acknowledge completion for a I2C message 153 * @result: controller propogated result 154 */ 155 struct nmk_i2c_dev { 156 struct platform_device *pdev; 157 struct i2c_adapter adap; 158 int irq; 159 void __iomem *virtbase; 160 struct clk *clk; 161 struct nmk_i2c_controller cfg; 162 struct i2c_nmk_client cli; 163 int stop; 164 struct completion xfer_complete; 165 int result; 166 }; 167 168 /* controller's abort causes */ 169 static const char *abort_causes[] = { 170 "no ack received after address transmission", 171 "no ack received during data phase", 172 "ack received after xmission of master code", 173 "master lost arbitration", 174 "slave restarts", 175 "slave reset", 176 "overflow, maxsize is 2047 bytes", 177 }; 178 179 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 180 { 181 writel(readl(reg) | mask, reg); 182 } 183 184 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 185 { 186 writel(readl(reg) & ~mask, reg); 187 } 188 189 /** 190 * flush_i2c_fifo() - This function flushes the I2C FIFO 191 * @dev: private data of I2C Driver 192 * 193 * This function flushes the I2C Tx and Rx FIFOs. It returns 194 * 0 on successful flushing of FIFO 195 */ 196 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 197 { 198 #define LOOP_ATTEMPTS 10 199 int i; 200 unsigned long timeout; 201 202 /* 203 * flush the transmit and receive FIFO. The flushing 204 * operation takes several cycles before to be completed. 205 * On the completion, the I2C internal logic clears these 206 * bits, until then no one must access Tx, Rx FIFO and 207 * should poll on these bits waiting for the completion. 208 */ 209 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 210 211 for (i = 0; i < LOOP_ATTEMPTS; i++) { 212 timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS); 213 214 while (!time_after(jiffies, timeout)) { 215 if ((readl(dev->virtbase + I2C_CR) & 216 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 217 return 0; 218 } 219 } 220 221 dev_err(&dev->pdev->dev, "flushing operation timed out " 222 "giving up after %d attempts", LOOP_ATTEMPTS); 223 224 return -ETIMEDOUT; 225 } 226 227 /** 228 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 229 * @dev: private data of I2C Driver 230 */ 231 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 232 { 233 u32 mask = IRQ_MASK(0); 234 writel(mask, dev->virtbase + I2C_IMSCR); 235 } 236 237 /** 238 * clear_all_interrupts() - Clear all interrupts of I2C Controller 239 * @dev: private data of I2C Driver 240 */ 241 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 242 { 243 u32 mask; 244 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 245 writel(mask, dev->virtbase + I2C_ICR); 246 } 247 248 /** 249 * init_hw() - initialize the I2C hardware 250 * @dev: private data of I2C Driver 251 */ 252 static int init_hw(struct nmk_i2c_dev *dev) 253 { 254 int stat; 255 256 clk_enable(dev->clk); 257 258 stat = flush_i2c_fifo(dev); 259 if (stat) 260 return stat; 261 262 /* disable the controller */ 263 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 264 265 disable_all_interrupts(dev); 266 267 clear_all_interrupts(dev); 268 269 dev->cli.operation = I2C_NO_OPERATION; 270 271 clk_disable(dev->clk); 272 273 udelay(I2C_DELAY); 274 return 0; 275 } 276 277 /* enable peripheral, master mode operation */ 278 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 279 280 /** 281 * load_i2c_mcr_reg() - load the MCR register 282 * @dev: private data of controller 283 */ 284 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev) 285 { 286 u32 mcr = 0; 287 288 /* 7-bit address transaction */ 289 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 290 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 291 292 /* start byte procedure not applied */ 293 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 294 295 /* check the operation, master read/write? */ 296 if (dev->cli.operation == I2C_WRITE) 297 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 298 else 299 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 300 301 /* stop or repeated start? */ 302 if (dev->stop) 303 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 304 else 305 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 306 307 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 308 309 return mcr; 310 } 311 312 /** 313 * setup_i2c_controller() - setup the controller 314 * @dev: private data of controller 315 */ 316 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 317 { 318 u32 brcr1, brcr2; 319 u32 i2c_clk, div; 320 321 writel(0x0, dev->virtbase + I2C_CR); 322 writel(0x0, dev->virtbase + I2C_HSMCR); 323 writel(0x0, dev->virtbase + I2C_TFTR); 324 writel(0x0, dev->virtbase + I2C_RFTR); 325 writel(0x0, dev->virtbase + I2C_DMAR); 326 327 /* 328 * set the slsu: 329 * 330 * slsu defines the data setup time after SCL clock 331 * stretching in terms of i2c clk cycles. The 332 * needed setup time for the three modes are 250ns, 333 * 100ns, 10ns repectively thus leading to the values 334 * of 14, 6, 2 for a 48 MHz i2c clk. 335 */ 336 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); 337 338 i2c_clk = clk_get_rate(dev->clk); 339 340 /* fallback to std. mode if machine has not provided it */ 341 if (dev->cfg.clk_freq == 0) 342 dev->cfg.clk_freq = 100000; 343 344 /* 345 * The spec says, in case of std. mode the divider is 346 * 2 whereas it is 3 for fast and fastplus mode of 347 * operation. TODO - high speed support. 348 */ 349 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 350 351 /* 352 * generate the mask for baud rate counters. The controller 353 * has two baud rate counters. One is used for High speed 354 * operation, and the other is for std, fast mode, fast mode 355 * plus operation. Currently we do not supprt high speed mode 356 * so set brcr1 to 0. 357 */ 358 brcr1 = 0 << 16; 359 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 360 361 /* set the baud rate counter register */ 362 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 363 364 /* 365 * set the speed mode. Currently we support 366 * only standard and fast mode of operation 367 * TODO - support for fast mode plus (upto 1Mb/s) 368 * and high speed (up to 3.4 Mb/s) 369 */ 370 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 371 dev_err(&dev->pdev->dev, "do not support this mode " 372 "defaulting to std. mode\n"); 373 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 374 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 375 writel(I2C_FREQ_MODE_STANDARD << 4, 376 dev->virtbase + I2C_CR); 377 } 378 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 379 380 /* set the Tx and Rx FIFO threshold */ 381 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 382 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 383 } 384 385 /** 386 * read_i2c() - Read from I2C client device 387 * @dev: private data of I2C Driver 388 * 389 * This function reads from i2c client device when controller is in 390 * master mode. There is a completion timeout. If there is no transfer 391 * before timeout error is returned. 392 */ 393 static int read_i2c(struct nmk_i2c_dev *dev) 394 { 395 u32 status = 0; 396 u32 mcr; 397 u32 irq_mask = 0; 398 int timeout; 399 400 mcr = load_i2c_mcr_reg(dev); 401 writel(mcr, dev->virtbase + I2C_MCR); 402 403 /* load the current CR value */ 404 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 405 dev->virtbase + I2C_CR); 406 407 /* enable the controller */ 408 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 409 410 init_completion(&dev->xfer_complete); 411 412 /* enable interrupts by setting the mask */ 413 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 414 I2C_IT_MAL | I2C_IT_BERR); 415 416 if (dev->stop) 417 irq_mask |= I2C_IT_MTD; 418 else 419 irq_mask |= I2C_IT_MTDWS; 420 421 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 422 423 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 424 dev->virtbase + I2C_IMSCR); 425 426 timeout = wait_for_completion_interruptible_timeout( 427 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); 428 429 if (timeout < 0) { 430 dev_err(&dev->pdev->dev, 431 "wait_for_completion_interruptible_timeout" 432 "returned %d waiting for event\n", timeout); 433 status = timeout; 434 } 435 436 if (timeout == 0) { 437 /* controler has timedout, re-init the h/w */ 438 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); 439 (void) init_hw(dev); 440 status = -ETIMEDOUT; 441 } 442 return status; 443 } 444 445 /** 446 * write_i2c() - Write data to I2C client. 447 * @dev: private data of I2C Driver 448 * 449 * This function writes data to I2C client 450 */ 451 static int write_i2c(struct nmk_i2c_dev *dev) 452 { 453 u32 status = 0; 454 u32 mcr; 455 u32 irq_mask = 0; 456 int timeout; 457 458 mcr = load_i2c_mcr_reg(dev); 459 460 writel(mcr, dev->virtbase + I2C_MCR); 461 462 /* load the current CR value */ 463 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 464 dev->virtbase + I2C_CR); 465 466 /* enable the controller */ 467 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 468 469 init_completion(&dev->xfer_complete); 470 471 /* enable interrupts by settings the masks */ 472 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR | 473 I2C_IT_MAL | I2C_IT_BERR); 474 475 /* 476 * check if we want to transfer a single or multiple bytes, if so 477 * set the MTDWS bit (Master Transaction Done Without Stop) 478 * to start repeated start operation 479 */ 480 if (dev->stop) 481 irq_mask |= I2C_IT_MTD; 482 else 483 irq_mask |= I2C_IT_MTDWS; 484 485 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 486 487 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 488 dev->virtbase + I2C_IMSCR); 489 490 timeout = wait_for_completion_interruptible_timeout( 491 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); 492 493 if (timeout < 0) { 494 dev_err(&dev->pdev->dev, 495 "wait_for_completion_interruptible_timeout" 496 "returned %d waiting for event\n", timeout); 497 status = timeout; 498 } 499 500 if (timeout == 0) { 501 /* controler has timedout, re-init the h/w */ 502 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); 503 (void) init_hw(dev); 504 status = -ETIMEDOUT; 505 } 506 507 return status; 508 } 509 510 /** 511 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 512 * @i2c_adap: Adapter pointer to the controller 513 * @msgs: Pointer to data to be written. 514 * @num_msgs: Number of messages to be executed 515 * 516 * This is the function called by the generic kernel i2c_transfer() 517 * or i2c_smbus...() API calls. Note that this code is protected by the 518 * semaphore set in the kernel i2c_transfer() function. 519 * 520 * NOTE: 521 * READ TRANSFER : We impose a restriction of the first message to be the 522 * index message for any read transaction. 523 * - a no index is coded as '0', 524 * - 2byte big endian index is coded as '3' 525 * !!! msg[0].buf holds the actual index. 526 * This is compatible with generic messages of smbus emulator 527 * that send a one byte index. 528 * eg. a I2C transation to read 2 bytes from index 0 529 * idx = 0; 530 * msg[0].addr = client->addr; 531 * msg[0].flags = 0x0; 532 * msg[0].len = 1; 533 * msg[0].buf = &idx; 534 * 535 * msg[1].addr = client->addr; 536 * msg[1].flags = I2C_M_RD; 537 * msg[1].len = 2; 538 * msg[1].buf = rd_buff 539 * i2c_transfer(adap, msg, 2); 540 * 541 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 542 * If you want to emulate an SMBUS write transaction put the 543 * index as first byte(or first and second) in the payload. 544 * eg. a I2C transation to write 2 bytes from index 1 545 * wr_buff[0] = 0x1; 546 * wr_buff[1] = 0x23; 547 * wr_buff[2] = 0x46; 548 * msg[0].flags = 0x0; 549 * msg[0].len = 3; 550 * msg[0].buf = wr_buff; 551 * i2c_transfer(adap, msg, 1); 552 * 553 * To read or write a block of data (multiple bytes) using SMBUS emulation 554 * please use the i2c_smbus_read_i2c_block_data() 555 * or i2c_smbus_write_i2c_block_data() API 556 */ 557 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 558 struct i2c_msg msgs[], int num_msgs) 559 { 560 int status; 561 int i; 562 u32 cause; 563 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 564 565 status = init_hw(dev); 566 if (status) 567 return status; 568 569 clk_enable(dev->clk); 570 571 /* setup the i2c controller */ 572 setup_i2c_controller(dev); 573 574 for (i = 0; i < num_msgs; i++) { 575 if (unlikely(msgs[i].flags & I2C_M_TEN)) { 576 dev_err(&dev->pdev->dev, "10 bit addressing" 577 "not supported\n"); 578 return -EINVAL; 579 } 580 dev->cli.slave_adr = msgs[i].addr; 581 dev->cli.buffer = msgs[i].buf; 582 dev->cli.count = msgs[i].len; 583 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 584 dev->result = 0; 585 586 if (msgs[i].flags & I2C_M_RD) { 587 /* it is a read operation */ 588 dev->cli.operation = I2C_READ; 589 status = read_i2c(dev); 590 } else { 591 /* write operation */ 592 dev->cli.operation = I2C_WRITE; 593 status = write_i2c(dev); 594 } 595 if (status || (dev->result)) { 596 /* get the abort cause */ 597 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7; 598 dev_err(&dev->pdev->dev, "error during I2C" 599 "message xfer: %d\n", cause); 600 dev_err(&dev->pdev->dev, "%s\n", 601 cause >= ARRAY_SIZE(abort_causes) 602 ? "unknown reason" : abort_causes[cause]); 603 clk_disable(dev->clk); 604 return status; 605 } 606 udelay(I2C_DELAY); 607 } 608 clk_disable(dev->clk); 609 610 /* return the no. messages processed */ 611 if (status) 612 return status; 613 else 614 return num_msgs; 615 } 616 617 /** 618 * disable_interrupts() - disable the interrupts 619 * @dev: private data of controller 620 * @irq: interrupt number 621 */ 622 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 623 { 624 irq = IRQ_MASK(irq); 625 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 626 dev->virtbase + I2C_IMSCR); 627 return 0; 628 } 629 630 /** 631 * i2c_irq_handler() - interrupt routine 632 * @irq: interrupt number 633 * @arg: data passed to the handler 634 * 635 * This is the interrupt handler for the i2c driver. Currently 636 * it handles the major interrupts like Rx & Tx FIFO management 637 * interrupts, master transaction interrupts, arbitration and 638 * bus error interrupts. The rest of the interrupts are treated as 639 * unhandled. 640 */ 641 static irqreturn_t i2c_irq_handler(int irq, void *arg) 642 { 643 struct nmk_i2c_dev *dev = arg; 644 u32 tft, rft; 645 u32 count; 646 u32 misr; 647 u32 src = 0; 648 649 /* load Tx FIFO and Rx FIFO threshold values */ 650 tft = readl(dev->virtbase + I2C_TFTR); 651 rft = readl(dev->virtbase + I2C_RFTR); 652 653 /* read interrupt status register */ 654 misr = readl(dev->virtbase + I2C_MISR); 655 656 src = __ffs(misr); 657 switch ((1 << src)) { 658 659 /* Transmit FIFO nearly empty interrupt */ 660 case I2C_IT_TXFNE: 661 { 662 if (dev->cli.operation == I2C_READ) { 663 /* 664 * in read operation why do we care for writing? 665 * so disable the Transmit FIFO interrupt 666 */ 667 disable_interrupts(dev, I2C_IT_TXFNE); 668 } else { 669 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2); 670 (count > 0) && 671 (dev->cli.count != 0); 672 count--) { 673 /* write to the Tx FIFO */ 674 writeb(*dev->cli.buffer, 675 dev->virtbase + I2C_TFR); 676 dev->cli.buffer++; 677 dev->cli.count--; 678 dev->cli.xfer_bytes++; 679 } 680 /* 681 * if done, close the transfer by disabling the 682 * corresponding TXFNE interrupt 683 */ 684 if (dev->cli.count == 0) 685 disable_interrupts(dev, I2C_IT_TXFNE); 686 } 687 } 688 break; 689 690 /* 691 * Rx FIFO nearly full interrupt. 692 * This is set when the numer of entries in Rx FIFO is 693 * greater or equal than the threshold value programmed 694 * in RFT 695 */ 696 case I2C_IT_RXFNF: 697 for (count = rft; count > 0; count--) { 698 /* Read the Rx FIFO */ 699 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 700 dev->cli.buffer++; 701 } 702 dev->cli.count -= rft; 703 dev->cli.xfer_bytes += rft; 704 break; 705 706 /* Rx FIFO full */ 707 case I2C_IT_RXFF: 708 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 709 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 710 dev->cli.buffer++; 711 } 712 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 713 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 714 break; 715 716 /* Master Transaction Done with/without stop */ 717 case I2C_IT_MTD: 718 case I2C_IT_MTDWS: 719 if (dev->cli.operation == I2C_READ) { 720 while (!(readl(dev->virtbase + I2C_RISR) 721 & I2C_IT_RXFE)) { 722 if (dev->cli.count == 0) 723 break; 724 *dev->cli.buffer = 725 readb(dev->virtbase + I2C_RFR); 726 dev->cli.buffer++; 727 dev->cli.count--; 728 dev->cli.xfer_bytes++; 729 } 730 } 731 732 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD); 733 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS); 734 735 disable_interrupts(dev, 736 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF 737 | I2C_IT_TXFOVR | I2C_IT_RXFNF 738 | I2C_IT_RXFF | I2C_IT_RXFE)); 739 740 if (dev->cli.count) { 741 dev->result = -1; 742 dev_err(&dev->pdev->dev, "%lu bytes still remain to be" 743 "xfered\n", dev->cli.count); 744 (void) init_hw(dev); 745 } 746 complete(&dev->xfer_complete); 747 748 break; 749 750 /* Master Arbitration lost interrupt */ 751 case I2C_IT_MAL: 752 dev->result = -1; 753 (void) init_hw(dev); 754 755 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 756 complete(&dev->xfer_complete); 757 758 break; 759 760 /* 761 * Bus Error interrupt. 762 * This happens when an unexpected start/stop condition occurs 763 * during the transaction. 764 */ 765 case I2C_IT_BERR: 766 dev->result = -1; 767 /* get the status */ 768 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 769 (void) init_hw(dev); 770 771 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 772 complete(&dev->xfer_complete); 773 774 break; 775 776 /* 777 * Tx FIFO overrun interrupt. 778 * This is set when a write operation in Tx FIFO is performed and 779 * the Tx FIFO is full. 780 */ 781 case I2C_IT_TXFOVR: 782 dev->result = -1; 783 (void) init_hw(dev); 784 785 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n"); 786 complete(&dev->xfer_complete); 787 788 break; 789 790 /* unhandled interrupts by this driver - TODO*/ 791 case I2C_IT_TXFE: 792 case I2C_IT_TXFF: 793 case I2C_IT_RXFE: 794 case I2C_IT_RFSR: 795 case I2C_IT_RFSE: 796 case I2C_IT_WTSR: 797 case I2C_IT_STD: 798 dev_err(&dev->pdev->dev, "unhandled Interrupt\n"); 799 break; 800 default: 801 dev_err(&dev->pdev->dev, "spurious Interrupt..\n"); 802 break; 803 } 804 805 return IRQ_HANDLED; 806 } 807 808 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 809 { 810 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 811 } 812 813 static const struct i2c_algorithm nmk_i2c_algo = { 814 .master_xfer = nmk_i2c_xfer, 815 .functionality = nmk_i2c_functionality 816 }; 817 818 static int __devinit nmk_i2c_probe(struct platform_device *pdev) 819 { 820 int ret = 0; 821 struct resource *res; 822 struct nmk_i2c_controller *pdata = 823 pdev->dev.platform_data; 824 struct nmk_i2c_dev *dev; 825 struct i2c_adapter *adap; 826 827 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 828 if (!dev) { 829 dev_err(&pdev->dev, "cannot allocate memory\n"); 830 ret = -ENOMEM; 831 goto err_no_mem; 832 } 833 834 dev->pdev = pdev; 835 platform_set_drvdata(pdev, dev); 836 837 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 838 if (!res) { 839 ret = -ENOENT; 840 goto err_no_resource; 841 } 842 843 if (request_mem_region(res->start, resource_size(res), 844 DRIVER_NAME "I/O region") == NULL) { 845 ret = -EBUSY; 846 goto err_no_region; 847 } 848 849 dev->virtbase = ioremap(res->start, resource_size(res)); 850 if (!dev->virtbase) { 851 ret = -ENOMEM; 852 goto err_no_ioremap; 853 } 854 855 dev->irq = platform_get_irq(pdev, 0); 856 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED, 857 DRIVER_NAME, dev); 858 if (ret) { 859 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq); 860 goto err_irq; 861 } 862 863 dev->clk = clk_get(&pdev->dev, NULL); 864 if (IS_ERR(dev->clk)) { 865 dev_err(&pdev->dev, "could not get i2c clock\n"); 866 ret = PTR_ERR(dev->clk); 867 goto err_no_clk; 868 } 869 870 adap = &dev->adap; 871 adap->dev.parent = &pdev->dev; 872 adap->owner = THIS_MODULE; 873 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 874 adap->algo = &nmk_i2c_algo; 875 876 /* fetch the controller id */ 877 adap->nr = pdev->id; 878 879 /* fetch the controller configuration from machine */ 880 dev->cfg.clk_freq = pdata->clk_freq; 881 dev->cfg.slsu = pdata->slsu; 882 dev->cfg.tft = pdata->tft; 883 dev->cfg.rft = pdata->rft; 884 dev->cfg.sm = pdata->sm; 885 886 i2c_set_adapdata(adap, dev); 887 888 ret = init_hw(dev); 889 if (ret != 0) { 890 dev_err(&pdev->dev, "error in initializing i2c hardware\n"); 891 goto err_init_hw; 892 } 893 894 dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual " 895 "base %p\n", pdev->id, dev->virtbase); 896 897 ret = i2c_add_numbered_adapter(adap); 898 if (ret) { 899 dev_err(&pdev->dev, "failed to add adapter\n"); 900 goto err_add_adap; 901 } 902 903 return 0; 904 905 err_init_hw: 906 err_add_adap: 907 clk_put(dev->clk); 908 err_no_clk: 909 free_irq(dev->irq, dev); 910 err_irq: 911 iounmap(dev->virtbase); 912 err_no_ioremap: 913 release_mem_region(res->start, resource_size(res)); 914 err_no_region: 915 platform_set_drvdata(pdev, NULL); 916 err_no_resource: 917 kfree(dev); 918 err_no_mem: 919 920 return ret; 921 } 922 923 static int __devexit nmk_i2c_remove(struct platform_device *pdev) 924 { 925 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 926 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev); 927 928 i2c_del_adapter(&dev->adap); 929 flush_i2c_fifo(dev); 930 disable_all_interrupts(dev); 931 clear_all_interrupts(dev); 932 /* disable the controller */ 933 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 934 free_irq(dev->irq, dev); 935 iounmap(dev->virtbase); 936 if (res) 937 release_mem_region(res->start, resource_size(res)); 938 clk_put(dev->clk); 939 platform_set_drvdata(pdev, NULL); 940 kfree(dev); 941 942 return 0; 943 } 944 945 static struct platform_driver nmk_i2c_driver = { 946 .driver = { 947 .owner = THIS_MODULE, 948 .name = DRIVER_NAME, 949 }, 950 .probe = nmk_i2c_probe, 951 .remove = __devexit_p(nmk_i2c_remove), 952 }; 953 954 static int __init nmk_i2c_init(void) 955 { 956 return platform_driver_register(&nmk_i2c_driver); 957 } 958 959 static void __exit nmk_i2c_exit(void) 960 { 961 platform_driver_unregister(&nmk_i2c_driver); 962 } 963 964 subsys_initcall(nmk_i2c_init); 965 module_exit(nmk_i2c_exit); 966 967 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 968 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 969 MODULE_LICENSE("GPL"); 970 MODULE_ALIAS("platform:" DRIVER_NAME); 971