1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/amba/bus.h> 18 #include <linux/slab.h> 19 #include <linux/interrupt.h> 20 #include <linux/i2c.h> 21 #include <linux/err.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 #include <linux/pinctrl/consumer.h> 27 28 #define DRIVER_NAME "nmk-i2c" 29 30 /* I2C Controller register offsets */ 31 #define I2C_CR (0x000) 32 #define I2C_SCR (0x004) 33 #define I2C_HSMCR (0x008) 34 #define I2C_MCR (0x00C) 35 #define I2C_TFR (0x010) 36 #define I2C_SR (0x014) 37 #define I2C_RFR (0x018) 38 #define I2C_TFTR (0x01C) 39 #define I2C_RFTR (0x020) 40 #define I2C_DMAR (0x024) 41 #define I2C_BRCR (0x028) 42 #define I2C_IMSCR (0x02C) 43 #define I2C_RISR (0x030) 44 #define I2C_MISR (0x034) 45 #define I2C_ICR (0x038) 46 47 /* Control registers */ 48 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 49 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 50 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 51 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 52 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 53 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 54 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 55 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 56 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 57 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 58 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 59 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 60 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 61 62 /* Master controller (MCR) register */ 63 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 64 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 65 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 66 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 67 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 68 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 69 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 70 71 /* Status register (SR) */ 72 #define I2C_SR_OP (0x3 << 0) /* Operation */ 73 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 74 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 75 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 76 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 77 78 /* Interrupt mask set/clear (IMSCR) bits */ 79 #define I2C_IT_TXFE (0x1 << 0) 80 #define I2C_IT_TXFNE (0x1 << 1) 81 #define I2C_IT_TXFF (0x1 << 2) 82 #define I2C_IT_TXFOVR (0x1 << 3) 83 #define I2C_IT_RXFE (0x1 << 4) 84 #define I2C_IT_RXFNF (0x1 << 5) 85 #define I2C_IT_RXFF (0x1 << 6) 86 #define I2C_IT_RFSR (0x1 << 16) 87 #define I2C_IT_RFSE (0x1 << 17) 88 #define I2C_IT_WTSR (0x1 << 18) 89 #define I2C_IT_MTD (0x1 << 19) 90 #define I2C_IT_STD (0x1 << 20) 91 #define I2C_IT_MAL (0x1 << 24) 92 #define I2C_IT_BERR (0x1 << 25) 93 #define I2C_IT_MTDWS (0x1 << 28) 94 95 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 96 97 /* some bits in ICR are reserved */ 98 #define I2C_CLEAR_ALL_INTS 0x131f007f 99 100 /* first three msb bits are reserved */ 101 #define IRQ_MASK(mask) (mask & 0x1fffffff) 102 103 /* maximum threshold value */ 104 #define MAX_I2C_FIFO_THRESHOLD 15 105 106 enum i2c_freq_mode { 107 I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */ 108 I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */ 109 I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */ 110 I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */ 111 }; 112 113 /** 114 * struct nmk_i2c_controller - client specific controller configuration 115 * @clk_freq: clock frequency for the operation mode 116 * @tft: Tx FIFO Threshold in bytes 117 * @rft: Rx FIFO Threshold in bytes 118 * @timeout Slave response timeout(ms) 119 * @sm: speed mode 120 */ 121 struct nmk_i2c_controller { 122 u32 clk_freq; 123 unsigned char tft; 124 unsigned char rft; 125 int timeout; 126 enum i2c_freq_mode sm; 127 }; 128 129 /** 130 * struct i2c_vendor_data - per-vendor variations 131 * @has_mtdws: variant has the MTDWS bit 132 * @fifodepth: variant FIFO depth 133 */ 134 struct i2c_vendor_data { 135 bool has_mtdws; 136 u32 fifodepth; 137 }; 138 139 enum i2c_status { 140 I2C_NOP, 141 I2C_ON_GOING, 142 I2C_OK, 143 I2C_ABORT 144 }; 145 146 /* operation */ 147 enum i2c_operation { 148 I2C_NO_OPERATION = 0xff, 149 I2C_WRITE = 0x00, 150 I2C_READ = 0x01 151 }; 152 153 /** 154 * struct i2c_nmk_client - client specific data 155 * @slave_adr: 7-bit slave address 156 * @count: no. bytes to be transferred 157 * @buffer: client data buffer 158 * @xfer_bytes: bytes transferred till now 159 * @operation: current I2C operation 160 */ 161 struct i2c_nmk_client { 162 unsigned short slave_adr; 163 unsigned long count; 164 unsigned char *buffer; 165 unsigned long xfer_bytes; 166 enum i2c_operation operation; 167 }; 168 169 /** 170 * struct nmk_i2c_dev - private data structure of the controller. 171 * @vendor: vendor data for this variant. 172 * @adev: parent amba device. 173 * @adap: corresponding I2C adapter. 174 * @irq: interrupt line for the controller. 175 * @virtbase: virtual io memory area. 176 * @clk: hardware i2c block clock. 177 * @cfg: machine provided controller configuration. 178 * @cli: holder of client specific data. 179 * @stop: stop condition. 180 * @xfer_complete: acknowledge completion for a I2C message. 181 * @result: controller propogated result. 182 * @busy: Busy doing transfer. 183 */ 184 struct nmk_i2c_dev { 185 struct i2c_vendor_data *vendor; 186 struct amba_device *adev; 187 struct i2c_adapter adap; 188 int irq; 189 void __iomem *virtbase; 190 struct clk *clk; 191 struct nmk_i2c_controller cfg; 192 struct i2c_nmk_client cli; 193 int stop; 194 struct completion xfer_complete; 195 int result; 196 bool busy; 197 }; 198 199 /* controller's abort causes */ 200 static const char *abort_causes[] = { 201 "no ack received after address transmission", 202 "no ack received during data phase", 203 "ack received after xmission of master code", 204 "master lost arbitration", 205 "slave restarts", 206 "slave reset", 207 "overflow, maxsize is 2047 bytes", 208 }; 209 210 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 211 { 212 writel(readl(reg) | mask, reg); 213 } 214 215 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 216 { 217 writel(readl(reg) & ~mask, reg); 218 } 219 220 /** 221 * flush_i2c_fifo() - This function flushes the I2C FIFO 222 * @dev: private data of I2C Driver 223 * 224 * This function flushes the I2C Tx and Rx FIFOs. It returns 225 * 0 on successful flushing of FIFO 226 */ 227 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 228 { 229 #define LOOP_ATTEMPTS 10 230 int i; 231 unsigned long timeout; 232 233 /* 234 * flush the transmit and receive FIFO. The flushing 235 * operation takes several cycles before to be completed. 236 * On the completion, the I2C internal logic clears these 237 * bits, until then no one must access Tx, Rx FIFO and 238 * should poll on these bits waiting for the completion. 239 */ 240 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 241 242 for (i = 0; i < LOOP_ATTEMPTS; i++) { 243 timeout = jiffies + dev->adap.timeout; 244 245 while (!time_after(jiffies, timeout)) { 246 if ((readl(dev->virtbase + I2C_CR) & 247 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 248 return 0; 249 } 250 } 251 252 dev_err(&dev->adev->dev, 253 "flushing operation timed out giving up after %d attempts", 254 LOOP_ATTEMPTS); 255 256 return -ETIMEDOUT; 257 } 258 259 /** 260 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 261 * @dev: private data of I2C Driver 262 */ 263 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 264 { 265 u32 mask = IRQ_MASK(0); 266 writel(mask, dev->virtbase + I2C_IMSCR); 267 } 268 269 /** 270 * clear_all_interrupts() - Clear all interrupts of I2C Controller 271 * @dev: private data of I2C Driver 272 */ 273 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 274 { 275 u32 mask; 276 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 277 writel(mask, dev->virtbase + I2C_ICR); 278 } 279 280 /** 281 * init_hw() - initialize the I2C hardware 282 * @dev: private data of I2C Driver 283 */ 284 static int init_hw(struct nmk_i2c_dev *dev) 285 { 286 int stat; 287 288 stat = flush_i2c_fifo(dev); 289 if (stat) 290 goto exit; 291 292 /* disable the controller */ 293 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 294 295 disable_all_interrupts(dev); 296 297 clear_all_interrupts(dev); 298 299 dev->cli.operation = I2C_NO_OPERATION; 300 301 exit: 302 return stat; 303 } 304 305 /* enable peripheral, master mode operation */ 306 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 307 308 /** 309 * load_i2c_mcr_reg() - load the MCR register 310 * @dev: private data of controller 311 * @flags: message flags 312 */ 313 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) 314 { 315 u32 mcr = 0; 316 unsigned short slave_adr_3msb_bits; 317 318 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 319 320 if (unlikely(flags & I2C_M_TEN)) { 321 /* 10-bit address transaction */ 322 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); 323 /* 324 * Get the top 3 bits. 325 * EA10 represents extended address in MCR. This includes 326 * the extension (MSB bits) of the 7 bit address loaded 327 * in A7 328 */ 329 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; 330 331 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); 332 } else { 333 /* 7-bit address transaction */ 334 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 335 } 336 337 /* start byte procedure not applied */ 338 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 339 340 /* check the operation, master read/write? */ 341 if (dev->cli.operation == I2C_WRITE) 342 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 343 else 344 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 345 346 /* stop or repeated start? */ 347 if (dev->stop) 348 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 349 else 350 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 351 352 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 353 354 return mcr; 355 } 356 357 /** 358 * setup_i2c_controller() - setup the controller 359 * @dev: private data of controller 360 */ 361 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 362 { 363 u32 brcr1, brcr2; 364 u32 i2c_clk, div; 365 u32 ns; 366 u16 slsu; 367 368 writel(0x0, dev->virtbase + I2C_CR); 369 writel(0x0, dev->virtbase + I2C_HSMCR); 370 writel(0x0, dev->virtbase + I2C_TFTR); 371 writel(0x0, dev->virtbase + I2C_RFTR); 372 writel(0x0, dev->virtbase + I2C_DMAR); 373 374 i2c_clk = clk_get_rate(dev->clk); 375 376 /* 377 * set the slsu: 378 * 379 * slsu defines the data setup time after SCL clock 380 * stretching in terms of i2c clk cycles + 1 (zero means 381 * "wait one cycle"), the needed setup time for the three 382 * modes are 250ns, 100ns, 10ns respectively. 383 * 384 * As the time for one cycle T in nanoseconds is 385 * T = (1/f) * 1000000000 => 386 * slsu = cycles / (1000000000 / f) + 1 387 */ 388 ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk); 389 switch (dev->cfg.sm) { 390 case I2C_FREQ_MODE_FAST: 391 case I2C_FREQ_MODE_FAST_PLUS: 392 slsu = DIV_ROUND_UP(100, ns); /* Fast */ 393 break; 394 case I2C_FREQ_MODE_HIGH_SPEED: 395 slsu = DIV_ROUND_UP(10, ns); /* High */ 396 break; 397 case I2C_FREQ_MODE_STANDARD: 398 default: 399 slsu = DIV_ROUND_UP(250, ns); /* Standard */ 400 break; 401 } 402 slsu += 1; 403 404 dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu); 405 writel(slsu << 16, dev->virtbase + I2C_SCR); 406 407 /* 408 * The spec says, in case of std. mode the divider is 409 * 2 whereas it is 3 for fast and fastplus mode of 410 * operation. TODO - high speed support. 411 */ 412 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 413 414 /* 415 * generate the mask for baud rate counters. The controller 416 * has two baud rate counters. One is used for High speed 417 * operation, and the other is for std, fast mode, fast mode 418 * plus operation. Currently we do not supprt high speed mode 419 * so set brcr1 to 0. 420 */ 421 brcr1 = 0 << 16; 422 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 423 424 /* set the baud rate counter register */ 425 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 426 427 /* 428 * set the speed mode. Currently we support 429 * only standard and fast mode of operation 430 * TODO - support for fast mode plus (up to 1Mb/s) 431 * and high speed (up to 3.4 Mb/s) 432 */ 433 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 434 dev_err(&dev->adev->dev, 435 "do not support this mode defaulting to std. mode\n"); 436 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 437 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 438 writel(I2C_FREQ_MODE_STANDARD << 4, 439 dev->virtbase + I2C_CR); 440 } 441 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 442 443 /* set the Tx and Rx FIFO threshold */ 444 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 445 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 446 } 447 448 /** 449 * read_i2c() - Read from I2C client device 450 * @dev: private data of I2C Driver 451 * @flags: message flags 452 * 453 * This function reads from i2c client device when controller is in 454 * master mode. There is a completion timeout. If there is no transfer 455 * before timeout error is returned. 456 */ 457 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 458 { 459 u32 status = 0; 460 u32 mcr, irq_mask; 461 int timeout; 462 463 mcr = load_i2c_mcr_reg(dev, flags); 464 writel(mcr, dev->virtbase + I2C_MCR); 465 466 /* load the current CR value */ 467 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 468 dev->virtbase + I2C_CR); 469 470 /* enable the controller */ 471 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 472 473 init_completion(&dev->xfer_complete); 474 475 /* enable interrupts by setting the mask */ 476 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 477 I2C_IT_MAL | I2C_IT_BERR); 478 479 if (dev->stop || !dev->vendor->has_mtdws) 480 irq_mask |= I2C_IT_MTD; 481 else 482 irq_mask |= I2C_IT_MTDWS; 483 484 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 485 486 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 487 dev->virtbase + I2C_IMSCR); 488 489 timeout = wait_for_completion_timeout( 490 &dev->xfer_complete, dev->adap.timeout); 491 492 if (timeout == 0) { 493 /* Controller timed out */ 494 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 495 dev->cli.slave_adr); 496 status = -ETIMEDOUT; 497 } 498 return status; 499 } 500 501 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) 502 { 503 int count; 504 505 for (count = (no_bytes - 2); 506 (count > 0) && 507 (dev->cli.count != 0); 508 count--) { 509 /* write to the Tx FIFO */ 510 writeb(*dev->cli.buffer, 511 dev->virtbase + I2C_TFR); 512 dev->cli.buffer++; 513 dev->cli.count--; 514 dev->cli.xfer_bytes++; 515 } 516 517 } 518 519 /** 520 * write_i2c() - Write data to I2C client. 521 * @dev: private data of I2C Driver 522 * @flags: message flags 523 * 524 * This function writes data to I2C client 525 */ 526 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) 527 { 528 u32 status = 0; 529 u32 mcr, irq_mask; 530 int timeout; 531 532 mcr = load_i2c_mcr_reg(dev, flags); 533 534 writel(mcr, dev->virtbase + I2C_MCR); 535 536 /* load the current CR value */ 537 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 538 dev->virtbase + I2C_CR); 539 540 /* enable the controller */ 541 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 542 543 init_completion(&dev->xfer_complete); 544 545 /* enable interrupts by settings the masks */ 546 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 547 548 /* Fill the TX FIFO with transmit data */ 549 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); 550 551 if (dev->cli.count != 0) 552 irq_mask |= I2C_IT_TXFNE; 553 554 /* 555 * check if we want to transfer a single or multiple bytes, if so 556 * set the MTDWS bit (Master Transaction Done Without Stop) 557 * to start repeated start operation 558 */ 559 if (dev->stop || !dev->vendor->has_mtdws) 560 irq_mask |= I2C_IT_MTD; 561 else 562 irq_mask |= I2C_IT_MTDWS; 563 564 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 565 566 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 567 dev->virtbase + I2C_IMSCR); 568 569 timeout = wait_for_completion_timeout( 570 &dev->xfer_complete, dev->adap.timeout); 571 572 if (timeout == 0) { 573 /* Controller timed out */ 574 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 575 dev->cli.slave_adr); 576 status = -ETIMEDOUT; 577 } 578 579 return status; 580 } 581 582 /** 583 * nmk_i2c_xfer_one() - transmit a single I2C message 584 * @dev: device with a message encoded into it 585 * @flags: message flags 586 */ 587 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) 588 { 589 int status; 590 591 if (flags & I2C_M_RD) { 592 /* read operation */ 593 dev->cli.operation = I2C_READ; 594 status = read_i2c(dev, flags); 595 } else { 596 /* write operation */ 597 dev->cli.operation = I2C_WRITE; 598 status = write_i2c(dev, flags); 599 } 600 601 if (status || (dev->result)) { 602 u32 i2c_sr; 603 u32 cause; 604 605 i2c_sr = readl(dev->virtbase + I2C_SR); 606 /* 607 * Check if the controller I2C operation status 608 * is set to ABORT(11b). 609 */ 610 if (((i2c_sr >> 2) & 0x3) == 0x3) { 611 /* get the abort cause */ 612 cause = (i2c_sr >> 4) & 0x7; 613 dev_err(&dev->adev->dev, "%s\n", 614 cause >= ARRAY_SIZE(abort_causes) ? 615 "unknown reason" : 616 abort_causes[cause]); 617 } 618 619 (void) init_hw(dev); 620 621 status = status ? status : dev->result; 622 } 623 624 return status; 625 } 626 627 /** 628 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 629 * @i2c_adap: Adapter pointer to the controller 630 * @msgs: Pointer to data to be written. 631 * @num_msgs: Number of messages to be executed 632 * 633 * This is the function called by the generic kernel i2c_transfer() 634 * or i2c_smbus...() API calls. Note that this code is protected by the 635 * semaphore set in the kernel i2c_transfer() function. 636 * 637 * NOTE: 638 * READ TRANSFER : We impose a restriction of the first message to be the 639 * index message for any read transaction. 640 * - a no index is coded as '0', 641 * - 2byte big endian index is coded as '3' 642 * !!! msg[0].buf holds the actual index. 643 * This is compatible with generic messages of smbus emulator 644 * that send a one byte index. 645 * eg. a I2C transation to read 2 bytes from index 0 646 * idx = 0; 647 * msg[0].addr = client->addr; 648 * msg[0].flags = 0x0; 649 * msg[0].len = 1; 650 * msg[0].buf = &idx; 651 * 652 * msg[1].addr = client->addr; 653 * msg[1].flags = I2C_M_RD; 654 * msg[1].len = 2; 655 * msg[1].buf = rd_buff 656 * i2c_transfer(adap, msg, 2); 657 * 658 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 659 * If you want to emulate an SMBUS write transaction put the 660 * index as first byte(or first and second) in the payload. 661 * eg. a I2C transation to write 2 bytes from index 1 662 * wr_buff[0] = 0x1; 663 * wr_buff[1] = 0x23; 664 * wr_buff[2] = 0x46; 665 * msg[0].flags = 0x0; 666 * msg[0].len = 3; 667 * msg[0].buf = wr_buff; 668 * i2c_transfer(adap, msg, 1); 669 * 670 * To read or write a block of data (multiple bytes) using SMBUS emulation 671 * please use the i2c_smbus_read_i2c_block_data() 672 * or i2c_smbus_write_i2c_block_data() API 673 */ 674 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 675 struct i2c_msg msgs[], int num_msgs) 676 { 677 int status; 678 int i; 679 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 680 int j; 681 682 dev->busy = true; 683 684 pm_runtime_get_sync(&dev->adev->dev); 685 686 status = clk_prepare_enable(dev->clk); 687 if (status) { 688 dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); 689 goto out_clk; 690 } 691 692 /* Optionaly enable pins to be muxed in and configured */ 693 pinctrl_pm_select_default_state(&dev->adev->dev); 694 695 status = init_hw(dev); 696 if (status) 697 goto out; 698 699 /* Attempt three times to send the message queue */ 700 for (j = 0; j < 3; j++) { 701 /* setup the i2c controller */ 702 setup_i2c_controller(dev); 703 704 for (i = 0; i < num_msgs; i++) { 705 dev->cli.slave_adr = msgs[i].addr; 706 dev->cli.buffer = msgs[i].buf; 707 dev->cli.count = msgs[i].len; 708 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 709 dev->result = 0; 710 711 status = nmk_i2c_xfer_one(dev, msgs[i].flags); 712 if (status != 0) 713 break; 714 } 715 if (status == 0) 716 break; 717 } 718 719 out: 720 clk_disable_unprepare(dev->clk); 721 out_clk: 722 /* Optionally let pins go into idle state */ 723 pinctrl_pm_select_idle_state(&dev->adev->dev); 724 725 pm_runtime_put_sync(&dev->adev->dev); 726 727 dev->busy = false; 728 729 /* return the no. messages processed */ 730 if (status) 731 return status; 732 else 733 return num_msgs; 734 } 735 736 /** 737 * disable_interrupts() - disable the interrupts 738 * @dev: private data of controller 739 * @irq: interrupt number 740 */ 741 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 742 { 743 irq = IRQ_MASK(irq); 744 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 745 dev->virtbase + I2C_IMSCR); 746 return 0; 747 } 748 749 /** 750 * i2c_irq_handler() - interrupt routine 751 * @irq: interrupt number 752 * @arg: data passed to the handler 753 * 754 * This is the interrupt handler for the i2c driver. Currently 755 * it handles the major interrupts like Rx & Tx FIFO management 756 * interrupts, master transaction interrupts, arbitration and 757 * bus error interrupts. The rest of the interrupts are treated as 758 * unhandled. 759 */ 760 static irqreturn_t i2c_irq_handler(int irq, void *arg) 761 { 762 struct nmk_i2c_dev *dev = arg; 763 u32 tft, rft; 764 u32 count; 765 u32 misr, src; 766 767 /* load Tx FIFO and Rx FIFO threshold values */ 768 tft = readl(dev->virtbase + I2C_TFTR); 769 rft = readl(dev->virtbase + I2C_RFTR); 770 771 /* read interrupt status register */ 772 misr = readl(dev->virtbase + I2C_MISR); 773 774 src = __ffs(misr); 775 switch ((1 << src)) { 776 777 /* Transmit FIFO nearly empty interrupt */ 778 case I2C_IT_TXFNE: 779 { 780 if (dev->cli.operation == I2C_READ) { 781 /* 782 * in read operation why do we care for writing? 783 * so disable the Transmit FIFO interrupt 784 */ 785 disable_interrupts(dev, I2C_IT_TXFNE); 786 } else { 787 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); 788 /* 789 * if done, close the transfer by disabling the 790 * corresponding TXFNE interrupt 791 */ 792 if (dev->cli.count == 0) 793 disable_interrupts(dev, I2C_IT_TXFNE); 794 } 795 } 796 break; 797 798 /* 799 * Rx FIFO nearly full interrupt. 800 * This is set when the numer of entries in Rx FIFO is 801 * greater or equal than the threshold value programmed 802 * in RFT 803 */ 804 case I2C_IT_RXFNF: 805 for (count = rft; count > 0; count--) { 806 /* Read the Rx FIFO */ 807 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 808 dev->cli.buffer++; 809 } 810 dev->cli.count -= rft; 811 dev->cli.xfer_bytes += rft; 812 break; 813 814 /* Rx FIFO full */ 815 case I2C_IT_RXFF: 816 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 817 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 818 dev->cli.buffer++; 819 } 820 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 821 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 822 break; 823 824 /* Master Transaction Done with/without stop */ 825 case I2C_IT_MTD: 826 case I2C_IT_MTDWS: 827 if (dev->cli.operation == I2C_READ) { 828 while (!(readl(dev->virtbase + I2C_RISR) 829 & I2C_IT_RXFE)) { 830 if (dev->cli.count == 0) 831 break; 832 *dev->cli.buffer = 833 readb(dev->virtbase + I2C_RFR); 834 dev->cli.buffer++; 835 dev->cli.count--; 836 dev->cli.xfer_bytes++; 837 } 838 } 839 840 disable_all_interrupts(dev); 841 clear_all_interrupts(dev); 842 843 if (dev->cli.count) { 844 dev->result = -EIO; 845 dev_err(&dev->adev->dev, 846 "%lu bytes still remain to be xfered\n", 847 dev->cli.count); 848 (void) init_hw(dev); 849 } 850 complete(&dev->xfer_complete); 851 852 break; 853 854 /* Master Arbitration lost interrupt */ 855 case I2C_IT_MAL: 856 dev->result = -EIO; 857 (void) init_hw(dev); 858 859 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 860 complete(&dev->xfer_complete); 861 862 break; 863 864 /* 865 * Bus Error interrupt. 866 * This happens when an unexpected start/stop condition occurs 867 * during the transaction. 868 */ 869 case I2C_IT_BERR: 870 dev->result = -EIO; 871 /* get the status */ 872 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 873 (void) init_hw(dev); 874 875 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 876 complete(&dev->xfer_complete); 877 878 break; 879 880 /* 881 * Tx FIFO overrun interrupt. 882 * This is set when a write operation in Tx FIFO is performed and 883 * the Tx FIFO is full. 884 */ 885 case I2C_IT_TXFOVR: 886 dev->result = -EIO; 887 (void) init_hw(dev); 888 889 dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); 890 complete(&dev->xfer_complete); 891 892 break; 893 894 /* unhandled interrupts by this driver - TODO*/ 895 case I2C_IT_TXFE: 896 case I2C_IT_TXFF: 897 case I2C_IT_RXFE: 898 case I2C_IT_RFSR: 899 case I2C_IT_RFSE: 900 case I2C_IT_WTSR: 901 case I2C_IT_STD: 902 dev_err(&dev->adev->dev, "unhandled Interrupt\n"); 903 break; 904 default: 905 dev_err(&dev->adev->dev, "spurious Interrupt..\n"); 906 break; 907 } 908 909 return IRQ_HANDLED; 910 } 911 912 913 #ifdef CONFIG_PM 914 static int nmk_i2c_suspend(struct device *dev) 915 { 916 struct amba_device *adev = to_amba_device(dev); 917 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 918 919 if (nmk_i2c->busy) 920 return -EBUSY; 921 922 pinctrl_pm_select_sleep_state(dev); 923 924 return 0; 925 } 926 927 static int nmk_i2c_resume(struct device *dev) 928 { 929 /* First go to the default state */ 930 pinctrl_pm_select_default_state(dev); 931 /* Then let's idle the pins until the next transfer happens */ 932 pinctrl_pm_select_idle_state(dev); 933 934 return 0; 935 } 936 #else 937 #define nmk_i2c_suspend NULL 938 #define nmk_i2c_resume NULL 939 #endif 940 941 /* 942 * We use noirq so that we suspend late and resume before the wakeup interrupt 943 * to ensure that we do the !pm_runtime_suspended() check in resume before 944 * there has been a regular pm runtime resume (via pm_runtime_get_sync()). 945 */ 946 static const struct dev_pm_ops nmk_i2c_pm = { 947 .suspend_noirq = nmk_i2c_suspend, 948 .resume_noirq = nmk_i2c_resume, 949 }; 950 951 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 952 { 953 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 954 } 955 956 static const struct i2c_algorithm nmk_i2c_algo = { 957 .master_xfer = nmk_i2c_xfer, 958 .functionality = nmk_i2c_functionality 959 }; 960 961 static struct nmk_i2c_controller u8500_i2c = { 962 .tft = 1, /* Tx FIFO threshold */ 963 .rft = 8, /* Rx FIFO threshold */ 964 .clk_freq = 400000, /* fast mode operation */ 965 .timeout = 200, /* Slave response timeout(ms) */ 966 .sm = I2C_FREQ_MODE_FAST, 967 }; 968 969 static void nmk_i2c_of_probe(struct device_node *np, 970 struct nmk_i2c_controller *pdata) 971 { 972 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); 973 974 /* This driver only supports 'standard' and 'fast' modes of operation. */ 975 if (pdata->clk_freq <= 100000) 976 pdata->sm = I2C_FREQ_MODE_STANDARD; 977 else 978 pdata->sm = I2C_FREQ_MODE_FAST; 979 } 980 981 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 982 { 983 int ret = 0; 984 struct nmk_i2c_controller *pdata = dev_get_platdata(&adev->dev); 985 struct device_node *np = adev->dev.of_node; 986 struct nmk_i2c_dev *dev; 987 struct i2c_adapter *adap; 988 struct i2c_vendor_data *vendor = id->data; 989 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; 990 991 if (!pdata) { 992 if (np) { 993 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); 994 if (!pdata) { 995 ret = -ENOMEM; 996 goto err_no_mem; 997 } 998 /* Provide the default configuration as a base. */ 999 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); 1000 nmk_i2c_of_probe(np, pdata); 1001 } else 1002 /* No i2c configuration found, using the default. */ 1003 pdata = &u8500_i2c; 1004 } 1005 1006 if (pdata->tft > max_fifo_threshold) { 1007 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", 1008 pdata->tft, max_fifo_threshold); 1009 pdata->tft = max_fifo_threshold; 1010 } 1011 1012 if (pdata->rft > max_fifo_threshold) { 1013 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", 1014 pdata->rft, max_fifo_threshold); 1015 pdata->rft = max_fifo_threshold; 1016 } 1017 1018 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 1019 if (!dev) { 1020 dev_err(&adev->dev, "cannot allocate memory\n"); 1021 ret = -ENOMEM; 1022 goto err_no_mem; 1023 } 1024 dev->vendor = vendor; 1025 dev->busy = false; 1026 dev->adev = adev; 1027 amba_set_drvdata(adev, dev); 1028 1029 /* Select default pin state */ 1030 pinctrl_pm_select_default_state(&adev->dev); 1031 /* If possible, let's go to idle until the first transfer */ 1032 pinctrl_pm_select_idle_state(&adev->dev); 1033 1034 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 1035 if (!dev->virtbase) { 1036 ret = -ENOMEM; 1037 goto err_no_ioremap; 1038 } 1039 1040 dev->irq = adev->irq[0]; 1041 ret = request_irq(dev->irq, i2c_irq_handler, 0, 1042 DRIVER_NAME, dev); 1043 if (ret) { 1044 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); 1045 goto err_irq; 1046 } 1047 1048 pm_suspend_ignore_children(&adev->dev, true); 1049 1050 dev->clk = clk_get(&adev->dev, NULL); 1051 if (IS_ERR(dev->clk)) { 1052 dev_err(&adev->dev, "could not get i2c clock\n"); 1053 ret = PTR_ERR(dev->clk); 1054 goto err_no_clk; 1055 } 1056 1057 adap = &dev->adap; 1058 adap->dev.of_node = np; 1059 adap->dev.parent = &adev->dev; 1060 adap->owner = THIS_MODULE; 1061 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1062 adap->algo = &nmk_i2c_algo; 1063 adap->timeout = msecs_to_jiffies(pdata->timeout); 1064 snprintf(adap->name, sizeof(adap->name), 1065 "Nomadik I2C at %pR", &adev->res); 1066 1067 /* fetch the controller configuration from machine */ 1068 dev->cfg.clk_freq = pdata->clk_freq; 1069 dev->cfg.tft = pdata->tft; 1070 dev->cfg.rft = pdata->rft; 1071 dev->cfg.sm = pdata->sm; 1072 1073 i2c_set_adapdata(adap, dev); 1074 1075 dev_info(&adev->dev, 1076 "initialize %s on virtual base %p\n", 1077 adap->name, dev->virtbase); 1078 1079 ret = i2c_add_adapter(adap); 1080 if (ret) { 1081 dev_err(&adev->dev, "failed to add adapter\n"); 1082 goto err_add_adap; 1083 } 1084 1085 pm_runtime_put(&adev->dev); 1086 1087 return 0; 1088 1089 err_add_adap: 1090 clk_put(dev->clk); 1091 err_no_clk: 1092 free_irq(dev->irq, dev); 1093 err_irq: 1094 iounmap(dev->virtbase); 1095 err_no_ioremap: 1096 kfree(dev); 1097 err_no_mem: 1098 1099 return ret; 1100 } 1101 1102 static int nmk_i2c_remove(struct amba_device *adev) 1103 { 1104 struct resource *res = &adev->res; 1105 struct nmk_i2c_dev *dev = amba_get_drvdata(adev); 1106 1107 i2c_del_adapter(&dev->adap); 1108 flush_i2c_fifo(dev); 1109 disable_all_interrupts(dev); 1110 clear_all_interrupts(dev); 1111 /* disable the controller */ 1112 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1113 free_irq(dev->irq, dev); 1114 iounmap(dev->virtbase); 1115 if (res) 1116 release_mem_region(res->start, resource_size(res)); 1117 clk_put(dev->clk); 1118 pm_runtime_disable(&adev->dev); 1119 kfree(dev); 1120 1121 return 0; 1122 } 1123 1124 static struct i2c_vendor_data vendor_stn8815 = { 1125 .has_mtdws = false, 1126 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ 1127 }; 1128 1129 static struct i2c_vendor_data vendor_db8500 = { 1130 .has_mtdws = true, 1131 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ 1132 }; 1133 1134 static struct amba_id nmk_i2c_ids[] = { 1135 { 1136 .id = 0x00180024, 1137 .mask = 0x00ffffff, 1138 .data = &vendor_stn8815, 1139 }, 1140 { 1141 .id = 0x00380024, 1142 .mask = 0x00ffffff, 1143 .data = &vendor_db8500, 1144 }, 1145 {}, 1146 }; 1147 1148 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1149 1150 static struct amba_driver nmk_i2c_driver = { 1151 .drv = { 1152 .owner = THIS_MODULE, 1153 .name = DRIVER_NAME, 1154 .pm = &nmk_i2c_pm, 1155 }, 1156 .id_table = nmk_i2c_ids, 1157 .probe = nmk_i2c_probe, 1158 .remove = nmk_i2c_remove, 1159 }; 1160 1161 static int __init nmk_i2c_init(void) 1162 { 1163 return amba_driver_register(&nmk_i2c_driver); 1164 } 1165 1166 static void __exit nmk_i2c_exit(void) 1167 { 1168 amba_driver_unregister(&nmk_i2c_driver); 1169 } 1170 1171 subsys_initcall(nmk_i2c_init); 1172 module_exit(nmk_i2c_exit); 1173 1174 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 1175 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1176 MODULE_LICENSE("GPL"); 1177