1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/amba/bus.h> 18 #include <linux/slab.h> 19 #include <linux/interrupt.h> 20 #include <linux/i2c.h> 21 #include <linux/err.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/platform_data/i2c-nomadik.h> 26 #include <linux/of.h> 27 #include <linux/of_i2c.h> 28 #include <linux/pinctrl/consumer.h> 29 30 #define DRIVER_NAME "nmk-i2c" 31 32 /* I2C Controller register offsets */ 33 #define I2C_CR (0x000) 34 #define I2C_SCR (0x004) 35 #define I2C_HSMCR (0x008) 36 #define I2C_MCR (0x00C) 37 #define I2C_TFR (0x010) 38 #define I2C_SR (0x014) 39 #define I2C_RFR (0x018) 40 #define I2C_TFTR (0x01C) 41 #define I2C_RFTR (0x020) 42 #define I2C_DMAR (0x024) 43 #define I2C_BRCR (0x028) 44 #define I2C_IMSCR (0x02C) 45 #define I2C_RISR (0x030) 46 #define I2C_MISR (0x034) 47 #define I2C_ICR (0x038) 48 49 /* Control registers */ 50 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 51 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 52 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 53 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 54 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 55 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 56 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 57 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 58 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 59 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 60 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 61 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 62 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 63 64 /* Master controller (MCR) register */ 65 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 66 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 67 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 68 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 69 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 70 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 71 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 72 73 /* Status register (SR) */ 74 #define I2C_SR_OP (0x3 << 0) /* Operation */ 75 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 76 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 77 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 78 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 79 80 /* Interrupt mask set/clear (IMSCR) bits */ 81 #define I2C_IT_TXFE (0x1 << 0) 82 #define I2C_IT_TXFNE (0x1 << 1) 83 #define I2C_IT_TXFF (0x1 << 2) 84 #define I2C_IT_TXFOVR (0x1 << 3) 85 #define I2C_IT_RXFE (0x1 << 4) 86 #define I2C_IT_RXFNF (0x1 << 5) 87 #define I2C_IT_RXFF (0x1 << 6) 88 #define I2C_IT_RFSR (0x1 << 16) 89 #define I2C_IT_RFSE (0x1 << 17) 90 #define I2C_IT_WTSR (0x1 << 18) 91 #define I2C_IT_MTD (0x1 << 19) 92 #define I2C_IT_STD (0x1 << 20) 93 #define I2C_IT_MAL (0x1 << 24) 94 #define I2C_IT_BERR (0x1 << 25) 95 #define I2C_IT_MTDWS (0x1 << 28) 96 97 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 98 99 /* some bits in ICR are reserved */ 100 #define I2C_CLEAR_ALL_INTS 0x131f007f 101 102 /* first three msb bits are reserved */ 103 #define IRQ_MASK(mask) (mask & 0x1fffffff) 104 105 /* maximum threshold value */ 106 #define MAX_I2C_FIFO_THRESHOLD 15 107 108 /** 109 * struct i2c_vendor_data - per-vendor variations 110 * @has_mtdws: variant has the MTDWS bit 111 * @fifodepth: variant FIFO depth 112 */ 113 struct i2c_vendor_data { 114 bool has_mtdws; 115 u32 fifodepth; 116 }; 117 118 enum i2c_status { 119 I2C_NOP, 120 I2C_ON_GOING, 121 I2C_OK, 122 I2C_ABORT 123 }; 124 125 /* operation */ 126 enum i2c_operation { 127 I2C_NO_OPERATION = 0xff, 128 I2C_WRITE = 0x00, 129 I2C_READ = 0x01 130 }; 131 132 /** 133 * struct i2c_nmk_client - client specific data 134 * @slave_adr: 7-bit slave address 135 * @count: no. bytes to be transferred 136 * @buffer: client data buffer 137 * @xfer_bytes: bytes transferred till now 138 * @operation: current I2C operation 139 */ 140 struct i2c_nmk_client { 141 unsigned short slave_adr; 142 unsigned long count; 143 unsigned char *buffer; 144 unsigned long xfer_bytes; 145 enum i2c_operation operation; 146 }; 147 148 /** 149 * struct nmk_i2c_dev - private data structure of the controller. 150 * @vendor: vendor data for this variant. 151 * @adev: parent amba device. 152 * @adap: corresponding I2C adapter. 153 * @irq: interrupt line for the controller. 154 * @virtbase: virtual io memory area. 155 * @clk: hardware i2c block clock. 156 * @cfg: machine provided controller configuration. 157 * @cli: holder of client specific data. 158 * @stop: stop condition. 159 * @xfer_complete: acknowledge completion for a I2C message. 160 * @result: controller propogated result. 161 * @busy: Busy doing transfer. 162 */ 163 struct nmk_i2c_dev { 164 struct i2c_vendor_data *vendor; 165 struct amba_device *adev; 166 struct i2c_adapter adap; 167 int irq; 168 void __iomem *virtbase; 169 struct clk *clk; 170 struct nmk_i2c_controller cfg; 171 struct i2c_nmk_client cli; 172 int stop; 173 struct completion xfer_complete; 174 int result; 175 bool busy; 176 }; 177 178 /* controller's abort causes */ 179 static const char *abort_causes[] = { 180 "no ack received after address transmission", 181 "no ack received during data phase", 182 "ack received after xmission of master code", 183 "master lost arbitration", 184 "slave restarts", 185 "slave reset", 186 "overflow, maxsize is 2047 bytes", 187 }; 188 189 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 190 { 191 writel(readl(reg) | mask, reg); 192 } 193 194 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 195 { 196 writel(readl(reg) & ~mask, reg); 197 } 198 199 /** 200 * flush_i2c_fifo() - This function flushes the I2C FIFO 201 * @dev: private data of I2C Driver 202 * 203 * This function flushes the I2C Tx and Rx FIFOs. It returns 204 * 0 on successful flushing of FIFO 205 */ 206 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 207 { 208 #define LOOP_ATTEMPTS 10 209 int i; 210 unsigned long timeout; 211 212 /* 213 * flush the transmit and receive FIFO. The flushing 214 * operation takes several cycles before to be completed. 215 * On the completion, the I2C internal logic clears these 216 * bits, until then no one must access Tx, Rx FIFO and 217 * should poll on these bits waiting for the completion. 218 */ 219 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 220 221 for (i = 0; i < LOOP_ATTEMPTS; i++) { 222 timeout = jiffies + dev->adap.timeout; 223 224 while (!time_after(jiffies, timeout)) { 225 if ((readl(dev->virtbase + I2C_CR) & 226 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 227 return 0; 228 } 229 } 230 231 dev_err(&dev->adev->dev, 232 "flushing operation timed out giving up after %d attempts", 233 LOOP_ATTEMPTS); 234 235 return -ETIMEDOUT; 236 } 237 238 /** 239 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 240 * @dev: private data of I2C Driver 241 */ 242 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 243 { 244 u32 mask = IRQ_MASK(0); 245 writel(mask, dev->virtbase + I2C_IMSCR); 246 } 247 248 /** 249 * clear_all_interrupts() - Clear all interrupts of I2C Controller 250 * @dev: private data of I2C Driver 251 */ 252 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 253 { 254 u32 mask; 255 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 256 writel(mask, dev->virtbase + I2C_ICR); 257 } 258 259 /** 260 * init_hw() - initialize the I2C hardware 261 * @dev: private data of I2C Driver 262 */ 263 static int init_hw(struct nmk_i2c_dev *dev) 264 { 265 int stat; 266 267 stat = flush_i2c_fifo(dev); 268 if (stat) 269 goto exit; 270 271 /* disable the controller */ 272 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 273 274 disable_all_interrupts(dev); 275 276 clear_all_interrupts(dev); 277 278 dev->cli.operation = I2C_NO_OPERATION; 279 280 exit: 281 return stat; 282 } 283 284 /* enable peripheral, master mode operation */ 285 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 286 287 /** 288 * load_i2c_mcr_reg() - load the MCR register 289 * @dev: private data of controller 290 * @flags: message flags 291 */ 292 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) 293 { 294 u32 mcr = 0; 295 unsigned short slave_adr_3msb_bits; 296 297 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 298 299 if (unlikely(flags & I2C_M_TEN)) { 300 /* 10-bit address transaction */ 301 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); 302 /* 303 * Get the top 3 bits. 304 * EA10 represents extended address in MCR. This includes 305 * the extension (MSB bits) of the 7 bit address loaded 306 * in A7 307 */ 308 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; 309 310 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); 311 } else { 312 /* 7-bit address transaction */ 313 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 314 } 315 316 /* start byte procedure not applied */ 317 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 318 319 /* check the operation, master read/write? */ 320 if (dev->cli.operation == I2C_WRITE) 321 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 322 else 323 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 324 325 /* stop or repeated start? */ 326 if (dev->stop) 327 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 328 else 329 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 330 331 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 332 333 return mcr; 334 } 335 336 /** 337 * setup_i2c_controller() - setup the controller 338 * @dev: private data of controller 339 */ 340 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 341 { 342 u32 brcr1, brcr2; 343 u32 i2c_clk, div; 344 345 writel(0x0, dev->virtbase + I2C_CR); 346 writel(0x0, dev->virtbase + I2C_HSMCR); 347 writel(0x0, dev->virtbase + I2C_TFTR); 348 writel(0x0, dev->virtbase + I2C_RFTR); 349 writel(0x0, dev->virtbase + I2C_DMAR); 350 351 /* 352 * set the slsu: 353 * 354 * slsu defines the data setup time after SCL clock 355 * stretching in terms of i2c clk cycles. The 356 * needed setup time for the three modes are 250ns, 357 * 100ns, 10ns respectively thus leading to the values 358 * of 14, 6, 2 for a 48 MHz i2c clk. 359 */ 360 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); 361 362 i2c_clk = clk_get_rate(dev->clk); 363 364 /* 365 * The spec says, in case of std. mode the divider is 366 * 2 whereas it is 3 for fast and fastplus mode of 367 * operation. TODO - high speed support. 368 */ 369 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 370 371 /* 372 * generate the mask for baud rate counters. The controller 373 * has two baud rate counters. One is used for High speed 374 * operation, and the other is for std, fast mode, fast mode 375 * plus operation. Currently we do not supprt high speed mode 376 * so set brcr1 to 0. 377 */ 378 brcr1 = 0 << 16; 379 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 380 381 /* set the baud rate counter register */ 382 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 383 384 /* 385 * set the speed mode. Currently we support 386 * only standard and fast mode of operation 387 * TODO - support for fast mode plus (up to 1Mb/s) 388 * and high speed (up to 3.4 Mb/s) 389 */ 390 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 391 dev_err(&dev->adev->dev, 392 "do not support this mode defaulting to std. mode\n"); 393 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 394 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 395 writel(I2C_FREQ_MODE_STANDARD << 4, 396 dev->virtbase + I2C_CR); 397 } 398 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 399 400 /* set the Tx and Rx FIFO threshold */ 401 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 402 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 403 } 404 405 /** 406 * read_i2c() - Read from I2C client device 407 * @dev: private data of I2C Driver 408 * @flags: message flags 409 * 410 * This function reads from i2c client device when controller is in 411 * master mode. There is a completion timeout. If there is no transfer 412 * before timeout error is returned. 413 */ 414 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 415 { 416 u32 status = 0; 417 u32 mcr, irq_mask; 418 int timeout; 419 420 mcr = load_i2c_mcr_reg(dev, flags); 421 writel(mcr, dev->virtbase + I2C_MCR); 422 423 /* load the current CR value */ 424 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 425 dev->virtbase + I2C_CR); 426 427 /* enable the controller */ 428 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 429 430 init_completion(&dev->xfer_complete); 431 432 /* enable interrupts by setting the mask */ 433 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 434 I2C_IT_MAL | I2C_IT_BERR); 435 436 if (dev->stop || !dev->vendor->has_mtdws) 437 irq_mask |= I2C_IT_MTD; 438 else 439 irq_mask |= I2C_IT_MTDWS; 440 441 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 442 443 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 444 dev->virtbase + I2C_IMSCR); 445 446 timeout = wait_for_completion_timeout( 447 &dev->xfer_complete, dev->adap.timeout); 448 449 if (timeout == 0) { 450 /* Controller timed out */ 451 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 452 dev->cli.slave_adr); 453 status = -ETIMEDOUT; 454 } 455 return status; 456 } 457 458 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) 459 { 460 int count; 461 462 for (count = (no_bytes - 2); 463 (count > 0) && 464 (dev->cli.count != 0); 465 count--) { 466 /* write to the Tx FIFO */ 467 writeb(*dev->cli.buffer, 468 dev->virtbase + I2C_TFR); 469 dev->cli.buffer++; 470 dev->cli.count--; 471 dev->cli.xfer_bytes++; 472 } 473 474 } 475 476 /** 477 * write_i2c() - Write data to I2C client. 478 * @dev: private data of I2C Driver 479 * @flags: message flags 480 * 481 * This function writes data to I2C client 482 */ 483 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) 484 { 485 u32 status = 0; 486 u32 mcr, irq_mask; 487 int timeout; 488 489 mcr = load_i2c_mcr_reg(dev, flags); 490 491 writel(mcr, dev->virtbase + I2C_MCR); 492 493 /* load the current CR value */ 494 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 495 dev->virtbase + I2C_CR); 496 497 /* enable the controller */ 498 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 499 500 init_completion(&dev->xfer_complete); 501 502 /* enable interrupts by settings the masks */ 503 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 504 505 /* Fill the TX FIFO with transmit data */ 506 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); 507 508 if (dev->cli.count != 0) 509 irq_mask |= I2C_IT_TXFNE; 510 511 /* 512 * check if we want to transfer a single or multiple bytes, if so 513 * set the MTDWS bit (Master Transaction Done Without Stop) 514 * to start repeated start operation 515 */ 516 if (dev->stop || !dev->vendor->has_mtdws) 517 irq_mask |= I2C_IT_MTD; 518 else 519 irq_mask |= I2C_IT_MTDWS; 520 521 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 522 523 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 524 dev->virtbase + I2C_IMSCR); 525 526 timeout = wait_for_completion_timeout( 527 &dev->xfer_complete, dev->adap.timeout); 528 529 if (timeout == 0) { 530 /* Controller timed out */ 531 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 532 dev->cli.slave_adr); 533 status = -ETIMEDOUT; 534 } 535 536 return status; 537 } 538 539 /** 540 * nmk_i2c_xfer_one() - transmit a single I2C message 541 * @dev: device with a message encoded into it 542 * @flags: message flags 543 */ 544 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) 545 { 546 int status; 547 548 if (flags & I2C_M_RD) { 549 /* read operation */ 550 dev->cli.operation = I2C_READ; 551 status = read_i2c(dev, flags); 552 } else { 553 /* write operation */ 554 dev->cli.operation = I2C_WRITE; 555 status = write_i2c(dev, flags); 556 } 557 558 if (status || (dev->result)) { 559 u32 i2c_sr; 560 u32 cause; 561 562 i2c_sr = readl(dev->virtbase + I2C_SR); 563 /* 564 * Check if the controller I2C operation status 565 * is set to ABORT(11b). 566 */ 567 if (((i2c_sr >> 2) & 0x3) == 0x3) { 568 /* get the abort cause */ 569 cause = (i2c_sr >> 4) & 0x7; 570 dev_err(&dev->adev->dev, "%s\n", 571 cause >= ARRAY_SIZE(abort_causes) ? 572 "unknown reason" : 573 abort_causes[cause]); 574 } 575 576 (void) init_hw(dev); 577 578 status = status ? status : dev->result; 579 } 580 581 return status; 582 } 583 584 /** 585 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 586 * @i2c_adap: Adapter pointer to the controller 587 * @msgs: Pointer to data to be written. 588 * @num_msgs: Number of messages to be executed 589 * 590 * This is the function called by the generic kernel i2c_transfer() 591 * or i2c_smbus...() API calls. Note that this code is protected by the 592 * semaphore set in the kernel i2c_transfer() function. 593 * 594 * NOTE: 595 * READ TRANSFER : We impose a restriction of the first message to be the 596 * index message for any read transaction. 597 * - a no index is coded as '0', 598 * - 2byte big endian index is coded as '3' 599 * !!! msg[0].buf holds the actual index. 600 * This is compatible with generic messages of smbus emulator 601 * that send a one byte index. 602 * eg. a I2C transation to read 2 bytes from index 0 603 * idx = 0; 604 * msg[0].addr = client->addr; 605 * msg[0].flags = 0x0; 606 * msg[0].len = 1; 607 * msg[0].buf = &idx; 608 * 609 * msg[1].addr = client->addr; 610 * msg[1].flags = I2C_M_RD; 611 * msg[1].len = 2; 612 * msg[1].buf = rd_buff 613 * i2c_transfer(adap, msg, 2); 614 * 615 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 616 * If you want to emulate an SMBUS write transaction put the 617 * index as first byte(or first and second) in the payload. 618 * eg. a I2C transation to write 2 bytes from index 1 619 * wr_buff[0] = 0x1; 620 * wr_buff[1] = 0x23; 621 * wr_buff[2] = 0x46; 622 * msg[0].flags = 0x0; 623 * msg[0].len = 3; 624 * msg[0].buf = wr_buff; 625 * i2c_transfer(adap, msg, 1); 626 * 627 * To read or write a block of data (multiple bytes) using SMBUS emulation 628 * please use the i2c_smbus_read_i2c_block_data() 629 * or i2c_smbus_write_i2c_block_data() API 630 */ 631 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 632 struct i2c_msg msgs[], int num_msgs) 633 { 634 int status; 635 int i; 636 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 637 int j; 638 639 dev->busy = true; 640 641 pm_runtime_get_sync(&dev->adev->dev); 642 643 status = clk_prepare_enable(dev->clk); 644 if (status) { 645 dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); 646 goto out_clk; 647 } 648 649 /* Optionaly enable pins to be muxed in and configured */ 650 pinctrl_pm_select_default_state(&dev->adev->dev); 651 652 status = init_hw(dev); 653 if (status) 654 goto out; 655 656 /* Attempt three times to send the message queue */ 657 for (j = 0; j < 3; j++) { 658 /* setup the i2c controller */ 659 setup_i2c_controller(dev); 660 661 for (i = 0; i < num_msgs; i++) { 662 dev->cli.slave_adr = msgs[i].addr; 663 dev->cli.buffer = msgs[i].buf; 664 dev->cli.count = msgs[i].len; 665 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 666 dev->result = 0; 667 668 status = nmk_i2c_xfer_one(dev, msgs[i].flags); 669 if (status != 0) 670 break; 671 } 672 if (status == 0) 673 break; 674 } 675 676 out: 677 clk_disable_unprepare(dev->clk); 678 out_clk: 679 /* Optionally let pins go into idle state */ 680 pinctrl_pm_select_idle_state(&dev->adev->dev); 681 682 pm_runtime_put_sync(&dev->adev->dev); 683 684 dev->busy = false; 685 686 /* return the no. messages processed */ 687 if (status) 688 return status; 689 else 690 return num_msgs; 691 } 692 693 /** 694 * disable_interrupts() - disable the interrupts 695 * @dev: private data of controller 696 * @irq: interrupt number 697 */ 698 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 699 { 700 irq = IRQ_MASK(irq); 701 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 702 dev->virtbase + I2C_IMSCR); 703 return 0; 704 } 705 706 /** 707 * i2c_irq_handler() - interrupt routine 708 * @irq: interrupt number 709 * @arg: data passed to the handler 710 * 711 * This is the interrupt handler for the i2c driver. Currently 712 * it handles the major interrupts like Rx & Tx FIFO management 713 * interrupts, master transaction interrupts, arbitration and 714 * bus error interrupts. The rest of the interrupts are treated as 715 * unhandled. 716 */ 717 static irqreturn_t i2c_irq_handler(int irq, void *arg) 718 { 719 struct nmk_i2c_dev *dev = arg; 720 u32 tft, rft; 721 u32 count; 722 u32 misr, src; 723 724 /* load Tx FIFO and Rx FIFO threshold values */ 725 tft = readl(dev->virtbase + I2C_TFTR); 726 rft = readl(dev->virtbase + I2C_RFTR); 727 728 /* read interrupt status register */ 729 misr = readl(dev->virtbase + I2C_MISR); 730 731 src = __ffs(misr); 732 switch ((1 << src)) { 733 734 /* Transmit FIFO nearly empty interrupt */ 735 case I2C_IT_TXFNE: 736 { 737 if (dev->cli.operation == I2C_READ) { 738 /* 739 * in read operation why do we care for writing? 740 * so disable the Transmit FIFO interrupt 741 */ 742 disable_interrupts(dev, I2C_IT_TXFNE); 743 } else { 744 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); 745 /* 746 * if done, close the transfer by disabling the 747 * corresponding TXFNE interrupt 748 */ 749 if (dev->cli.count == 0) 750 disable_interrupts(dev, I2C_IT_TXFNE); 751 } 752 } 753 break; 754 755 /* 756 * Rx FIFO nearly full interrupt. 757 * This is set when the numer of entries in Rx FIFO is 758 * greater or equal than the threshold value programmed 759 * in RFT 760 */ 761 case I2C_IT_RXFNF: 762 for (count = rft; count > 0; count--) { 763 /* Read the Rx FIFO */ 764 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 765 dev->cli.buffer++; 766 } 767 dev->cli.count -= rft; 768 dev->cli.xfer_bytes += rft; 769 break; 770 771 /* Rx FIFO full */ 772 case I2C_IT_RXFF: 773 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 774 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 775 dev->cli.buffer++; 776 } 777 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 778 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 779 break; 780 781 /* Master Transaction Done with/without stop */ 782 case I2C_IT_MTD: 783 case I2C_IT_MTDWS: 784 if (dev->cli.operation == I2C_READ) { 785 while (!(readl(dev->virtbase + I2C_RISR) 786 & I2C_IT_RXFE)) { 787 if (dev->cli.count == 0) 788 break; 789 *dev->cli.buffer = 790 readb(dev->virtbase + I2C_RFR); 791 dev->cli.buffer++; 792 dev->cli.count--; 793 dev->cli.xfer_bytes++; 794 } 795 } 796 797 disable_all_interrupts(dev); 798 clear_all_interrupts(dev); 799 800 if (dev->cli.count) { 801 dev->result = -EIO; 802 dev_err(&dev->adev->dev, 803 "%lu bytes still remain to be xfered\n", 804 dev->cli.count); 805 (void) init_hw(dev); 806 } 807 complete(&dev->xfer_complete); 808 809 break; 810 811 /* Master Arbitration lost interrupt */ 812 case I2C_IT_MAL: 813 dev->result = -EIO; 814 (void) init_hw(dev); 815 816 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 817 complete(&dev->xfer_complete); 818 819 break; 820 821 /* 822 * Bus Error interrupt. 823 * This happens when an unexpected start/stop condition occurs 824 * during the transaction. 825 */ 826 case I2C_IT_BERR: 827 dev->result = -EIO; 828 /* get the status */ 829 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 830 (void) init_hw(dev); 831 832 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 833 complete(&dev->xfer_complete); 834 835 break; 836 837 /* 838 * Tx FIFO overrun interrupt. 839 * This is set when a write operation in Tx FIFO is performed and 840 * the Tx FIFO is full. 841 */ 842 case I2C_IT_TXFOVR: 843 dev->result = -EIO; 844 (void) init_hw(dev); 845 846 dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); 847 complete(&dev->xfer_complete); 848 849 break; 850 851 /* unhandled interrupts by this driver - TODO*/ 852 case I2C_IT_TXFE: 853 case I2C_IT_TXFF: 854 case I2C_IT_RXFE: 855 case I2C_IT_RFSR: 856 case I2C_IT_RFSE: 857 case I2C_IT_WTSR: 858 case I2C_IT_STD: 859 dev_err(&dev->adev->dev, "unhandled Interrupt\n"); 860 break; 861 default: 862 dev_err(&dev->adev->dev, "spurious Interrupt..\n"); 863 break; 864 } 865 866 return IRQ_HANDLED; 867 } 868 869 870 #ifdef CONFIG_PM 871 static int nmk_i2c_suspend(struct device *dev) 872 { 873 struct amba_device *adev = to_amba_device(dev); 874 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 875 876 if (nmk_i2c->busy) 877 return -EBUSY; 878 879 pinctrl_pm_select_sleep_state(dev); 880 881 return 0; 882 } 883 884 static int nmk_i2c_resume(struct device *dev) 885 { 886 /* First go to the default state */ 887 pinctrl_pm_select_default_state(dev); 888 /* Then let's idle the pins until the next transfer happens */ 889 pinctrl_pm_select_idle_state(dev); 890 891 return 0; 892 } 893 #else 894 #define nmk_i2c_suspend NULL 895 #define nmk_i2c_resume NULL 896 #endif 897 898 /* 899 * We use noirq so that we suspend late and resume before the wakeup interrupt 900 * to ensure that we do the !pm_runtime_suspended() check in resume before 901 * there has been a regular pm runtime resume (via pm_runtime_get_sync()). 902 */ 903 static const struct dev_pm_ops nmk_i2c_pm = { 904 .suspend_noirq = nmk_i2c_suspend, 905 .resume_noirq = nmk_i2c_resume, 906 }; 907 908 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 909 { 910 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 911 } 912 913 static const struct i2c_algorithm nmk_i2c_algo = { 914 .master_xfer = nmk_i2c_xfer, 915 .functionality = nmk_i2c_functionality 916 }; 917 918 static struct nmk_i2c_controller u8500_i2c = { 919 /* 920 * Slave data setup time; 250ns, 100ns, and 10ns, which 921 * is 14, 6 and 2 respectively for a 48Mhz i2c clock. 922 */ 923 .slsu = 0xe, 924 .tft = 1, /* Tx FIFO threshold */ 925 .rft = 8, /* Rx FIFO threshold */ 926 .clk_freq = 400000, /* fast mode operation */ 927 .timeout = 200, /* Slave response timeout(ms) */ 928 .sm = I2C_FREQ_MODE_FAST, 929 }; 930 931 static void nmk_i2c_of_probe(struct device_node *np, 932 struct nmk_i2c_controller *pdata) 933 { 934 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); 935 936 /* This driver only supports 'standard' and 'fast' modes of operation. */ 937 if (pdata->clk_freq <= 100000) 938 pdata->sm = I2C_FREQ_MODE_STANDARD; 939 else 940 pdata->sm = I2C_FREQ_MODE_FAST; 941 } 942 943 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 944 { 945 int ret = 0; 946 struct nmk_i2c_controller *pdata = adev->dev.platform_data; 947 struct device_node *np = adev->dev.of_node; 948 struct nmk_i2c_dev *dev; 949 struct i2c_adapter *adap; 950 struct i2c_vendor_data *vendor = id->data; 951 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; 952 953 if (!pdata) { 954 if (np) { 955 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); 956 if (!pdata) { 957 ret = -ENOMEM; 958 goto err_no_mem; 959 } 960 /* Provide the default configuration as a base. */ 961 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); 962 nmk_i2c_of_probe(np, pdata); 963 } else 964 /* No i2c configuration found, using the default. */ 965 pdata = &u8500_i2c; 966 } 967 968 if (pdata->tft > max_fifo_threshold) { 969 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", 970 pdata->tft, max_fifo_threshold); 971 pdata->tft = max_fifo_threshold; 972 } 973 974 if (pdata->rft > max_fifo_threshold) { 975 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", 976 pdata->rft, max_fifo_threshold); 977 pdata->rft = max_fifo_threshold; 978 } 979 980 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 981 if (!dev) { 982 dev_err(&adev->dev, "cannot allocate memory\n"); 983 ret = -ENOMEM; 984 goto err_no_mem; 985 } 986 dev->vendor = vendor; 987 dev->busy = false; 988 dev->adev = adev; 989 amba_set_drvdata(adev, dev); 990 991 /* Select default pin state */ 992 pinctrl_pm_select_default_state(&adev->dev); 993 /* If possible, let's go to idle until the first transfer */ 994 pinctrl_pm_select_idle_state(&adev->dev); 995 996 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 997 if (!dev->virtbase) { 998 ret = -ENOMEM; 999 goto err_no_ioremap; 1000 } 1001 1002 dev->irq = adev->irq[0]; 1003 ret = request_irq(dev->irq, i2c_irq_handler, 0, 1004 DRIVER_NAME, dev); 1005 if (ret) { 1006 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); 1007 goto err_irq; 1008 } 1009 1010 pm_suspend_ignore_children(&adev->dev, true); 1011 1012 dev->clk = clk_get(&adev->dev, NULL); 1013 if (IS_ERR(dev->clk)) { 1014 dev_err(&adev->dev, "could not get i2c clock\n"); 1015 ret = PTR_ERR(dev->clk); 1016 goto err_no_clk; 1017 } 1018 1019 adap = &dev->adap; 1020 adap->dev.of_node = np; 1021 adap->dev.parent = &adev->dev; 1022 adap->owner = THIS_MODULE; 1023 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1024 adap->algo = &nmk_i2c_algo; 1025 adap->timeout = msecs_to_jiffies(pdata->timeout); 1026 snprintf(adap->name, sizeof(adap->name), 1027 "Nomadik I2C at %pR", &adev->res); 1028 1029 /* fetch the controller configuration from machine */ 1030 dev->cfg.clk_freq = pdata->clk_freq; 1031 dev->cfg.slsu = pdata->slsu; 1032 dev->cfg.tft = pdata->tft; 1033 dev->cfg.rft = pdata->rft; 1034 dev->cfg.sm = pdata->sm; 1035 1036 i2c_set_adapdata(adap, dev); 1037 1038 dev_info(&adev->dev, 1039 "initialize %s on virtual base %p\n", 1040 adap->name, dev->virtbase); 1041 1042 ret = i2c_add_adapter(adap); 1043 if (ret) { 1044 dev_err(&adev->dev, "failed to add adapter\n"); 1045 goto err_add_adap; 1046 } 1047 1048 of_i2c_register_devices(adap); 1049 1050 pm_runtime_put(&adev->dev); 1051 1052 return 0; 1053 1054 err_add_adap: 1055 clk_put(dev->clk); 1056 err_no_clk: 1057 free_irq(dev->irq, dev); 1058 err_irq: 1059 iounmap(dev->virtbase); 1060 err_no_ioremap: 1061 kfree(dev); 1062 err_no_mem: 1063 1064 return ret; 1065 } 1066 1067 static int nmk_i2c_remove(struct amba_device *adev) 1068 { 1069 struct resource *res = &adev->res; 1070 struct nmk_i2c_dev *dev = amba_get_drvdata(adev); 1071 1072 i2c_del_adapter(&dev->adap); 1073 flush_i2c_fifo(dev); 1074 disable_all_interrupts(dev); 1075 clear_all_interrupts(dev); 1076 /* disable the controller */ 1077 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1078 free_irq(dev->irq, dev); 1079 iounmap(dev->virtbase); 1080 if (res) 1081 release_mem_region(res->start, resource_size(res)); 1082 clk_put(dev->clk); 1083 pm_runtime_disable(&adev->dev); 1084 kfree(dev); 1085 1086 return 0; 1087 } 1088 1089 static struct i2c_vendor_data vendor_stn8815 = { 1090 .has_mtdws = false, 1091 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ 1092 }; 1093 1094 static struct i2c_vendor_data vendor_db8500 = { 1095 .has_mtdws = true, 1096 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ 1097 }; 1098 1099 static struct amba_id nmk_i2c_ids[] = { 1100 { 1101 .id = 0x00180024, 1102 .mask = 0x00ffffff, 1103 .data = &vendor_stn8815, 1104 }, 1105 { 1106 .id = 0x00380024, 1107 .mask = 0x00ffffff, 1108 .data = &vendor_db8500, 1109 }, 1110 {}, 1111 }; 1112 1113 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1114 1115 static struct amba_driver nmk_i2c_driver = { 1116 .drv = { 1117 .owner = THIS_MODULE, 1118 .name = DRIVER_NAME, 1119 .pm = &nmk_i2c_pm, 1120 }, 1121 .id_table = nmk_i2c_ids, 1122 .probe = nmk_i2c_probe, 1123 .remove = nmk_i2c_remove, 1124 }; 1125 1126 static int __init nmk_i2c_init(void) 1127 { 1128 return amba_driver_register(&nmk_i2c_driver); 1129 } 1130 1131 static void __exit nmk_i2c_exit(void) 1132 { 1133 amba_driver_unregister(&nmk_i2c_driver); 1134 } 1135 1136 subsys_initcall(nmk_i2c_init); 1137 module_exit(nmk_i2c_exit); 1138 1139 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 1140 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1141 MODULE_LICENSE("GPL"); 1142