1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/amba/bus.h> 18 #include <linux/atomic.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/i2c.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/platform_data/i2c-nomadik.h> 27 #include <linux/of.h> 28 #include <linux/of_i2c.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "nmk-i2c" 32 33 /* I2C Controller register offsets */ 34 #define I2C_CR (0x000) 35 #define I2C_SCR (0x004) 36 #define I2C_HSMCR (0x008) 37 #define I2C_MCR (0x00C) 38 #define I2C_TFR (0x010) 39 #define I2C_SR (0x014) 40 #define I2C_RFR (0x018) 41 #define I2C_TFTR (0x01C) 42 #define I2C_RFTR (0x020) 43 #define I2C_DMAR (0x024) 44 #define I2C_BRCR (0x028) 45 #define I2C_IMSCR (0x02C) 46 #define I2C_RISR (0x030) 47 #define I2C_MISR (0x034) 48 #define I2C_ICR (0x038) 49 50 /* Control registers */ 51 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 52 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 53 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 54 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 55 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 56 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 57 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 58 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 59 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 60 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 61 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 62 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 63 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 64 65 /* Master controller (MCR) register */ 66 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 67 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 68 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 69 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 70 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 71 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 72 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 73 74 /* Status register (SR) */ 75 #define I2C_SR_OP (0x3 << 0) /* Operation */ 76 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 77 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 78 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 79 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 80 81 /* Interrupt mask set/clear (IMSCR) bits */ 82 #define I2C_IT_TXFE (0x1 << 0) 83 #define I2C_IT_TXFNE (0x1 << 1) 84 #define I2C_IT_TXFF (0x1 << 2) 85 #define I2C_IT_TXFOVR (0x1 << 3) 86 #define I2C_IT_RXFE (0x1 << 4) 87 #define I2C_IT_RXFNF (0x1 << 5) 88 #define I2C_IT_RXFF (0x1 << 6) 89 #define I2C_IT_RFSR (0x1 << 16) 90 #define I2C_IT_RFSE (0x1 << 17) 91 #define I2C_IT_WTSR (0x1 << 18) 92 #define I2C_IT_MTD (0x1 << 19) 93 #define I2C_IT_STD (0x1 << 20) 94 #define I2C_IT_MAL (0x1 << 24) 95 #define I2C_IT_BERR (0x1 << 25) 96 #define I2C_IT_MTDWS (0x1 << 28) 97 98 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 99 100 /* some bits in ICR are reserved */ 101 #define I2C_CLEAR_ALL_INTS 0x131f007f 102 103 /* first three msb bits are reserved */ 104 #define IRQ_MASK(mask) (mask & 0x1fffffff) 105 106 /* maximum threshold value */ 107 #define MAX_I2C_FIFO_THRESHOLD 15 108 109 enum i2c_status { 110 I2C_NOP, 111 I2C_ON_GOING, 112 I2C_OK, 113 I2C_ABORT 114 }; 115 116 /* operation */ 117 enum i2c_operation { 118 I2C_NO_OPERATION = 0xff, 119 I2C_WRITE = 0x00, 120 I2C_READ = 0x01 121 }; 122 123 /** 124 * struct i2c_nmk_client - client specific data 125 * @slave_adr: 7-bit slave address 126 * @count: no. bytes to be transferred 127 * @buffer: client data buffer 128 * @xfer_bytes: bytes transferred till now 129 * @operation: current I2C operation 130 */ 131 struct i2c_nmk_client { 132 unsigned short slave_adr; 133 unsigned long count; 134 unsigned char *buffer; 135 unsigned long xfer_bytes; 136 enum i2c_operation operation; 137 }; 138 139 /** 140 * struct nmk_i2c_dev - private data structure of the controller. 141 * @adev: parent amba device. 142 * @adap: corresponding I2C adapter. 143 * @irq: interrupt line for the controller. 144 * @virtbase: virtual io memory area. 145 * @clk: hardware i2c block clock. 146 * @cfg: machine provided controller configuration. 147 * @cli: holder of client specific data. 148 * @stop: stop condition. 149 * @xfer_complete: acknowledge completion for a I2C message. 150 * @result: controller propogated result. 151 * @pinctrl: pinctrl handle. 152 * @pins_default: default state for the pins. 153 * @pins_idle: idle state for the pins. 154 * @pins_sleep: sleep state for the pins. 155 * @busy: Busy doing transfer. 156 */ 157 struct nmk_i2c_dev { 158 struct amba_device *adev; 159 struct i2c_adapter adap; 160 int irq; 161 void __iomem *virtbase; 162 struct clk *clk; 163 struct nmk_i2c_controller cfg; 164 struct i2c_nmk_client cli; 165 int stop; 166 struct completion xfer_complete; 167 int result; 168 /* Three pin states - default, idle & sleep */ 169 struct pinctrl *pinctrl; 170 struct pinctrl_state *pins_default; 171 struct pinctrl_state *pins_idle; 172 struct pinctrl_state *pins_sleep; 173 bool busy; 174 }; 175 176 /* controller's abort causes */ 177 static const char *abort_causes[] = { 178 "no ack received after address transmission", 179 "no ack received during data phase", 180 "ack received after xmission of master code", 181 "master lost arbitration", 182 "slave restarts", 183 "slave reset", 184 "overflow, maxsize is 2047 bytes", 185 }; 186 187 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 188 { 189 writel(readl(reg) | mask, reg); 190 } 191 192 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 193 { 194 writel(readl(reg) & ~mask, reg); 195 } 196 197 /** 198 * flush_i2c_fifo() - This function flushes the I2C FIFO 199 * @dev: private data of I2C Driver 200 * 201 * This function flushes the I2C Tx and Rx FIFOs. It returns 202 * 0 on successful flushing of FIFO 203 */ 204 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 205 { 206 #define LOOP_ATTEMPTS 10 207 int i; 208 unsigned long timeout; 209 210 /* 211 * flush the transmit and receive FIFO. The flushing 212 * operation takes several cycles before to be completed. 213 * On the completion, the I2C internal logic clears these 214 * bits, until then no one must access Tx, Rx FIFO and 215 * should poll on these bits waiting for the completion. 216 */ 217 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 218 219 for (i = 0; i < LOOP_ATTEMPTS; i++) { 220 timeout = jiffies + dev->adap.timeout; 221 222 while (!time_after(jiffies, timeout)) { 223 if ((readl(dev->virtbase + I2C_CR) & 224 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 225 return 0; 226 } 227 } 228 229 dev_err(&dev->adev->dev, 230 "flushing operation timed out giving up after %d attempts", 231 LOOP_ATTEMPTS); 232 233 return -ETIMEDOUT; 234 } 235 236 /** 237 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 238 * @dev: private data of I2C Driver 239 */ 240 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 241 { 242 u32 mask = IRQ_MASK(0); 243 writel(mask, dev->virtbase + I2C_IMSCR); 244 } 245 246 /** 247 * clear_all_interrupts() - Clear all interrupts of I2C Controller 248 * @dev: private data of I2C Driver 249 */ 250 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 251 { 252 u32 mask; 253 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 254 writel(mask, dev->virtbase + I2C_ICR); 255 } 256 257 /** 258 * init_hw() - initialize the I2C hardware 259 * @dev: private data of I2C Driver 260 */ 261 static int init_hw(struct nmk_i2c_dev *dev) 262 { 263 int stat; 264 265 stat = flush_i2c_fifo(dev); 266 if (stat) 267 goto exit; 268 269 /* disable the controller */ 270 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 271 272 disable_all_interrupts(dev); 273 274 clear_all_interrupts(dev); 275 276 dev->cli.operation = I2C_NO_OPERATION; 277 278 exit: 279 return stat; 280 } 281 282 /* enable peripheral, master mode operation */ 283 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 284 285 /** 286 * load_i2c_mcr_reg() - load the MCR register 287 * @dev: private data of controller 288 * @flags: message flags 289 */ 290 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) 291 { 292 u32 mcr = 0; 293 unsigned short slave_adr_3msb_bits; 294 295 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 296 297 if (unlikely(flags & I2C_M_TEN)) { 298 /* 10-bit address transaction */ 299 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); 300 /* 301 * Get the top 3 bits. 302 * EA10 represents extended address in MCR. This includes 303 * the extension (MSB bits) of the 7 bit address loaded 304 * in A7 305 */ 306 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; 307 308 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); 309 } else { 310 /* 7-bit address transaction */ 311 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 312 } 313 314 /* start byte procedure not applied */ 315 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 316 317 /* check the operation, master read/write? */ 318 if (dev->cli.operation == I2C_WRITE) 319 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 320 else 321 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 322 323 /* stop or repeated start? */ 324 if (dev->stop) 325 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 326 else 327 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 328 329 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 330 331 return mcr; 332 } 333 334 /** 335 * setup_i2c_controller() - setup the controller 336 * @dev: private data of controller 337 */ 338 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 339 { 340 u32 brcr1, brcr2; 341 u32 i2c_clk, div; 342 343 writel(0x0, dev->virtbase + I2C_CR); 344 writel(0x0, dev->virtbase + I2C_HSMCR); 345 writel(0x0, dev->virtbase + I2C_TFTR); 346 writel(0x0, dev->virtbase + I2C_RFTR); 347 writel(0x0, dev->virtbase + I2C_DMAR); 348 349 /* 350 * set the slsu: 351 * 352 * slsu defines the data setup time after SCL clock 353 * stretching in terms of i2c clk cycles. The 354 * needed setup time for the three modes are 250ns, 355 * 100ns, 10ns respectively thus leading to the values 356 * of 14, 6, 2 for a 48 MHz i2c clk. 357 */ 358 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); 359 360 i2c_clk = clk_get_rate(dev->clk); 361 362 /* 363 * The spec says, in case of std. mode the divider is 364 * 2 whereas it is 3 for fast and fastplus mode of 365 * operation. TODO - high speed support. 366 */ 367 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 368 369 /* 370 * generate the mask for baud rate counters. The controller 371 * has two baud rate counters. One is used for High speed 372 * operation, and the other is for std, fast mode, fast mode 373 * plus operation. Currently we do not supprt high speed mode 374 * so set brcr1 to 0. 375 */ 376 brcr1 = 0 << 16; 377 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 378 379 /* set the baud rate counter register */ 380 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 381 382 /* 383 * set the speed mode. Currently we support 384 * only standard and fast mode of operation 385 * TODO - support for fast mode plus (up to 1Mb/s) 386 * and high speed (up to 3.4 Mb/s) 387 */ 388 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 389 dev_err(&dev->adev->dev, 390 "do not support this mode defaulting to std. mode\n"); 391 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 392 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 393 writel(I2C_FREQ_MODE_STANDARD << 4, 394 dev->virtbase + I2C_CR); 395 } 396 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 397 398 /* set the Tx and Rx FIFO threshold */ 399 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 400 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 401 } 402 403 /** 404 * read_i2c() - Read from I2C client device 405 * @dev: private data of I2C Driver 406 * @flags: message flags 407 * 408 * This function reads from i2c client device when controller is in 409 * master mode. There is a completion timeout. If there is no transfer 410 * before timeout error is returned. 411 */ 412 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 413 { 414 u32 status = 0; 415 u32 mcr, irq_mask; 416 int timeout; 417 418 mcr = load_i2c_mcr_reg(dev, flags); 419 writel(mcr, dev->virtbase + I2C_MCR); 420 421 /* load the current CR value */ 422 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 423 dev->virtbase + I2C_CR); 424 425 /* enable the controller */ 426 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 427 428 init_completion(&dev->xfer_complete); 429 430 /* enable interrupts by setting the mask */ 431 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 432 I2C_IT_MAL | I2C_IT_BERR); 433 434 if (dev->stop) 435 irq_mask |= I2C_IT_MTD; 436 else 437 irq_mask |= I2C_IT_MTDWS; 438 439 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 440 441 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 442 dev->virtbase + I2C_IMSCR); 443 444 timeout = wait_for_completion_timeout( 445 &dev->xfer_complete, dev->adap.timeout); 446 447 if (timeout == 0) { 448 /* Controller timed out */ 449 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 450 dev->cli.slave_adr); 451 status = -ETIMEDOUT; 452 } 453 return status; 454 } 455 456 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) 457 { 458 int count; 459 460 for (count = (no_bytes - 2); 461 (count > 0) && 462 (dev->cli.count != 0); 463 count--) { 464 /* write to the Tx FIFO */ 465 writeb(*dev->cli.buffer, 466 dev->virtbase + I2C_TFR); 467 dev->cli.buffer++; 468 dev->cli.count--; 469 dev->cli.xfer_bytes++; 470 } 471 472 } 473 474 /** 475 * write_i2c() - Write data to I2C client. 476 * @dev: private data of I2C Driver 477 * @flags: message flags 478 * 479 * This function writes data to I2C client 480 */ 481 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) 482 { 483 u32 status = 0; 484 u32 mcr, irq_mask; 485 int timeout; 486 487 mcr = load_i2c_mcr_reg(dev, flags); 488 489 writel(mcr, dev->virtbase + I2C_MCR); 490 491 /* load the current CR value */ 492 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 493 dev->virtbase + I2C_CR); 494 495 /* enable the controller */ 496 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 497 498 init_completion(&dev->xfer_complete); 499 500 /* enable interrupts by settings the masks */ 501 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 502 503 /* Fill the TX FIFO with transmit data */ 504 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); 505 506 if (dev->cli.count != 0) 507 irq_mask |= I2C_IT_TXFNE; 508 509 /* 510 * check if we want to transfer a single or multiple bytes, if so 511 * set the MTDWS bit (Master Transaction Done Without Stop) 512 * to start repeated start operation 513 */ 514 if (dev->stop) 515 irq_mask |= I2C_IT_MTD; 516 else 517 irq_mask |= I2C_IT_MTDWS; 518 519 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 520 521 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 522 dev->virtbase + I2C_IMSCR); 523 524 timeout = wait_for_completion_timeout( 525 &dev->xfer_complete, dev->adap.timeout); 526 527 if (timeout == 0) { 528 /* Controller timed out */ 529 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 530 dev->cli.slave_adr); 531 status = -ETIMEDOUT; 532 } 533 534 return status; 535 } 536 537 /** 538 * nmk_i2c_xfer_one() - transmit a single I2C message 539 * @dev: device with a message encoded into it 540 * @flags: message flags 541 */ 542 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) 543 { 544 int status; 545 546 if (flags & I2C_M_RD) { 547 /* read operation */ 548 dev->cli.operation = I2C_READ; 549 status = read_i2c(dev, flags); 550 } else { 551 /* write operation */ 552 dev->cli.operation = I2C_WRITE; 553 status = write_i2c(dev, flags); 554 } 555 556 if (status || (dev->result)) { 557 u32 i2c_sr; 558 u32 cause; 559 560 i2c_sr = readl(dev->virtbase + I2C_SR); 561 /* 562 * Check if the controller I2C operation status 563 * is set to ABORT(11b). 564 */ 565 if (((i2c_sr >> 2) & 0x3) == 0x3) { 566 /* get the abort cause */ 567 cause = (i2c_sr >> 4) & 0x7; 568 dev_err(&dev->adev->dev, "%s\n", 569 cause >= ARRAY_SIZE(abort_causes) ? 570 "unknown reason" : 571 abort_causes[cause]); 572 } 573 574 (void) init_hw(dev); 575 576 status = status ? status : dev->result; 577 } 578 579 return status; 580 } 581 582 /** 583 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 584 * @i2c_adap: Adapter pointer to the controller 585 * @msgs: Pointer to data to be written. 586 * @num_msgs: Number of messages to be executed 587 * 588 * This is the function called by the generic kernel i2c_transfer() 589 * or i2c_smbus...() API calls. Note that this code is protected by the 590 * semaphore set in the kernel i2c_transfer() function. 591 * 592 * NOTE: 593 * READ TRANSFER : We impose a restriction of the first message to be the 594 * index message for any read transaction. 595 * - a no index is coded as '0', 596 * - 2byte big endian index is coded as '3' 597 * !!! msg[0].buf holds the actual index. 598 * This is compatible with generic messages of smbus emulator 599 * that send a one byte index. 600 * eg. a I2C transation to read 2 bytes from index 0 601 * idx = 0; 602 * msg[0].addr = client->addr; 603 * msg[0].flags = 0x0; 604 * msg[0].len = 1; 605 * msg[0].buf = &idx; 606 * 607 * msg[1].addr = client->addr; 608 * msg[1].flags = I2C_M_RD; 609 * msg[1].len = 2; 610 * msg[1].buf = rd_buff 611 * i2c_transfer(adap, msg, 2); 612 * 613 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 614 * If you want to emulate an SMBUS write transaction put the 615 * index as first byte(or first and second) in the payload. 616 * eg. a I2C transation to write 2 bytes from index 1 617 * wr_buff[0] = 0x1; 618 * wr_buff[1] = 0x23; 619 * wr_buff[2] = 0x46; 620 * msg[0].flags = 0x0; 621 * msg[0].len = 3; 622 * msg[0].buf = wr_buff; 623 * i2c_transfer(adap, msg, 1); 624 * 625 * To read or write a block of data (multiple bytes) using SMBUS emulation 626 * please use the i2c_smbus_read_i2c_block_data() 627 * or i2c_smbus_write_i2c_block_data() API 628 */ 629 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 630 struct i2c_msg msgs[], int num_msgs) 631 { 632 int status; 633 int i; 634 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 635 int j; 636 637 dev->busy = true; 638 639 pm_runtime_get_sync(&dev->adev->dev); 640 641 status = clk_prepare_enable(dev->clk); 642 if (status) { 643 dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); 644 goto out_clk; 645 } 646 647 /* Optionaly enable pins to be muxed in and configured */ 648 if (!IS_ERR(dev->pins_default)) { 649 status = pinctrl_select_state(dev->pinctrl, 650 dev->pins_default); 651 if (status) 652 dev_err(&dev->adev->dev, 653 "could not set default pins\n"); 654 } 655 656 status = init_hw(dev); 657 if (status) 658 goto out; 659 660 /* Attempt three times to send the message queue */ 661 for (j = 0; j < 3; j++) { 662 /* setup the i2c controller */ 663 setup_i2c_controller(dev); 664 665 for (i = 0; i < num_msgs; i++) { 666 dev->cli.slave_adr = msgs[i].addr; 667 dev->cli.buffer = msgs[i].buf; 668 dev->cli.count = msgs[i].len; 669 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 670 dev->result = 0; 671 672 status = nmk_i2c_xfer_one(dev, msgs[i].flags); 673 if (status != 0) 674 break; 675 } 676 if (status == 0) 677 break; 678 } 679 680 out: 681 clk_disable_unprepare(dev->clk); 682 out_clk: 683 /* Optionally let pins go into idle state */ 684 if (!IS_ERR(dev->pins_idle)) { 685 status = pinctrl_select_state(dev->pinctrl, 686 dev->pins_idle); 687 if (status) 688 dev_err(&dev->adev->dev, 689 "could not set pins to idle state\n"); 690 } 691 692 pm_runtime_put_sync(&dev->adev->dev); 693 694 dev->busy = false; 695 696 /* return the no. messages processed */ 697 if (status) 698 return status; 699 else 700 return num_msgs; 701 } 702 703 /** 704 * disable_interrupts() - disable the interrupts 705 * @dev: private data of controller 706 * @irq: interrupt number 707 */ 708 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 709 { 710 irq = IRQ_MASK(irq); 711 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 712 dev->virtbase + I2C_IMSCR); 713 return 0; 714 } 715 716 /** 717 * i2c_irq_handler() - interrupt routine 718 * @irq: interrupt number 719 * @arg: data passed to the handler 720 * 721 * This is the interrupt handler for the i2c driver. Currently 722 * it handles the major interrupts like Rx & Tx FIFO management 723 * interrupts, master transaction interrupts, arbitration and 724 * bus error interrupts. The rest of the interrupts are treated as 725 * unhandled. 726 */ 727 static irqreturn_t i2c_irq_handler(int irq, void *arg) 728 { 729 struct nmk_i2c_dev *dev = arg; 730 u32 tft, rft; 731 u32 count; 732 u32 misr, src; 733 734 /* load Tx FIFO and Rx FIFO threshold values */ 735 tft = readl(dev->virtbase + I2C_TFTR); 736 rft = readl(dev->virtbase + I2C_RFTR); 737 738 /* read interrupt status register */ 739 misr = readl(dev->virtbase + I2C_MISR); 740 741 src = __ffs(misr); 742 switch ((1 << src)) { 743 744 /* Transmit FIFO nearly empty interrupt */ 745 case I2C_IT_TXFNE: 746 { 747 if (dev->cli.operation == I2C_READ) { 748 /* 749 * in read operation why do we care for writing? 750 * so disable the Transmit FIFO interrupt 751 */ 752 disable_interrupts(dev, I2C_IT_TXFNE); 753 } else { 754 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); 755 /* 756 * if done, close the transfer by disabling the 757 * corresponding TXFNE interrupt 758 */ 759 if (dev->cli.count == 0) 760 disable_interrupts(dev, I2C_IT_TXFNE); 761 } 762 } 763 break; 764 765 /* 766 * Rx FIFO nearly full interrupt. 767 * This is set when the numer of entries in Rx FIFO is 768 * greater or equal than the threshold value programmed 769 * in RFT 770 */ 771 case I2C_IT_RXFNF: 772 for (count = rft; count > 0; count--) { 773 /* Read the Rx FIFO */ 774 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 775 dev->cli.buffer++; 776 } 777 dev->cli.count -= rft; 778 dev->cli.xfer_bytes += rft; 779 break; 780 781 /* Rx FIFO full */ 782 case I2C_IT_RXFF: 783 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 784 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 785 dev->cli.buffer++; 786 } 787 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 788 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 789 break; 790 791 /* Master Transaction Done with/without stop */ 792 case I2C_IT_MTD: 793 case I2C_IT_MTDWS: 794 if (dev->cli.operation == I2C_READ) { 795 while (!(readl(dev->virtbase + I2C_RISR) 796 & I2C_IT_RXFE)) { 797 if (dev->cli.count == 0) 798 break; 799 *dev->cli.buffer = 800 readb(dev->virtbase + I2C_RFR); 801 dev->cli.buffer++; 802 dev->cli.count--; 803 dev->cli.xfer_bytes++; 804 } 805 } 806 807 disable_all_interrupts(dev); 808 clear_all_interrupts(dev); 809 810 if (dev->cli.count) { 811 dev->result = -EIO; 812 dev_err(&dev->adev->dev, 813 "%lu bytes still remain to be xfered\n", 814 dev->cli.count); 815 (void) init_hw(dev); 816 } 817 complete(&dev->xfer_complete); 818 819 break; 820 821 /* Master Arbitration lost interrupt */ 822 case I2C_IT_MAL: 823 dev->result = -EIO; 824 (void) init_hw(dev); 825 826 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 827 complete(&dev->xfer_complete); 828 829 break; 830 831 /* 832 * Bus Error interrupt. 833 * This happens when an unexpected start/stop condition occurs 834 * during the transaction. 835 */ 836 case I2C_IT_BERR: 837 dev->result = -EIO; 838 /* get the status */ 839 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 840 (void) init_hw(dev); 841 842 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 843 complete(&dev->xfer_complete); 844 845 break; 846 847 /* 848 * Tx FIFO overrun interrupt. 849 * This is set when a write operation in Tx FIFO is performed and 850 * the Tx FIFO is full. 851 */ 852 case I2C_IT_TXFOVR: 853 dev->result = -EIO; 854 (void) init_hw(dev); 855 856 dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); 857 complete(&dev->xfer_complete); 858 859 break; 860 861 /* unhandled interrupts by this driver - TODO*/ 862 case I2C_IT_TXFE: 863 case I2C_IT_TXFF: 864 case I2C_IT_RXFE: 865 case I2C_IT_RFSR: 866 case I2C_IT_RFSE: 867 case I2C_IT_WTSR: 868 case I2C_IT_STD: 869 dev_err(&dev->adev->dev, "unhandled Interrupt\n"); 870 break; 871 default: 872 dev_err(&dev->adev->dev, "spurious Interrupt..\n"); 873 break; 874 } 875 876 return IRQ_HANDLED; 877 } 878 879 880 #ifdef CONFIG_PM 881 static int nmk_i2c_suspend(struct device *dev) 882 { 883 struct amba_device *adev = to_amba_device(dev); 884 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 885 int ret; 886 887 if (nmk_i2c->busy) 888 return -EBUSY; 889 890 if (!IS_ERR(nmk_i2c->pins_sleep)) { 891 ret = pinctrl_select_state(nmk_i2c->pinctrl, 892 nmk_i2c->pins_sleep); 893 if (ret) 894 dev_err(dev, "could not set pins to sleep state\n"); 895 } 896 897 return 0; 898 } 899 900 static int nmk_i2c_resume(struct device *dev) 901 { 902 struct amba_device *adev = to_amba_device(dev); 903 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 904 int ret; 905 906 /* First go to the default state */ 907 if (!IS_ERR(nmk_i2c->pins_default)) { 908 ret = pinctrl_select_state(nmk_i2c->pinctrl, 909 nmk_i2c->pins_default); 910 if (ret) 911 dev_err(dev, "could not set pins to default state\n"); 912 } 913 /* Then let's idle the pins until the next transfer happens */ 914 if (!IS_ERR(nmk_i2c->pins_idle)) { 915 ret = pinctrl_select_state(nmk_i2c->pinctrl, 916 nmk_i2c->pins_idle); 917 if (ret) 918 dev_err(dev, "could not set pins to idle state\n"); 919 } 920 return 0; 921 } 922 #else 923 #define nmk_i2c_suspend NULL 924 #define nmk_i2c_resume NULL 925 #endif 926 927 /* 928 * We use noirq so that we suspend late and resume before the wakeup interrupt 929 * to ensure that we do the !pm_runtime_suspended() check in resume before 930 * there has been a regular pm runtime resume (via pm_runtime_get_sync()). 931 */ 932 static const struct dev_pm_ops nmk_i2c_pm = { 933 .suspend_noirq = nmk_i2c_suspend, 934 .resume_noirq = nmk_i2c_resume, 935 }; 936 937 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 938 { 939 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 940 } 941 942 static const struct i2c_algorithm nmk_i2c_algo = { 943 .master_xfer = nmk_i2c_xfer, 944 .functionality = nmk_i2c_functionality 945 }; 946 947 static struct nmk_i2c_controller u8500_i2c = { 948 /* 949 * Slave data setup time; 250ns, 100ns, and 10ns, which 950 * is 14, 6 and 2 respectively for a 48Mhz i2c clock. 951 */ 952 .slsu = 0xe, 953 .tft = 1, /* Tx FIFO threshold */ 954 .rft = 8, /* Rx FIFO threshold */ 955 .clk_freq = 400000, /* fast mode operation */ 956 .timeout = 200, /* Slave response timeout(ms) */ 957 .sm = I2C_FREQ_MODE_FAST, 958 }; 959 960 static void nmk_i2c_of_probe(struct device_node *np, 961 struct nmk_i2c_controller *pdata) 962 { 963 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); 964 965 /* This driver only supports 'standard' and 'fast' modes of operation. */ 966 if (pdata->clk_freq <= 100000) 967 pdata->sm = I2C_FREQ_MODE_STANDARD; 968 else 969 pdata->sm = I2C_FREQ_MODE_FAST; 970 } 971 972 static atomic_t adapter_id = ATOMIC_INIT(0); 973 974 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 975 { 976 int ret = 0; 977 struct nmk_i2c_controller *pdata = adev->dev.platform_data; 978 struct device_node *np = adev->dev.of_node; 979 struct nmk_i2c_dev *dev; 980 struct i2c_adapter *adap; 981 982 if (!pdata) { 983 if (np) { 984 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); 985 if (!pdata) { 986 ret = -ENOMEM; 987 goto err_no_mem; 988 } 989 /* Provide the default configuration as a base. */ 990 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); 991 nmk_i2c_of_probe(np, pdata); 992 } else 993 /* No i2c configuration found, using the default. */ 994 pdata = &u8500_i2c; 995 } 996 997 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 998 if (!dev) { 999 dev_err(&adev->dev, "cannot allocate memory\n"); 1000 ret = -ENOMEM; 1001 goto err_no_mem; 1002 } 1003 dev->busy = false; 1004 dev->adev = adev; 1005 amba_set_drvdata(adev, dev); 1006 1007 dev->pinctrl = devm_pinctrl_get(&adev->dev); 1008 if (IS_ERR(dev->pinctrl)) { 1009 ret = PTR_ERR(dev->pinctrl); 1010 goto err_pinctrl; 1011 } 1012 1013 dev->pins_default = pinctrl_lookup_state(dev->pinctrl, 1014 PINCTRL_STATE_DEFAULT); 1015 if (IS_ERR(dev->pins_default)) { 1016 dev_err(&adev->dev, "could not get default pinstate\n"); 1017 } else { 1018 ret = pinctrl_select_state(dev->pinctrl, 1019 dev->pins_default); 1020 if (ret) 1021 dev_dbg(&adev->dev, "could not set default pinstate\n"); 1022 } 1023 1024 dev->pins_idle = pinctrl_lookup_state(dev->pinctrl, 1025 PINCTRL_STATE_IDLE); 1026 if (IS_ERR(dev->pins_idle)) { 1027 dev_dbg(&adev->dev, "could not get idle pinstate\n"); 1028 } else { 1029 /* If possible, let's go to idle until the first transfer */ 1030 ret = pinctrl_select_state(dev->pinctrl, 1031 dev->pins_idle); 1032 if (ret) 1033 dev_dbg(&adev->dev, "could not set idle pinstate\n"); 1034 } 1035 1036 dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl, 1037 PINCTRL_STATE_SLEEP); 1038 if (IS_ERR(dev->pins_sleep)) 1039 dev_dbg(&adev->dev, "could not get sleep pinstate\n"); 1040 1041 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 1042 if (!dev->virtbase) { 1043 ret = -ENOMEM; 1044 goto err_no_ioremap; 1045 } 1046 1047 dev->irq = adev->irq[0]; 1048 ret = request_irq(dev->irq, i2c_irq_handler, 0, 1049 DRIVER_NAME, dev); 1050 if (ret) { 1051 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); 1052 goto err_irq; 1053 } 1054 1055 pm_suspend_ignore_children(&adev->dev, true); 1056 1057 dev->clk = clk_get(&adev->dev, NULL); 1058 if (IS_ERR(dev->clk)) { 1059 dev_err(&adev->dev, "could not get i2c clock\n"); 1060 ret = PTR_ERR(dev->clk); 1061 goto err_no_clk; 1062 } 1063 1064 adap = &dev->adap; 1065 adap->dev.of_node = np; 1066 adap->dev.parent = &adev->dev; 1067 adap->owner = THIS_MODULE; 1068 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1069 adap->algo = &nmk_i2c_algo; 1070 adap->timeout = msecs_to_jiffies(pdata->timeout); 1071 adap->nr = atomic_read(&adapter_id); 1072 snprintf(adap->name, sizeof(adap->name), 1073 "Nomadik I2C%d at %pR", adap->nr, &adev->res); 1074 atomic_inc(&adapter_id); 1075 1076 /* fetch the controller configuration from machine */ 1077 dev->cfg.clk_freq = pdata->clk_freq; 1078 dev->cfg.slsu = pdata->slsu; 1079 dev->cfg.tft = pdata->tft; 1080 dev->cfg.rft = pdata->rft; 1081 dev->cfg.sm = pdata->sm; 1082 1083 i2c_set_adapdata(adap, dev); 1084 1085 dev_info(&adev->dev, 1086 "initialize %s on virtual base %p\n", 1087 adap->name, dev->virtbase); 1088 1089 ret = i2c_add_numbered_adapter(adap); 1090 if (ret) { 1091 dev_err(&adev->dev, "failed to add adapter\n"); 1092 goto err_add_adap; 1093 } 1094 1095 of_i2c_register_devices(adap); 1096 1097 pm_runtime_put(&adev->dev); 1098 1099 return 0; 1100 1101 err_add_adap: 1102 clk_put(dev->clk); 1103 err_no_clk: 1104 free_irq(dev->irq, dev); 1105 err_irq: 1106 iounmap(dev->virtbase); 1107 err_no_ioremap: 1108 kfree(dev); 1109 err_pinctrl: 1110 err_no_mem: 1111 1112 return ret; 1113 } 1114 1115 static int nmk_i2c_remove(struct amba_device *adev) 1116 { 1117 struct resource *res = &adev->res; 1118 struct nmk_i2c_dev *dev = amba_get_drvdata(adev); 1119 1120 i2c_del_adapter(&dev->adap); 1121 flush_i2c_fifo(dev); 1122 disable_all_interrupts(dev); 1123 clear_all_interrupts(dev); 1124 /* disable the controller */ 1125 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1126 free_irq(dev->irq, dev); 1127 iounmap(dev->virtbase); 1128 if (res) 1129 release_mem_region(res->start, resource_size(res)); 1130 clk_put(dev->clk); 1131 pm_runtime_disable(&adev->dev); 1132 kfree(dev); 1133 1134 return 0; 1135 } 1136 1137 static struct amba_id nmk_i2c_ids[] = { 1138 { 1139 .id = 0x00180024, 1140 .mask = 0x00ffffff, 1141 }, 1142 { 1143 .id = 0x00380024, 1144 .mask = 0x00ffffff, 1145 }, 1146 {}, 1147 }; 1148 1149 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1150 1151 static struct amba_driver nmk_i2c_driver = { 1152 .drv = { 1153 .owner = THIS_MODULE, 1154 .name = DRIVER_NAME, 1155 .pm = &nmk_i2c_pm, 1156 }, 1157 .id_table = nmk_i2c_ids, 1158 .probe = nmk_i2c_probe, 1159 .remove = nmk_i2c_remove, 1160 }; 1161 1162 static int __init nmk_i2c_init(void) 1163 { 1164 return amba_driver_register(&nmk_i2c_driver); 1165 } 1166 1167 static void __exit nmk_i2c_exit(void) 1168 { 1169 amba_driver_unregister(&nmk_i2c_driver); 1170 } 1171 1172 subsys_initcall(nmk_i2c_init); 1173 module_exit(nmk_i2c_exit); 1174 1175 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 1176 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1177 MODULE_LICENSE("GPL"); 1178