1 /* 2 * Freescale MXS I2C bus driver 3 * 4 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. 5 * 6 * based on a (non-working) driver which was: 7 * 8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/device.h> 19 #include <linux/module.h> 20 #include <linux/i2c.h> 21 #include <linux/err.h> 22 #include <linux/interrupt.h> 23 #include <linux/completion.h> 24 #include <linux/platform_device.h> 25 #include <linux/jiffies.h> 26 #include <linux/io.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/stmp_device.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/of_i2c.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 35 #define DRIVER_NAME "mxs-i2c" 36 37 #define MXS_I2C_CTRL0 (0x00) 38 #define MXS_I2C_CTRL0_SET (0x04) 39 40 #define MXS_I2C_CTRL0_SFTRST 0x80000000 41 #define MXS_I2C_CTRL0_RUN 0x20000000 42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 43 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 44 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 45 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 46 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000 47 #define MXS_I2C_CTRL0_DIRECTION 0x00010000 48 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) 49 50 #define MXS_I2C_TIMING0 (0x10) 51 #define MXS_I2C_TIMING1 (0x20) 52 #define MXS_I2C_TIMING2 (0x30) 53 54 #define MXS_I2C_CTRL1 (0x40) 55 #define MXS_I2C_CTRL1_SET (0x44) 56 #define MXS_I2C_CTRL1_CLR (0x48) 57 58 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 59 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80 60 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 61 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 62 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 63 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08 64 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04 65 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02 66 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 67 68 #define MXS_I2C_STAT (0x50) 69 #define MXS_I2C_STAT_BUS_BUSY 0x00000800 70 #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400 71 72 #define MXS_I2C_DATA (0xa0) 73 74 #define MXS_I2C_DEBUG0 (0xb0) 75 #define MXS_I2C_DEBUG0_CLR (0xb8) 76 77 #define MXS_I2C_DEBUG0_DMAREQ 0x80000000 78 79 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \ 80 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \ 81 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \ 82 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ 83 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ 84 MXS_I2C_CTRL1_SLAVE_IRQ) 85 86 87 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ 88 MXS_I2C_CTRL0_PRE_SEND_START | \ 89 MXS_I2C_CTRL0_MASTER_MODE | \ 90 MXS_I2C_CTRL0_DIRECTION | \ 91 MXS_I2C_CTRL0_XFER_COUNT(1)) 92 93 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \ 94 MXS_I2C_CTRL0_MASTER_MODE | \ 95 MXS_I2C_CTRL0_DIRECTION) 96 97 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ 98 MXS_I2C_CTRL0_MASTER_MODE) 99 100 /** 101 * struct mxs_i2c_dev - per device, private MXS-I2C data 102 * 103 * @dev: driver model device node 104 * @regs: IO registers pointer 105 * @cmd_complete: completion object for transaction wait 106 * @cmd_err: error code for last transaction 107 * @adapter: i2c subsystem adapter node 108 */ 109 struct mxs_i2c_dev { 110 struct device *dev; 111 void __iomem *regs; 112 struct completion cmd_complete; 113 int cmd_err; 114 struct i2c_adapter adapter; 115 116 uint32_t timing0; 117 uint32_t timing1; 118 119 /* DMA support components */ 120 struct dma_chan *dmach; 121 uint32_t pio_data[2]; 122 uint32_t addr_data; 123 struct scatterlist sg_io[2]; 124 bool dma_read; 125 }; 126 127 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) 128 { 129 stmp_reset_block(i2c->regs); 130 131 /* 132 * Configure timing for the I2C block. The I2C TIMING2 register has to 133 * be programmed with this particular magic number. The rest is derived 134 * from the XTAL speed and requested I2C speed. 135 * 136 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4]. 137 */ 138 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0); 139 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1); 140 writel(0x00300030, i2c->regs + MXS_I2C_TIMING2); 141 142 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 143 } 144 145 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) 146 { 147 if (i2c->dma_read) { 148 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 149 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 150 } else { 151 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 152 } 153 } 154 155 static void mxs_i2c_dma_irq_callback(void *param) 156 { 157 struct mxs_i2c_dev *i2c = param; 158 159 complete(&i2c->cmd_complete); 160 mxs_i2c_dma_finish(i2c); 161 } 162 163 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap, 164 struct i2c_msg *msg, uint32_t flags) 165 { 166 struct dma_async_tx_descriptor *desc; 167 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 168 169 if (msg->flags & I2C_M_RD) { 170 i2c->dma_read = 1; 171 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ; 172 173 /* 174 * SELECT command. 175 */ 176 177 /* Queue the PIO register write transfer. */ 178 i2c->pio_data[0] = MXS_CMD_I2C_SELECT; 179 desc = dmaengine_prep_slave_sg(i2c->dmach, 180 (struct scatterlist *)&i2c->pio_data[0], 181 1, DMA_TRANS_NONE, 0); 182 if (!desc) { 183 dev_err(i2c->dev, 184 "Failed to get PIO reg. write descriptor.\n"); 185 goto select_init_pio_fail; 186 } 187 188 /* Queue the DMA data transfer. */ 189 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1); 190 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 191 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1, 192 DMA_MEM_TO_DEV, 193 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 194 if (!desc) { 195 dev_err(i2c->dev, 196 "Failed to get DMA data write descriptor.\n"); 197 goto select_init_dma_fail; 198 } 199 200 /* 201 * READ command. 202 */ 203 204 /* Queue the PIO register write transfer. */ 205 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ | 206 MXS_I2C_CTRL0_XFER_COUNT(msg->len); 207 desc = dmaengine_prep_slave_sg(i2c->dmach, 208 (struct scatterlist *)&i2c->pio_data[1], 209 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT); 210 if (!desc) { 211 dev_err(i2c->dev, 212 "Failed to get PIO reg. write descriptor.\n"); 213 goto select_init_dma_fail; 214 } 215 216 /* Queue the DMA data transfer. */ 217 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len); 218 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 219 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1, 220 DMA_DEV_TO_MEM, 221 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 222 if (!desc) { 223 dev_err(i2c->dev, 224 "Failed to get DMA data write descriptor.\n"); 225 goto read_init_dma_fail; 226 } 227 } else { 228 i2c->dma_read = 0; 229 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE; 230 231 /* 232 * WRITE command. 233 */ 234 235 /* Queue the PIO register write transfer. */ 236 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE | 237 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1); 238 desc = dmaengine_prep_slave_sg(i2c->dmach, 239 (struct scatterlist *)&i2c->pio_data[0], 240 1, DMA_TRANS_NONE, 0); 241 if (!desc) { 242 dev_err(i2c->dev, 243 "Failed to get PIO reg. write descriptor.\n"); 244 goto write_init_pio_fail; 245 } 246 247 /* Queue the DMA data transfer. */ 248 sg_init_table(i2c->sg_io, 2); 249 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1); 250 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len); 251 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 252 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2, 253 DMA_MEM_TO_DEV, 254 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 255 if (!desc) { 256 dev_err(i2c->dev, 257 "Failed to get DMA data write descriptor.\n"); 258 goto write_init_dma_fail; 259 } 260 } 261 262 /* 263 * The last descriptor must have this callback, 264 * to finish the DMA transaction. 265 */ 266 desc->callback = mxs_i2c_dma_irq_callback; 267 desc->callback_param = i2c; 268 269 /* Start the transfer. */ 270 dmaengine_submit(desc); 271 dma_async_issue_pending(i2c->dmach); 272 return 0; 273 274 /* Read failpath. */ 275 read_init_dma_fail: 276 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 277 select_init_dma_fail: 278 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 279 select_init_pio_fail: 280 dmaengine_terminate_all(i2c->dmach); 281 return -EINVAL; 282 283 /* Write failpath. */ 284 write_init_dma_fail: 285 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 286 write_init_pio_fail: 287 dmaengine_terminate_all(i2c->dmach); 288 return -EINVAL; 289 } 290 291 static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c) 292 { 293 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 294 295 while (!(readl(i2c->regs + MXS_I2C_DEBUG0) & 296 MXS_I2C_DEBUG0_DMAREQ)) { 297 if (time_after(jiffies, timeout)) 298 return -ETIMEDOUT; 299 cond_resched(); 300 } 301 302 return 0; 303 } 304 305 static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last) 306 { 307 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 308 309 /* 310 * We do not use interrupts in the PIO mode. Due to the 311 * maximum transfer length being 8 bytes in PIO mode, the 312 * overhead of interrupt would be too large and this would 313 * neglect the gain from using the PIO mode. 314 */ 315 316 while (!(readl(i2c->regs + MXS_I2C_CTRL1) & 317 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) { 318 if (time_after(jiffies, timeout)) 319 return -ETIMEDOUT; 320 cond_resched(); 321 } 322 323 writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ, 324 i2c->regs + MXS_I2C_CTRL1_CLR); 325 326 /* 327 * When ending a transfer with a stop, we have to wait for the bus to 328 * go idle before we report the transfer as completed. Otherwise the 329 * start of the next transfer may race with the end of the current one. 330 */ 331 while (last && (readl(i2c->regs + MXS_I2C_STAT) & 332 (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) { 333 if (time_after(jiffies, timeout)) 334 return -ETIMEDOUT; 335 cond_resched(); 336 } 337 338 return 0; 339 } 340 341 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c) 342 { 343 u32 state; 344 345 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK; 346 347 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) 348 i2c->cmd_err = -ENXIO; 349 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | 350 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | 351 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | 352 MXS_I2C_CTRL1_SLAVE_IRQ)) 353 i2c->cmd_err = -EIO; 354 355 return i2c->cmd_err; 356 } 357 358 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd) 359 { 360 u32 reg; 361 362 writel(cmd, i2c->regs + MXS_I2C_CTRL0); 363 364 /* readback makes sure the write is latched into hardware */ 365 reg = readl(i2c->regs + MXS_I2C_CTRL0); 366 reg |= MXS_I2C_CTRL0_RUN; 367 writel(reg, i2c->regs + MXS_I2C_CTRL0); 368 } 369 370 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap, 371 struct i2c_msg *msg, uint32_t flags) 372 { 373 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 374 uint32_t addr_data = msg->addr << 1; 375 uint32_t data = 0; 376 int i, shifts_left, ret; 377 378 /* Mute IRQs coming from this block. */ 379 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR); 380 381 if (msg->flags & I2C_M_RD) { 382 addr_data |= I2C_SMBUS_READ; 383 384 /* SELECT command. */ 385 mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT); 386 387 ret = mxs_i2c_pio_wait_dmareq(i2c); 388 if (ret) 389 return ret; 390 391 writel(addr_data, i2c->regs + MXS_I2C_DATA); 392 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR); 393 394 ret = mxs_i2c_pio_wait_cplt(i2c, 0); 395 if (ret) 396 return ret; 397 398 if (mxs_i2c_pio_check_error_state(i2c)) 399 goto cleanup; 400 401 /* READ command. */ 402 mxs_i2c_pio_trigger_cmd(i2c, 403 MXS_CMD_I2C_READ | flags | 404 MXS_I2C_CTRL0_XFER_COUNT(msg->len)); 405 406 for (i = 0; i < msg->len; i++) { 407 if ((i & 3) == 0) { 408 ret = mxs_i2c_pio_wait_dmareq(i2c); 409 if (ret) 410 return ret; 411 data = readl(i2c->regs + MXS_I2C_DATA); 412 writel(MXS_I2C_DEBUG0_DMAREQ, 413 i2c->regs + MXS_I2C_DEBUG0_CLR); 414 } 415 msg->buf[i] = data & 0xff; 416 data >>= 8; 417 } 418 } else { 419 addr_data |= I2C_SMBUS_WRITE; 420 421 /* WRITE command. */ 422 mxs_i2c_pio_trigger_cmd(i2c, 423 MXS_CMD_I2C_WRITE | flags | 424 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1)); 425 426 /* 427 * The LSB of data buffer is the first byte blasted across 428 * the bus. Higher order bytes follow. Thus the following 429 * filling schematic. 430 */ 431 data = addr_data << 24; 432 for (i = 0; i < msg->len; i++) { 433 data >>= 8; 434 data |= (msg->buf[i] << 24); 435 if ((i & 3) == 2) { 436 ret = mxs_i2c_pio_wait_dmareq(i2c); 437 if (ret) 438 return ret; 439 writel(data, i2c->regs + MXS_I2C_DATA); 440 writel(MXS_I2C_DEBUG0_DMAREQ, 441 i2c->regs + MXS_I2C_DEBUG0_CLR); 442 } 443 } 444 445 shifts_left = 24 - (i & 3) * 8; 446 if (shifts_left) { 447 data >>= shifts_left; 448 ret = mxs_i2c_pio_wait_dmareq(i2c); 449 if (ret) 450 return ret; 451 writel(data, i2c->regs + MXS_I2C_DATA); 452 writel(MXS_I2C_DEBUG0_DMAREQ, 453 i2c->regs + MXS_I2C_DEBUG0_CLR); 454 } 455 } 456 457 ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP); 458 if (ret) 459 return ret; 460 461 /* make sure we capture any occurred error into cmd_err */ 462 mxs_i2c_pio_check_error_state(i2c); 463 464 cleanup: 465 /* Clear any dangling IRQs and re-enable interrupts. */ 466 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR); 467 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 468 469 return 0; 470 } 471 472 /* 473 * Low level master read/write transaction. 474 */ 475 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, 476 int stop) 477 { 478 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 479 int ret; 480 int flags; 481 482 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; 483 484 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 485 msg->addr, msg->len, msg->flags, stop); 486 487 if (msg->len == 0) 488 return -EINVAL; 489 490 /* 491 * The current boundary to select between PIO/DMA transfer method 492 * is set to 8 bytes, transfers shorter than 8 bytes are transfered 493 * using PIO mode while longer transfers use DMA. The 8 byte border is 494 * based on this empirical measurement and a lot of previous frobbing. 495 */ 496 i2c->cmd_err = 0; 497 if (msg->len < 8) { 498 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags); 499 if (ret) 500 mxs_i2c_reset(i2c); 501 } else { 502 INIT_COMPLETION(i2c->cmd_complete); 503 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); 504 if (ret) 505 return ret; 506 507 ret = wait_for_completion_timeout(&i2c->cmd_complete, 508 msecs_to_jiffies(1000)); 509 if (ret == 0) 510 goto timeout; 511 } 512 513 if (i2c->cmd_err == -ENXIO) { 514 /* 515 * If the transfer fails with a NAK from the slave the 516 * controller halts until it gets told to return to idle state. 517 */ 518 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK, 519 i2c->regs + MXS_I2C_CTRL1_SET); 520 } 521 522 ret = i2c->cmd_err; 523 524 dev_dbg(i2c->dev, "Done with err=%d\n", ret); 525 526 return ret; 527 528 timeout: 529 dev_dbg(i2c->dev, "Timeout!\n"); 530 mxs_i2c_dma_finish(i2c); 531 mxs_i2c_reset(i2c); 532 return -ETIMEDOUT; 533 } 534 535 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 536 int num) 537 { 538 int i; 539 int err; 540 541 for (i = 0; i < num; i++) { 542 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1)); 543 if (err) 544 return err; 545 } 546 547 return num; 548 } 549 550 static u32 mxs_i2c_func(struct i2c_adapter *adap) 551 { 552 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 553 } 554 555 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) 556 { 557 struct mxs_i2c_dev *i2c = dev_id; 558 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; 559 560 if (!stat) 561 return IRQ_NONE; 562 563 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) 564 i2c->cmd_err = -ENXIO; 565 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | 566 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | 567 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) 568 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ 569 i2c->cmd_err = -EIO; 570 571 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); 572 573 return IRQ_HANDLED; 574 } 575 576 static const struct i2c_algorithm mxs_i2c_algo = { 577 .master_xfer = mxs_i2c_xfer, 578 .functionality = mxs_i2c_func, 579 }; 580 581 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed) 582 { 583 /* The I2C block clock run at 24MHz */ 584 const uint32_t clk = 24000000; 585 uint32_t base; 586 uint16_t high_count, low_count, rcv_count, xmit_count; 587 struct device *dev = i2c->dev; 588 589 if (speed > 540000) { 590 dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed); 591 speed = 540000; 592 } else if (speed < 12000) { 593 dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed); 594 speed = 12000; 595 } 596 597 /* 598 * The timing derivation algorithm. There is no documentation for this 599 * algorithm available, it was derived by using the scope and fiddling 600 * with constants until the result observed on the scope was good enough 601 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be 602 * possible to assume the algorithm works for other frequencies as well. 603 * 604 * Note it was necessary to cap the frequency on both ends as it's not 605 * possible to configure completely arbitrary frequency for the I2C bus 606 * clock. 607 */ 608 base = ((clk / speed) - 38) / 2; 609 high_count = base + 3; 610 low_count = base - 3; 611 rcv_count = (high_count * 3) / 4; 612 xmit_count = low_count / 4; 613 614 i2c->timing0 = (high_count << 16) | rcv_count; 615 i2c->timing1 = (low_count << 16) | xmit_count; 616 } 617 618 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) 619 { 620 uint32_t speed; 621 struct device *dev = i2c->dev; 622 struct device_node *node = dev->of_node; 623 int ret; 624 625 ret = of_property_read_u32(node, "clock-frequency", &speed); 626 if (ret) { 627 dev_warn(dev, "No I2C speed selected, using 100kHz\n"); 628 speed = 100000; 629 } 630 631 mxs_i2c_derive_timing(i2c, speed); 632 633 return 0; 634 } 635 636 static int mxs_i2c_probe(struct platform_device *pdev) 637 { 638 struct device *dev = &pdev->dev; 639 struct mxs_i2c_dev *i2c; 640 struct i2c_adapter *adap; 641 struct pinctrl *pinctrl; 642 struct resource *res; 643 resource_size_t res_size; 644 int err, irq; 645 646 pinctrl = devm_pinctrl_get_select_default(dev); 647 if (IS_ERR(pinctrl)) 648 return PTR_ERR(pinctrl); 649 650 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); 651 if (!i2c) 652 return -ENOMEM; 653 654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 655 irq = platform_get_irq(pdev, 0); 656 657 if (!res || irq < 0) 658 return -ENOENT; 659 660 res_size = resource_size(res); 661 if (!devm_request_mem_region(dev, res->start, res_size, res->name)) 662 return -EBUSY; 663 664 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size); 665 if (!i2c->regs) 666 return -EBUSY; 667 668 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); 669 if (err) 670 return err; 671 672 i2c->dev = dev; 673 674 init_completion(&i2c->cmd_complete); 675 676 if (dev->of_node) { 677 err = mxs_i2c_get_ofdata(i2c); 678 if (err) 679 return err; 680 } 681 682 /* Setup the DMA */ 683 i2c->dmach = dma_request_slave_channel(dev, "rx-tx"); 684 if (!i2c->dmach) { 685 dev_err(dev, "Failed to request dma\n"); 686 return -ENODEV; 687 } 688 689 platform_set_drvdata(pdev, i2c); 690 691 /* Do reset to enforce correct startup after pinmuxing */ 692 mxs_i2c_reset(i2c); 693 694 adap = &i2c->adapter; 695 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); 696 adap->owner = THIS_MODULE; 697 adap->algo = &mxs_i2c_algo; 698 adap->dev.parent = dev; 699 adap->nr = pdev->id; 700 adap->dev.of_node = pdev->dev.of_node; 701 i2c_set_adapdata(adap, i2c); 702 err = i2c_add_numbered_adapter(adap); 703 if (err) { 704 dev_err(dev, "Failed to add adapter (%d)\n", err); 705 writel(MXS_I2C_CTRL0_SFTRST, 706 i2c->regs + MXS_I2C_CTRL0_SET); 707 return err; 708 } 709 710 of_i2c_register_devices(adap); 711 712 return 0; 713 } 714 715 static int mxs_i2c_remove(struct platform_device *pdev) 716 { 717 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev); 718 719 i2c_del_adapter(&i2c->adapter); 720 721 if (i2c->dmach) 722 dma_release_channel(i2c->dmach); 723 724 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); 725 726 return 0; 727 } 728 729 static const struct of_device_id mxs_i2c_dt_ids[] = { 730 { .compatible = "fsl,imx28-i2c", }, 731 { /* sentinel */ } 732 }; 733 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); 734 735 static struct platform_driver mxs_i2c_driver = { 736 .driver = { 737 .name = DRIVER_NAME, 738 .owner = THIS_MODULE, 739 .of_match_table = mxs_i2c_dt_ids, 740 }, 741 .remove = mxs_i2c_remove, 742 }; 743 744 static int __init mxs_i2c_init(void) 745 { 746 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe); 747 } 748 subsys_initcall(mxs_i2c_init); 749 750 static void __exit mxs_i2c_exit(void) 751 { 752 platform_driver_unregister(&mxs_i2c_driver); 753 } 754 module_exit(mxs_i2c_exit); 755 756 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 757 MODULE_DESCRIPTION("MXS I2C Bus Driver"); 758 MODULE_LICENSE("GPL"); 759 MODULE_ALIAS("platform:" DRIVER_NAME); 760