1 /* 2 * Driver for the i2c controller on the Marvell line of host bridges 3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/mv643xx_i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/clk.h> 26 #include <linux/err.h> 27 #include <linux/delay.h> 28 29 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) 30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) 31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) 32 33 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) 34 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) 35 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) 36 #define MV64XXX_I2C_REG_CONTROL_START BIT(5) 37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) 38 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) 39 40 /* Ctlr status values */ 41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 42 #define MV64XXX_I2C_STATUS_MAST_START 0x08 43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 58 59 /* Register defines (I2C bridge) */ 60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0 61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4 62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8 63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc 64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0 65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4 66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8 67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC 68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 69 70 /* Bridge Control values */ 71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) 72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) 73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) 75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) 78 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20) 79 80 /* Bridge Status values */ 81 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) 82 83 /* Driver states */ 84 enum { 85 MV64XXX_I2C_STATE_INVALID, 86 MV64XXX_I2C_STATE_IDLE, 87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND, 88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART, 89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, 90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, 91 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, 92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, 93 }; 94 95 /* Driver actions */ 96 enum { 97 MV64XXX_I2C_ACTION_INVALID, 98 MV64XXX_I2C_ACTION_CONTINUE, 99 MV64XXX_I2C_ACTION_SEND_RESTART, 100 MV64XXX_I2C_ACTION_SEND_ADDR_1, 101 MV64XXX_I2C_ACTION_SEND_ADDR_2, 102 MV64XXX_I2C_ACTION_SEND_DATA, 103 MV64XXX_I2C_ACTION_RCV_DATA, 104 MV64XXX_I2C_ACTION_RCV_DATA_STOP, 105 MV64XXX_I2C_ACTION_SEND_STOP, 106 }; 107 108 struct mv64xxx_i2c_regs { 109 u8 addr; 110 u8 ext_addr; 111 u8 data; 112 u8 control; 113 u8 status; 114 u8 clock; 115 u8 soft_reset; 116 }; 117 118 struct mv64xxx_i2c_data { 119 struct i2c_msg *msgs; 120 int num_msgs; 121 int irq; 122 u32 state; 123 u32 action; 124 u32 aborting; 125 u32 cntl_bits; 126 void __iomem *reg_base; 127 struct mv64xxx_i2c_regs reg_offsets; 128 u32 addr1; 129 u32 addr2; 130 u32 bytes_left; 131 u32 byte_posn; 132 u32 send_stop; 133 u32 block; 134 int rc; 135 u32 freq_m; 136 u32 freq_n; 137 #if defined(CONFIG_HAVE_CLK) 138 struct clk *clk; 139 #endif 140 wait_queue_head_t waitq; 141 spinlock_t lock; 142 struct i2c_msg *msg; 143 struct i2c_adapter adapter; 144 bool offload_enabled; 145 /* 5us delay in order to avoid repeated start timing violation */ 146 bool errata_delay; 147 struct reset_control *rstc; 148 bool irq_clear_inverted; 149 /* Clk div is 2 to the power n, not 2 to the power n + 1 */ 150 bool clk_n_base_0; 151 }; 152 153 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { 154 .addr = 0x00, 155 .ext_addr = 0x10, 156 .data = 0x04, 157 .control = 0x08, 158 .status = 0x0c, 159 .clock = 0x0c, 160 .soft_reset = 0x1c, 161 }; 162 163 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = { 164 .addr = 0x00, 165 .ext_addr = 0x04, 166 .data = 0x08, 167 .control = 0x0c, 168 .status = 0x10, 169 .clock = 0x14, 170 .soft_reset = 0x18, 171 }; 172 173 static void 174 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, 175 struct i2c_msg *msg) 176 { 177 u32 dir = 0; 178 179 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | 180 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; 181 182 if (msg->flags & I2C_M_RD) 183 dir = 1; 184 185 if (msg->flags & I2C_M_TEN) { 186 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; 187 drv_data->addr2 = (u32)msg->addr & 0xff; 188 } else { 189 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir; 190 drv_data->addr2 = 0; 191 } 192 } 193 194 /* 195 ***************************************************************************** 196 * 197 * Finite State Machine & Interrupt Routines 198 * 199 ***************************************************************************** 200 */ 201 202 /* Reset hardware and initialize FSM */ 203 static void 204 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 205 { 206 if (drv_data->offload_enabled) { 207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 208 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); 209 writel(0, drv_data->reg_base + 210 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 211 writel(0, drv_data->reg_base + 212 MV64XXX_I2C_REG_BRIDGE_INTR_MASK); 213 } 214 215 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); 216 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), 217 drv_data->reg_base + drv_data->reg_offsets.clock); 218 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); 219 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); 220 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 221 drv_data->reg_base + drv_data->reg_offsets.control); 222 drv_data->state = MV64XXX_I2C_STATE_IDLE; 223 } 224 225 static void 226 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) 227 { 228 /* 229 * If state is idle, then this is likely the remnants of an old 230 * operation that driver has given up on or the user has killed. 231 * If so, issue the stop condition and go to idle. 232 */ 233 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { 234 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 235 return; 236 } 237 238 /* The status from the ctlr [mostly] tells us what to do next */ 239 switch (status) { 240 /* Start condition interrupt */ 241 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ 242 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ 243 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 244 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 245 break; 246 247 /* Performing a write */ 248 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ 249 if (drv_data->msg->flags & I2C_M_TEN) { 250 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 251 drv_data->state = 252 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 253 break; 254 } 255 /* FALLTHRU */ 256 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ 257 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ 258 if ((drv_data->bytes_left == 0) 259 || (drv_data->aborting 260 && (drv_data->byte_posn != 0))) { 261 if (drv_data->send_stop || drv_data->aborting) { 262 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 263 drv_data->state = MV64XXX_I2C_STATE_IDLE; 264 } else { 265 drv_data->action = 266 MV64XXX_I2C_ACTION_SEND_RESTART; 267 drv_data->state = 268 MV64XXX_I2C_STATE_WAITING_FOR_RESTART; 269 } 270 } else { 271 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 272 drv_data->state = 273 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 274 drv_data->bytes_left--; 275 } 276 break; 277 278 /* Performing a read */ 279 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ 280 if (drv_data->msg->flags & I2C_M_TEN) { 281 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 282 drv_data->state = 283 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 284 break; 285 } 286 /* FALLTHRU */ 287 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ 288 if (drv_data->bytes_left == 0) { 289 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 290 drv_data->state = MV64XXX_I2C_STATE_IDLE; 291 break; 292 } 293 /* FALLTHRU */ 294 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ 295 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) 296 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 297 else { 298 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; 299 drv_data->bytes_left--; 300 } 301 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 302 303 if ((drv_data->bytes_left == 1) || drv_data->aborting) 304 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; 305 break; 306 307 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ 308 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; 309 drv_data->state = MV64XXX_I2C_STATE_IDLE; 310 break; 311 312 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ 313 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ 314 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ 315 /* Doesn't seem to be a device at other end */ 316 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 317 drv_data->state = MV64XXX_I2C_STATE_IDLE; 318 drv_data->rc = -ENXIO; 319 break; 320 321 default: 322 dev_err(&drv_data->adapter.dev, 323 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " 324 "status: 0x%x, addr: 0x%x, flags: 0x%x\n", 325 drv_data->state, status, drv_data->msg->addr, 326 drv_data->msg->flags); 327 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 328 mv64xxx_i2c_hw_init(drv_data); 329 drv_data->rc = -EIO; 330 } 331 } 332 333 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) 334 { 335 drv_data->msg = drv_data->msgs; 336 drv_data->byte_posn = 0; 337 drv_data->bytes_left = drv_data->msg->len; 338 drv_data->aborting = 0; 339 drv_data->rc = 0; 340 341 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs); 342 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 343 drv_data->reg_base + drv_data->reg_offsets.control); 344 } 345 346 static void 347 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) 348 { 349 switch(drv_data->action) { 350 case MV64XXX_I2C_ACTION_SEND_RESTART: 351 /* We should only get here if we have further messages */ 352 BUG_ON(drv_data->num_msgs == 0); 353 354 drv_data->msgs++; 355 drv_data->num_msgs--; 356 mv64xxx_i2c_send_start(drv_data); 357 358 if (drv_data->errata_delay) 359 udelay(5); 360 361 /* 362 * We're never at the start of the message here, and by this 363 * time it's already too late to do any protocol mangling. 364 * Thankfully, do not advertise support for that feature. 365 */ 366 drv_data->send_stop = drv_data->num_msgs == 1; 367 break; 368 369 case MV64XXX_I2C_ACTION_CONTINUE: 370 writel(drv_data->cntl_bits, 371 drv_data->reg_base + drv_data->reg_offsets.control); 372 break; 373 374 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 375 writel(drv_data->addr1, 376 drv_data->reg_base + drv_data->reg_offsets.data); 377 writel(drv_data->cntl_bits, 378 drv_data->reg_base + drv_data->reg_offsets.control); 379 break; 380 381 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 382 writel(drv_data->addr2, 383 drv_data->reg_base + drv_data->reg_offsets.data); 384 writel(drv_data->cntl_bits, 385 drv_data->reg_base + drv_data->reg_offsets.control); 386 break; 387 388 case MV64XXX_I2C_ACTION_SEND_DATA: 389 writel(drv_data->msg->buf[drv_data->byte_posn++], 390 drv_data->reg_base + drv_data->reg_offsets.data); 391 writel(drv_data->cntl_bits, 392 drv_data->reg_base + drv_data->reg_offsets.control); 393 break; 394 395 case MV64XXX_I2C_ACTION_RCV_DATA: 396 drv_data->msg->buf[drv_data->byte_posn++] = 397 readl(drv_data->reg_base + drv_data->reg_offsets.data); 398 writel(drv_data->cntl_bits, 399 drv_data->reg_base + drv_data->reg_offsets.control); 400 break; 401 402 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 403 drv_data->msg->buf[drv_data->byte_posn++] = 404 readl(drv_data->reg_base + drv_data->reg_offsets.data); 405 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 406 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 407 drv_data->reg_base + drv_data->reg_offsets.control); 408 drv_data->block = 0; 409 if (drv_data->errata_delay) 410 udelay(5); 411 412 wake_up(&drv_data->waitq); 413 break; 414 415 case MV64XXX_I2C_ACTION_INVALID: 416 default: 417 dev_err(&drv_data->adapter.dev, 418 "mv64xxx_i2c_do_action: Invalid action: %d\n", 419 drv_data->action); 420 drv_data->rc = -EIO; 421 422 /* FALLTHRU */ 423 case MV64XXX_I2C_ACTION_SEND_STOP: 424 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 425 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 426 drv_data->reg_base + drv_data->reg_offsets.control); 427 drv_data->block = 0; 428 wake_up(&drv_data->waitq); 429 break; 430 } 431 } 432 433 static void 434 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data, 435 struct i2c_msg *msg) 436 { 437 u32 buf[2]; 438 439 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO); 440 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI); 441 442 memcpy(msg->buf, buf, msg->len); 443 } 444 445 static int 446 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data) 447 { 448 u32 cause, status; 449 450 cause = readl(drv_data->reg_base + 451 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 452 if (!cause) 453 return IRQ_NONE; 454 455 status = readl(drv_data->reg_base + 456 MV64XXX_I2C_REG_BRIDGE_STATUS); 457 458 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) { 459 drv_data->rc = -EIO; 460 goto out; 461 } 462 463 drv_data->rc = 0; 464 465 /* 466 * Transaction is a one message read transaction, read data 467 * for this message. 468 */ 469 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) { 470 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs); 471 drv_data->msgs++; 472 drv_data->num_msgs--; 473 } 474 /* 475 * Transaction is a two messages write/read transaction, read 476 * data for the second (read) message. 477 */ 478 else if (drv_data->num_msgs == 2 && 479 !(drv_data->msgs[0].flags & I2C_M_RD) && 480 drv_data->msgs[1].flags & I2C_M_RD) { 481 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1); 482 drv_data->msgs += 2; 483 drv_data->num_msgs -= 2; 484 } 485 486 out: 487 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 488 writel(0, drv_data->reg_base + 489 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 490 drv_data->block = 0; 491 492 wake_up(&drv_data->waitq); 493 494 return IRQ_HANDLED; 495 } 496 497 static irqreturn_t 498 mv64xxx_i2c_intr(int irq, void *dev_id) 499 { 500 struct mv64xxx_i2c_data *drv_data = dev_id; 501 unsigned long flags; 502 u32 status; 503 irqreturn_t rc = IRQ_NONE; 504 505 spin_lock_irqsave(&drv_data->lock, flags); 506 507 if (drv_data->offload_enabled) 508 rc = mv64xxx_i2c_intr_offload(drv_data); 509 510 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & 511 MV64XXX_I2C_REG_CONTROL_IFLG) { 512 status = readl(drv_data->reg_base + drv_data->reg_offsets.status); 513 mv64xxx_i2c_fsm(drv_data, status); 514 mv64xxx_i2c_do_action(drv_data); 515 516 if (drv_data->irq_clear_inverted) 517 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG, 518 drv_data->reg_base + drv_data->reg_offsets.control); 519 520 rc = IRQ_HANDLED; 521 } 522 spin_unlock_irqrestore(&drv_data->lock, flags); 523 524 return rc; 525 } 526 527 /* 528 ***************************************************************************** 529 * 530 * I2C Msg Execution Routines 531 * 532 ***************************************************************************** 533 */ 534 static void 535 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 536 { 537 long time_left; 538 unsigned long flags; 539 char abort = 0; 540 541 time_left = wait_event_timeout(drv_data->waitq, 542 !drv_data->block, drv_data->adapter.timeout); 543 544 spin_lock_irqsave(&drv_data->lock, flags); 545 if (!time_left) { /* Timed out */ 546 drv_data->rc = -ETIMEDOUT; 547 abort = 1; 548 } else if (time_left < 0) { /* Interrupted/Error */ 549 drv_data->rc = time_left; /* errno value */ 550 abort = 1; 551 } 552 553 if (abort && drv_data->block) { 554 drv_data->aborting = 1; 555 spin_unlock_irqrestore(&drv_data->lock, flags); 556 557 time_left = wait_event_timeout(drv_data->waitq, 558 !drv_data->block, drv_data->adapter.timeout); 559 560 if ((time_left <= 0) && drv_data->block) { 561 drv_data->state = MV64XXX_I2C_STATE_IDLE; 562 dev_err(&drv_data->adapter.dev, 563 "mv64xxx: I2C bus locked, block: %d, " 564 "time_left: %d\n", drv_data->block, 565 (int)time_left); 566 mv64xxx_i2c_hw_init(drv_data); 567 } 568 } else 569 spin_unlock_irqrestore(&drv_data->lock, flags); 570 } 571 572 static int 573 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 574 int is_last) 575 { 576 unsigned long flags; 577 578 spin_lock_irqsave(&drv_data->lock, flags); 579 580 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; 581 582 drv_data->send_stop = is_last; 583 drv_data->block = 1; 584 mv64xxx_i2c_send_start(drv_data); 585 spin_unlock_irqrestore(&drv_data->lock, flags); 586 587 mv64xxx_i2c_wait_for_completion(drv_data); 588 return drv_data->rc; 589 } 590 591 static void 592 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data) 593 { 594 struct i2c_msg *msg = drv_data->msgs; 595 u32 buf[2]; 596 597 memcpy(buf, msg->buf, msg->len); 598 599 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); 600 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); 601 } 602 603 static int 604 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data) 605 { 606 struct i2c_msg *msgs = drv_data->msgs; 607 int num = drv_data->num_msgs; 608 unsigned long ctrl_reg; 609 unsigned long flags; 610 611 spin_lock_irqsave(&drv_data->lock, flags); 612 613 /* Build transaction */ 614 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE | 615 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT); 616 617 if (msgs[0].flags & I2C_M_TEN) 618 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT; 619 620 /* Single write message transaction */ 621 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) { 622 size_t len = msgs[0].len - 1; 623 624 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR | 625 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT); 626 mv64xxx_i2c_prepare_tx(drv_data); 627 } 628 /* Single read message transaction */ 629 else if (num == 1 && msgs[0].flags & I2C_M_RD) { 630 size_t len = msgs[0].len - 1; 631 632 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD | 633 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT); 634 } 635 /* 636 * Transaction with one write and one read message. This is 637 * guaranteed by the mv64xx_i2c_can_offload() checks. 638 */ 639 else if (num == 2) { 640 size_t lentx = msgs[0].len - 1; 641 size_t lenrx = msgs[1].len - 1; 642 643 ctrl_reg |= 644 MV64XXX_I2C_BRIDGE_CONTROL_RD | 645 MV64XXX_I2C_BRIDGE_CONTROL_WR | 646 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) | 647 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) | 648 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START; 649 mv64xxx_i2c_prepare_tx(drv_data); 650 } 651 652 /* Execute transaction */ 653 drv_data->block = 1; 654 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 655 spin_unlock_irqrestore(&drv_data->lock, flags); 656 657 mv64xxx_i2c_wait_for_completion(drv_data); 658 659 return drv_data->rc; 660 } 661 662 static bool 663 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg) 664 { 665 return msg->len <= 8 && msg->len >= 1; 666 } 667 668 static bool 669 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data) 670 { 671 struct i2c_msg *msgs = drv_data->msgs; 672 int num = drv_data->num_msgs; 673 674 if (!drv_data->offload_enabled) 675 return false; 676 677 /* 678 * We can offload a transaction consisting of a single 679 * message, as long as the message has a length between 1 and 680 * 8 bytes. 681 */ 682 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs)) 683 return true; 684 685 /* 686 * We can offload a transaction consisting of two messages, if 687 * the first is a write and a second is a read, and both have 688 * a length between 1 and 8 bytes. 689 */ 690 if (num == 2 && 691 mv64xxx_i2c_valid_offload_sz(msgs) && 692 mv64xxx_i2c_valid_offload_sz(msgs + 1) && 693 !(msgs[0].flags & I2C_M_RD) && 694 msgs[1].flags & I2C_M_RD) 695 return true; 696 697 return false; 698 } 699 700 /* 701 ***************************************************************************** 702 * 703 * I2C Core Support Routines (Interface to higher level I2C code) 704 * 705 ***************************************************************************** 706 */ 707 static u32 708 mv64xxx_i2c_functionality(struct i2c_adapter *adap) 709 { 710 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 711 } 712 713 static int 714 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 715 { 716 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 717 int rc, ret = num; 718 719 BUG_ON(drv_data->msgs != NULL); 720 drv_data->msgs = msgs; 721 drv_data->num_msgs = num; 722 723 if (mv64xxx_i2c_can_offload(drv_data)) 724 rc = mv64xxx_i2c_offload_xfer(drv_data); 725 else 726 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1); 727 728 if (rc < 0) 729 ret = rc; 730 731 drv_data->num_msgs = 0; 732 drv_data->msgs = NULL; 733 734 return ret; 735 } 736 737 static const struct i2c_algorithm mv64xxx_i2c_algo = { 738 .master_xfer = mv64xxx_i2c_xfer, 739 .functionality = mv64xxx_i2c_functionality, 740 }; 741 742 /* 743 ***************************************************************************** 744 * 745 * Driver Interface & Early Init Routines 746 * 747 ***************************************************************************** 748 */ 749 static const struct of_device_id mv64xxx_i2c_of_match_table[] = { 750 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i}, 751 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i}, 752 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 753 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 754 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 755 {} 756 }; 757 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); 758 759 #ifdef CONFIG_OF 760 #ifdef CONFIG_HAVE_CLK 761 static int 762 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data, 763 const int tclk, const int n, const int m) 764 { 765 if (drv_data->clk_n_base_0) 766 return tclk / (10 * (m + 1) * (1 << n)); 767 else 768 return tclk / (10 * (m + 1) * (2 << n)); 769 } 770 771 static bool 772 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data, 773 const u32 req_freq, const u32 tclk) 774 { 775 int freq, delta, best_delta = INT_MAX; 776 int m, n; 777 778 for (n = 0; n <= 7; n++) 779 for (m = 0; m <= 15; m++) { 780 freq = mv64xxx_calc_freq(drv_data, tclk, n, m); 781 delta = req_freq - freq; 782 if (delta >= 0 && delta < best_delta) { 783 drv_data->freq_m = m; 784 drv_data->freq_n = n; 785 best_delta = delta; 786 } 787 if (best_delta == 0) 788 return true; 789 } 790 if (best_delta == INT_MAX) 791 return false; 792 return true; 793 } 794 #endif /* CONFIG_HAVE_CLK */ 795 796 static int 797 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 798 struct device *dev) 799 { 800 /* CLK is mandatory when using DT to describe the i2c bus. We 801 * need to know tclk in order to calculate bus clock 802 * factors. 803 */ 804 #if !defined(CONFIG_HAVE_CLK) 805 /* Have OF but no CLK */ 806 return -ENODEV; 807 #else 808 const struct of_device_id *device; 809 struct device_node *np = dev->of_node; 810 u32 bus_freq, tclk; 811 int rc = 0; 812 813 if (IS_ERR(drv_data->clk)) { 814 rc = -ENODEV; 815 goto out; 816 } 817 tclk = clk_get_rate(drv_data->clk); 818 819 if (of_property_read_u32(np, "clock-frequency", &bus_freq)) 820 bus_freq = 100000; /* 100kHz by default */ 821 822 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") || 823 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c")) 824 drv_data->clk_n_base_0 = true; 825 826 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) { 827 rc = -EINVAL; 828 goto out; 829 } 830 drv_data->irq = irq_of_parse_and_map(np, 0); 831 832 drv_data->rstc = devm_reset_control_get_optional(dev, NULL); 833 if (IS_ERR(drv_data->rstc)) { 834 if (PTR_ERR(drv_data->rstc) == -EPROBE_DEFER) { 835 rc = -EPROBE_DEFER; 836 goto out; 837 } 838 } else { 839 reset_control_deassert(drv_data->rstc); 840 } 841 842 /* Its not yet defined how timeouts will be specified in device tree. 843 * So hard code the value to 1 second. 844 */ 845 drv_data->adapter.timeout = HZ; 846 847 device = of_match_device(mv64xxx_i2c_of_match_table, dev); 848 if (!device) 849 return -ENODEV; 850 851 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); 852 853 /* 854 * For controllers embedded in new SoCs activate the 855 * Transaction Generator support and the errata fix. 856 */ 857 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) { 858 drv_data->offload_enabled = true; 859 drv_data->errata_delay = true; 860 } 861 862 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) { 863 drv_data->offload_enabled = false; 864 drv_data->errata_delay = true; 865 } 866 867 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c")) 868 drv_data->irq_clear_inverted = true; 869 870 out: 871 return rc; 872 #endif 873 } 874 #else /* CONFIG_OF */ 875 static int 876 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 877 struct device *dev) 878 { 879 return -ENODEV; 880 } 881 #endif /* CONFIG_OF */ 882 883 static int 884 mv64xxx_i2c_probe(struct platform_device *pd) 885 { 886 struct mv64xxx_i2c_data *drv_data; 887 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); 888 struct resource *r; 889 int rc; 890 891 if ((!pdata && !pd->dev.of_node)) 892 return -ENODEV; 893 894 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data), 895 GFP_KERNEL); 896 if (!drv_data) 897 return -ENOMEM; 898 899 r = platform_get_resource(pd, IORESOURCE_MEM, 0); 900 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r); 901 if (IS_ERR(drv_data->reg_base)) 902 return PTR_ERR(drv_data->reg_base); 903 904 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 905 sizeof(drv_data->adapter.name)); 906 907 init_waitqueue_head(&drv_data->waitq); 908 spin_lock_init(&drv_data->lock); 909 910 #if defined(CONFIG_HAVE_CLK) 911 /* Not all platforms have a clk */ 912 drv_data->clk = devm_clk_get(&pd->dev, NULL); 913 if (!IS_ERR(drv_data->clk)) { 914 clk_prepare(drv_data->clk); 915 clk_enable(drv_data->clk); 916 } 917 #endif 918 if (pdata) { 919 drv_data->freq_m = pdata->freq_m; 920 drv_data->freq_n = pdata->freq_n; 921 drv_data->irq = platform_get_irq(pd, 0); 922 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); 923 drv_data->offload_enabled = false; 924 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets)); 925 } else if (pd->dev.of_node) { 926 rc = mv64xxx_of_config(drv_data, &pd->dev); 927 if (rc) 928 goto exit_clk; 929 } 930 if (drv_data->irq < 0) { 931 rc = -ENXIO; 932 goto exit_reset; 933 } 934 935 drv_data->adapter.dev.parent = &pd->dev; 936 drv_data->adapter.algo = &mv64xxx_i2c_algo; 937 drv_data->adapter.owner = THIS_MODULE; 938 drv_data->adapter.class = I2C_CLASS_DEPRECATED; 939 drv_data->adapter.nr = pd->id; 940 drv_data->adapter.dev.of_node = pd->dev.of_node; 941 platform_set_drvdata(pd, drv_data); 942 i2c_set_adapdata(&drv_data->adapter, drv_data); 943 944 mv64xxx_i2c_hw_init(drv_data); 945 946 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 947 MV64XXX_I2C_CTLR_NAME, drv_data); 948 if (rc) { 949 dev_err(&drv_data->adapter.dev, 950 "mv64xxx: Can't register intr handler irq%d: %d\n", 951 drv_data->irq, rc); 952 goto exit_reset; 953 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { 954 dev_err(&drv_data->adapter.dev, 955 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 956 goto exit_free_irq; 957 } 958 959 return 0; 960 961 exit_free_irq: 962 free_irq(drv_data->irq, drv_data); 963 exit_reset: 964 if (!IS_ERR_OR_NULL(drv_data->rstc)) 965 reset_control_assert(drv_data->rstc); 966 exit_clk: 967 #if defined(CONFIG_HAVE_CLK) 968 /* Not all platforms have a clk */ 969 if (!IS_ERR(drv_data->clk)) { 970 clk_disable(drv_data->clk); 971 clk_unprepare(drv_data->clk); 972 } 973 #endif 974 return rc; 975 } 976 977 static int 978 mv64xxx_i2c_remove(struct platform_device *dev) 979 { 980 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); 981 982 i2c_del_adapter(&drv_data->adapter); 983 free_irq(drv_data->irq, drv_data); 984 if (!IS_ERR_OR_NULL(drv_data->rstc)) 985 reset_control_assert(drv_data->rstc); 986 #if defined(CONFIG_HAVE_CLK) 987 /* Not all platforms have a clk */ 988 if (!IS_ERR(drv_data->clk)) { 989 clk_disable(drv_data->clk); 990 clk_unprepare(drv_data->clk); 991 } 992 #endif 993 994 return 0; 995 } 996 997 static struct platform_driver mv64xxx_i2c_driver = { 998 .probe = mv64xxx_i2c_probe, 999 .remove = mv64xxx_i2c_remove, 1000 .driver = { 1001 .name = MV64XXX_I2C_CTLR_NAME, 1002 .of_match_table = mv64xxx_i2c_of_match_table, 1003 }, 1004 }; 1005 1006 module_platform_driver(mv64xxx_i2c_driver); 1007 1008 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 1009 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); 1010 MODULE_LICENSE("GPL"); 1011