1 /* 2 * Driver for the i2c controller on the Marvell line of host bridges 3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/mv643xx_i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/delay.h> 29 30 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) 31 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) 32 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) 33 34 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) 35 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) 36 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) 37 #define MV64XXX_I2C_REG_CONTROL_START BIT(5) 38 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) 39 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) 40 41 /* Ctlr status values */ 42 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 43 #define MV64XXX_I2C_STATUS_MAST_START 0x08 44 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 46 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 47 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 48 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 49 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 51 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 53 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 55 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 57 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 58 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 59 60 /* Register defines (I2C bridge) */ 61 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0 62 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4 63 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8 64 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc 65 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0 66 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4 67 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8 68 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC 69 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 70 71 /* Bridge Control values */ 72 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) 73 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) 74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 75 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) 76 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 77 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 78 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) 79 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20) 80 81 /* Bridge Status values */ 82 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) 83 84 /* Driver states */ 85 enum { 86 MV64XXX_I2C_STATE_INVALID, 87 MV64XXX_I2C_STATE_IDLE, 88 MV64XXX_I2C_STATE_WAITING_FOR_START_COND, 89 MV64XXX_I2C_STATE_WAITING_FOR_RESTART, 90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, 91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, 92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, 93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, 94 }; 95 96 /* Driver actions */ 97 enum { 98 MV64XXX_I2C_ACTION_INVALID, 99 MV64XXX_I2C_ACTION_CONTINUE, 100 MV64XXX_I2C_ACTION_SEND_RESTART, 101 MV64XXX_I2C_ACTION_SEND_ADDR_1, 102 MV64XXX_I2C_ACTION_SEND_ADDR_2, 103 MV64XXX_I2C_ACTION_SEND_DATA, 104 MV64XXX_I2C_ACTION_RCV_DATA, 105 MV64XXX_I2C_ACTION_RCV_DATA_STOP, 106 MV64XXX_I2C_ACTION_SEND_STOP, 107 }; 108 109 struct mv64xxx_i2c_regs { 110 u8 addr; 111 u8 ext_addr; 112 u8 data; 113 u8 control; 114 u8 status; 115 u8 clock; 116 u8 soft_reset; 117 }; 118 119 struct mv64xxx_i2c_data { 120 struct i2c_msg *msgs; 121 int num_msgs; 122 int irq; 123 u32 state; 124 u32 action; 125 u32 aborting; 126 u32 cntl_bits; 127 void __iomem *reg_base; 128 struct mv64xxx_i2c_regs reg_offsets; 129 u32 addr1; 130 u32 addr2; 131 u32 bytes_left; 132 u32 byte_posn; 133 u32 send_stop; 134 u32 block; 135 int rc; 136 u32 freq_m; 137 u32 freq_n; 138 struct clk *clk; 139 struct clk *reg_clk; 140 wait_queue_head_t waitq; 141 spinlock_t lock; 142 struct i2c_msg *msg; 143 struct i2c_adapter adapter; 144 bool offload_enabled; 145 /* 5us delay in order to avoid repeated start timing violation */ 146 bool errata_delay; 147 struct reset_control *rstc; 148 bool irq_clear_inverted; 149 /* Clk div is 2 to the power n, not 2 to the power n + 1 */ 150 bool clk_n_base_0; 151 struct i2c_bus_recovery_info rinfo; 152 }; 153 154 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { 155 .addr = 0x00, 156 .ext_addr = 0x10, 157 .data = 0x04, 158 .control = 0x08, 159 .status = 0x0c, 160 .clock = 0x0c, 161 .soft_reset = 0x1c, 162 }; 163 164 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = { 165 .addr = 0x00, 166 .ext_addr = 0x04, 167 .data = 0x08, 168 .control = 0x0c, 169 .status = 0x10, 170 .clock = 0x14, 171 .soft_reset = 0x18, 172 }; 173 174 static void 175 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, 176 struct i2c_msg *msg) 177 { 178 u32 dir = 0; 179 180 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | 181 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; 182 183 if (msg->flags & I2C_M_RD) 184 dir = 1; 185 186 if (msg->flags & I2C_M_TEN) { 187 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; 188 drv_data->addr2 = (u32)msg->addr & 0xff; 189 } else { 190 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir; 191 drv_data->addr2 = 0; 192 } 193 } 194 195 /* 196 ***************************************************************************** 197 * 198 * Finite State Machine & Interrupt Routines 199 * 200 ***************************************************************************** 201 */ 202 203 /* Reset hardware and initialize FSM */ 204 static void 205 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 206 { 207 if (drv_data->offload_enabled) { 208 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 209 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); 210 writel(0, drv_data->reg_base + 211 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 212 writel(0, drv_data->reg_base + 213 MV64XXX_I2C_REG_BRIDGE_INTR_MASK); 214 } 215 216 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); 217 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), 218 drv_data->reg_base + drv_data->reg_offsets.clock); 219 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); 220 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); 221 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 222 drv_data->reg_base + drv_data->reg_offsets.control); 223 drv_data->state = MV64XXX_I2C_STATE_IDLE; 224 } 225 226 static void 227 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) 228 { 229 /* 230 * If state is idle, then this is likely the remnants of an old 231 * operation that driver has given up on or the user has killed. 232 * If so, issue the stop condition and go to idle. 233 */ 234 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { 235 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 236 return; 237 } 238 239 /* The status from the ctlr [mostly] tells us what to do next */ 240 switch (status) { 241 /* Start condition interrupt */ 242 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ 243 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ 244 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 245 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 246 break; 247 248 /* Performing a write */ 249 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ 250 if (drv_data->msg->flags & I2C_M_TEN) { 251 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 252 drv_data->state = 253 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 254 break; 255 } 256 fallthrough; 257 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ 258 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ 259 if ((drv_data->bytes_left == 0) 260 || (drv_data->aborting 261 && (drv_data->byte_posn != 0))) { 262 if (drv_data->send_stop || drv_data->aborting) { 263 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 264 drv_data->state = MV64XXX_I2C_STATE_IDLE; 265 } else { 266 drv_data->action = 267 MV64XXX_I2C_ACTION_SEND_RESTART; 268 drv_data->state = 269 MV64XXX_I2C_STATE_WAITING_FOR_RESTART; 270 } 271 } else { 272 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 273 drv_data->state = 274 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 275 drv_data->bytes_left--; 276 } 277 break; 278 279 /* Performing a read */ 280 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ 281 if (drv_data->msg->flags & I2C_M_TEN) { 282 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 283 drv_data->state = 284 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 285 break; 286 } 287 fallthrough; 288 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ 289 if (drv_data->bytes_left == 0) { 290 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 291 drv_data->state = MV64XXX_I2C_STATE_IDLE; 292 break; 293 } 294 fallthrough; 295 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ 296 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) 297 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 298 else { 299 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; 300 drv_data->bytes_left--; 301 } 302 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 303 304 if ((drv_data->bytes_left == 1) || drv_data->aborting) 305 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; 306 break; 307 308 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ 309 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; 310 drv_data->state = MV64XXX_I2C_STATE_IDLE; 311 break; 312 313 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ 314 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ 315 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ 316 /* Doesn't seem to be a device at other end */ 317 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 318 drv_data->state = MV64XXX_I2C_STATE_IDLE; 319 drv_data->rc = -ENXIO; 320 break; 321 322 default: 323 dev_err(&drv_data->adapter.dev, 324 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " 325 "status: 0x%x, addr: 0x%x, flags: 0x%x\n", 326 drv_data->state, status, drv_data->msg->addr, 327 drv_data->msg->flags); 328 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 329 mv64xxx_i2c_hw_init(drv_data); 330 i2c_recover_bus(&drv_data->adapter); 331 drv_data->rc = -EAGAIN; 332 } 333 } 334 335 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) 336 { 337 drv_data->msg = drv_data->msgs; 338 drv_data->byte_posn = 0; 339 drv_data->bytes_left = drv_data->msg->len; 340 drv_data->aborting = 0; 341 drv_data->rc = 0; 342 343 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs); 344 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 345 drv_data->reg_base + drv_data->reg_offsets.control); 346 } 347 348 static void 349 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) 350 { 351 switch(drv_data->action) { 352 case MV64XXX_I2C_ACTION_SEND_RESTART: 353 /* We should only get here if we have further messages */ 354 BUG_ON(drv_data->num_msgs == 0); 355 356 drv_data->msgs++; 357 drv_data->num_msgs--; 358 mv64xxx_i2c_send_start(drv_data); 359 360 if (drv_data->errata_delay) 361 udelay(5); 362 363 /* 364 * We're never at the start of the message here, and by this 365 * time it's already too late to do any protocol mangling. 366 * Thankfully, do not advertise support for that feature. 367 */ 368 drv_data->send_stop = drv_data->num_msgs == 1; 369 break; 370 371 case MV64XXX_I2C_ACTION_CONTINUE: 372 writel(drv_data->cntl_bits, 373 drv_data->reg_base + drv_data->reg_offsets.control); 374 break; 375 376 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 377 writel(drv_data->addr1, 378 drv_data->reg_base + drv_data->reg_offsets.data); 379 writel(drv_data->cntl_bits, 380 drv_data->reg_base + drv_data->reg_offsets.control); 381 break; 382 383 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 384 writel(drv_data->addr2, 385 drv_data->reg_base + drv_data->reg_offsets.data); 386 writel(drv_data->cntl_bits, 387 drv_data->reg_base + drv_data->reg_offsets.control); 388 break; 389 390 case MV64XXX_I2C_ACTION_SEND_DATA: 391 writel(drv_data->msg->buf[drv_data->byte_posn++], 392 drv_data->reg_base + drv_data->reg_offsets.data); 393 writel(drv_data->cntl_bits, 394 drv_data->reg_base + drv_data->reg_offsets.control); 395 break; 396 397 case MV64XXX_I2C_ACTION_RCV_DATA: 398 drv_data->msg->buf[drv_data->byte_posn++] = 399 readl(drv_data->reg_base + drv_data->reg_offsets.data); 400 writel(drv_data->cntl_bits, 401 drv_data->reg_base + drv_data->reg_offsets.control); 402 break; 403 404 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 405 drv_data->msg->buf[drv_data->byte_posn++] = 406 readl(drv_data->reg_base + drv_data->reg_offsets.data); 407 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 408 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 409 drv_data->reg_base + drv_data->reg_offsets.control); 410 drv_data->block = 0; 411 if (drv_data->errata_delay) 412 udelay(5); 413 414 wake_up(&drv_data->waitq); 415 break; 416 417 case MV64XXX_I2C_ACTION_INVALID: 418 default: 419 dev_err(&drv_data->adapter.dev, 420 "mv64xxx_i2c_do_action: Invalid action: %d\n", 421 drv_data->action); 422 drv_data->rc = -EIO; 423 fallthrough; 424 case MV64XXX_I2C_ACTION_SEND_STOP: 425 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 426 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 427 drv_data->reg_base + drv_data->reg_offsets.control); 428 drv_data->block = 0; 429 wake_up(&drv_data->waitq); 430 break; 431 } 432 } 433 434 static void 435 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data, 436 struct i2c_msg *msg) 437 { 438 u32 buf[2]; 439 440 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO); 441 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI); 442 443 memcpy(msg->buf, buf, msg->len); 444 } 445 446 static int 447 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data) 448 { 449 u32 cause, status; 450 451 cause = readl(drv_data->reg_base + 452 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 453 if (!cause) 454 return IRQ_NONE; 455 456 status = readl(drv_data->reg_base + 457 MV64XXX_I2C_REG_BRIDGE_STATUS); 458 459 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) { 460 drv_data->rc = -EIO; 461 goto out; 462 } 463 464 drv_data->rc = 0; 465 466 /* 467 * Transaction is a one message read transaction, read data 468 * for this message. 469 */ 470 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) { 471 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs); 472 drv_data->msgs++; 473 drv_data->num_msgs--; 474 } 475 /* 476 * Transaction is a two messages write/read transaction, read 477 * data for the second (read) message. 478 */ 479 else if (drv_data->num_msgs == 2 && 480 !(drv_data->msgs[0].flags & I2C_M_RD) && 481 drv_data->msgs[1].flags & I2C_M_RD) { 482 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1); 483 drv_data->msgs += 2; 484 drv_data->num_msgs -= 2; 485 } 486 487 out: 488 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 489 writel(0, drv_data->reg_base + 490 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); 491 drv_data->block = 0; 492 493 wake_up(&drv_data->waitq); 494 495 return IRQ_HANDLED; 496 } 497 498 static irqreturn_t 499 mv64xxx_i2c_intr(int irq, void *dev_id) 500 { 501 struct mv64xxx_i2c_data *drv_data = dev_id; 502 u32 status; 503 irqreturn_t rc = IRQ_NONE; 504 505 spin_lock(&drv_data->lock); 506 507 if (drv_data->offload_enabled) 508 rc = mv64xxx_i2c_intr_offload(drv_data); 509 510 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & 511 MV64XXX_I2C_REG_CONTROL_IFLG) { 512 status = readl(drv_data->reg_base + drv_data->reg_offsets.status); 513 mv64xxx_i2c_fsm(drv_data, status); 514 mv64xxx_i2c_do_action(drv_data); 515 516 if (drv_data->irq_clear_inverted) 517 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG, 518 drv_data->reg_base + drv_data->reg_offsets.control); 519 520 rc = IRQ_HANDLED; 521 } 522 spin_unlock(&drv_data->lock); 523 524 return rc; 525 } 526 527 /* 528 ***************************************************************************** 529 * 530 * I2C Msg Execution Routines 531 * 532 ***************************************************************************** 533 */ 534 static void 535 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 536 { 537 long time_left; 538 unsigned long flags; 539 char abort = 0; 540 541 time_left = wait_event_timeout(drv_data->waitq, 542 !drv_data->block, drv_data->adapter.timeout); 543 544 spin_lock_irqsave(&drv_data->lock, flags); 545 if (!time_left) { /* Timed out */ 546 drv_data->rc = -ETIMEDOUT; 547 abort = 1; 548 } else if (time_left < 0) { /* Interrupted/Error */ 549 drv_data->rc = time_left; /* errno value */ 550 abort = 1; 551 } 552 553 if (abort && drv_data->block) { 554 drv_data->aborting = 1; 555 spin_unlock_irqrestore(&drv_data->lock, flags); 556 557 time_left = wait_event_timeout(drv_data->waitq, 558 !drv_data->block, drv_data->adapter.timeout); 559 560 if ((time_left <= 0) && drv_data->block) { 561 drv_data->state = MV64XXX_I2C_STATE_IDLE; 562 dev_err(&drv_data->adapter.dev, 563 "mv64xxx: I2C bus locked, block: %d, " 564 "time_left: %d\n", drv_data->block, 565 (int)time_left); 566 mv64xxx_i2c_hw_init(drv_data); 567 i2c_recover_bus(&drv_data->adapter); 568 } 569 } else 570 spin_unlock_irqrestore(&drv_data->lock, flags); 571 } 572 573 static int 574 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 575 int is_last) 576 { 577 unsigned long flags; 578 579 spin_lock_irqsave(&drv_data->lock, flags); 580 581 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; 582 583 drv_data->send_stop = is_last; 584 drv_data->block = 1; 585 mv64xxx_i2c_send_start(drv_data); 586 spin_unlock_irqrestore(&drv_data->lock, flags); 587 588 mv64xxx_i2c_wait_for_completion(drv_data); 589 return drv_data->rc; 590 } 591 592 static void 593 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data) 594 { 595 struct i2c_msg *msg = drv_data->msgs; 596 u32 buf[2]; 597 598 memcpy(buf, msg->buf, msg->len); 599 600 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); 601 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); 602 } 603 604 static int 605 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data) 606 { 607 struct i2c_msg *msgs = drv_data->msgs; 608 int num = drv_data->num_msgs; 609 unsigned long ctrl_reg; 610 unsigned long flags; 611 612 spin_lock_irqsave(&drv_data->lock, flags); 613 614 /* Build transaction */ 615 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE | 616 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT); 617 618 if (msgs[0].flags & I2C_M_TEN) 619 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT; 620 621 /* Single write message transaction */ 622 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) { 623 size_t len = msgs[0].len - 1; 624 625 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR | 626 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT); 627 mv64xxx_i2c_prepare_tx(drv_data); 628 } 629 /* Single read message transaction */ 630 else if (num == 1 && msgs[0].flags & I2C_M_RD) { 631 size_t len = msgs[0].len - 1; 632 633 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD | 634 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT); 635 } 636 /* 637 * Transaction with one write and one read message. This is 638 * guaranteed by the mv64xx_i2c_can_offload() checks. 639 */ 640 else if (num == 2) { 641 size_t lentx = msgs[0].len - 1; 642 size_t lenrx = msgs[1].len - 1; 643 644 ctrl_reg |= 645 MV64XXX_I2C_BRIDGE_CONTROL_RD | 646 MV64XXX_I2C_BRIDGE_CONTROL_WR | 647 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) | 648 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) | 649 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START; 650 mv64xxx_i2c_prepare_tx(drv_data); 651 } 652 653 /* Execute transaction */ 654 drv_data->block = 1; 655 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 656 spin_unlock_irqrestore(&drv_data->lock, flags); 657 658 mv64xxx_i2c_wait_for_completion(drv_data); 659 660 return drv_data->rc; 661 } 662 663 static bool 664 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg) 665 { 666 return msg->len <= 8 && msg->len >= 1; 667 } 668 669 static bool 670 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data) 671 { 672 struct i2c_msg *msgs = drv_data->msgs; 673 int num = drv_data->num_msgs; 674 675 if (!drv_data->offload_enabled) 676 return false; 677 678 /* 679 * We can offload a transaction consisting of a single 680 * message, as long as the message has a length between 1 and 681 * 8 bytes. 682 */ 683 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs)) 684 return true; 685 686 /* 687 * We can offload a transaction consisting of two messages, if 688 * the first is a write and a second is a read, and both have 689 * a length between 1 and 8 bytes. 690 */ 691 if (num == 2 && 692 mv64xxx_i2c_valid_offload_sz(msgs) && 693 mv64xxx_i2c_valid_offload_sz(msgs + 1) && 694 !(msgs[0].flags & I2C_M_RD) && 695 msgs[1].flags & I2C_M_RD) 696 return true; 697 698 return false; 699 } 700 701 /* 702 ***************************************************************************** 703 * 704 * I2C Core Support Routines (Interface to higher level I2C code) 705 * 706 ***************************************************************************** 707 */ 708 static u32 709 mv64xxx_i2c_functionality(struct i2c_adapter *adap) 710 { 711 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 712 } 713 714 static int 715 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 716 { 717 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 718 int rc, ret = num; 719 720 BUG_ON(drv_data->msgs != NULL); 721 drv_data->msgs = msgs; 722 drv_data->num_msgs = num; 723 724 if (mv64xxx_i2c_can_offload(drv_data)) 725 rc = mv64xxx_i2c_offload_xfer(drv_data); 726 else 727 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1); 728 729 if (rc < 0) 730 ret = rc; 731 732 drv_data->num_msgs = 0; 733 drv_data->msgs = NULL; 734 735 return ret; 736 } 737 738 static const struct i2c_algorithm mv64xxx_i2c_algo = { 739 .master_xfer = mv64xxx_i2c_xfer, 740 .functionality = mv64xxx_i2c_functionality, 741 }; 742 743 /* 744 ***************************************************************************** 745 * 746 * Driver Interface & Early Init Routines 747 * 748 ***************************************************************************** 749 */ 750 static const struct of_device_id mv64xxx_i2c_of_match_table[] = { 751 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i}, 752 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i}, 753 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 754 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 755 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 756 {} 757 }; 758 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); 759 760 #ifdef CONFIG_OF 761 static int 762 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data, 763 const int tclk, const int n, const int m) 764 { 765 if (drv_data->clk_n_base_0) 766 return tclk / (10 * (m + 1) * (1 << n)); 767 else 768 return tclk / (10 * (m + 1) * (2 << n)); 769 } 770 771 static bool 772 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data, 773 const u32 req_freq, const u32 tclk) 774 { 775 int freq, delta, best_delta = INT_MAX; 776 int m, n; 777 778 for (n = 0; n <= 7; n++) 779 for (m = 0; m <= 15; m++) { 780 freq = mv64xxx_calc_freq(drv_data, tclk, n, m); 781 delta = req_freq - freq; 782 if (delta >= 0 && delta < best_delta) { 783 drv_data->freq_m = m; 784 drv_data->freq_n = n; 785 best_delta = delta; 786 } 787 if (best_delta == 0) 788 return true; 789 } 790 if (best_delta == INT_MAX) 791 return false; 792 return true; 793 } 794 795 static int 796 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 797 struct device *dev) 798 { 799 const struct of_device_id *device; 800 struct device_node *np = dev->of_node; 801 u32 bus_freq, tclk; 802 int rc = 0; 803 804 /* CLK is mandatory when using DT to describe the i2c bus. We 805 * need to know tclk in order to calculate bus clock 806 * factors. 807 */ 808 if (IS_ERR(drv_data->clk)) { 809 rc = -ENODEV; 810 goto out; 811 } 812 tclk = clk_get_rate(drv_data->clk); 813 814 if (of_property_read_u32(np, "clock-frequency", &bus_freq)) 815 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */ 816 817 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") || 818 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c")) 819 drv_data->clk_n_base_0 = true; 820 821 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) { 822 rc = -EINVAL; 823 goto out; 824 } 825 826 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 827 if (IS_ERR(drv_data->rstc)) { 828 rc = PTR_ERR(drv_data->rstc); 829 goto out; 830 } 831 reset_control_deassert(drv_data->rstc); 832 833 /* Its not yet defined how timeouts will be specified in device tree. 834 * So hard code the value to 1 second. 835 */ 836 drv_data->adapter.timeout = HZ; 837 838 device = of_match_device(mv64xxx_i2c_of_match_table, dev); 839 if (!device) 840 return -ENODEV; 841 842 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); 843 844 /* 845 * For controllers embedded in new SoCs activate the 846 * Transaction Generator support and the errata fix. 847 */ 848 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) { 849 drv_data->offload_enabled = true; 850 /* The delay is only needed in standard mode (100kHz) */ 851 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ) 852 drv_data->errata_delay = true; 853 } 854 855 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) { 856 drv_data->offload_enabled = false; 857 /* The delay is only needed in standard mode (100kHz) */ 858 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ) 859 drv_data->errata_delay = true; 860 } 861 862 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c")) 863 drv_data->irq_clear_inverted = true; 864 865 out: 866 return rc; 867 } 868 #else /* CONFIG_OF */ 869 static int 870 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 871 struct device *dev) 872 { 873 return -ENODEV; 874 } 875 #endif /* CONFIG_OF */ 876 877 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data, 878 struct device *dev) 879 { 880 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo; 881 882 rinfo->pinctrl = devm_pinctrl_get(dev); 883 if (IS_ERR(rinfo->pinctrl)) { 884 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) 885 return -EPROBE_DEFER; 886 dev_info(dev, "can't get pinctrl, bus recovery not supported\n"); 887 return PTR_ERR(rinfo->pinctrl); 888 } else if (!rinfo->pinctrl) { 889 return -ENODEV; 890 } 891 892 drv_data->adapter.bus_recovery_info = rinfo; 893 return 0; 894 } 895 896 static int 897 mv64xxx_i2c_probe(struct platform_device *pd) 898 { 899 struct mv64xxx_i2c_data *drv_data; 900 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); 901 int rc; 902 903 if ((!pdata && !pd->dev.of_node)) 904 return -ENODEV; 905 906 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data), 907 GFP_KERNEL); 908 if (!drv_data) 909 return -ENOMEM; 910 911 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0); 912 if (IS_ERR(drv_data->reg_base)) 913 return PTR_ERR(drv_data->reg_base); 914 915 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 916 sizeof(drv_data->adapter.name)); 917 918 init_waitqueue_head(&drv_data->waitq); 919 spin_lock_init(&drv_data->lock); 920 921 /* Not all platforms have clocks */ 922 drv_data->clk = devm_clk_get(&pd->dev, NULL); 923 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER) 924 return -EPROBE_DEFER; 925 if (!IS_ERR(drv_data->clk)) 926 clk_prepare_enable(drv_data->clk); 927 928 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg"); 929 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER) 930 return -EPROBE_DEFER; 931 if (!IS_ERR(drv_data->reg_clk)) 932 clk_prepare_enable(drv_data->reg_clk); 933 934 drv_data->irq = platform_get_irq(pd, 0); 935 936 if (pdata) { 937 drv_data->freq_m = pdata->freq_m; 938 drv_data->freq_n = pdata->freq_n; 939 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); 940 drv_data->offload_enabled = false; 941 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets)); 942 } else if (pd->dev.of_node) { 943 rc = mv64xxx_of_config(drv_data, &pd->dev); 944 if (rc) 945 goto exit_clk; 946 } 947 if (drv_data->irq < 0) { 948 rc = drv_data->irq; 949 goto exit_reset; 950 } 951 952 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev); 953 if (rc == -EPROBE_DEFER) 954 goto exit_reset; 955 956 drv_data->adapter.dev.parent = &pd->dev; 957 drv_data->adapter.algo = &mv64xxx_i2c_algo; 958 drv_data->adapter.owner = THIS_MODULE; 959 drv_data->adapter.class = I2C_CLASS_DEPRECATED; 960 drv_data->adapter.nr = pd->id; 961 drv_data->adapter.dev.of_node = pd->dev.of_node; 962 platform_set_drvdata(pd, drv_data); 963 i2c_set_adapdata(&drv_data->adapter, drv_data); 964 965 mv64xxx_i2c_hw_init(drv_data); 966 967 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 968 MV64XXX_I2C_CTLR_NAME, drv_data); 969 if (rc) { 970 dev_err(&drv_data->adapter.dev, 971 "mv64xxx: Can't register intr handler irq%d: %d\n", 972 drv_data->irq, rc); 973 goto exit_reset; 974 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { 975 dev_err(&drv_data->adapter.dev, 976 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 977 goto exit_free_irq; 978 } 979 980 return 0; 981 982 exit_free_irq: 983 free_irq(drv_data->irq, drv_data); 984 exit_reset: 985 reset_control_assert(drv_data->rstc); 986 exit_clk: 987 clk_disable_unprepare(drv_data->reg_clk); 988 clk_disable_unprepare(drv_data->clk); 989 990 return rc; 991 } 992 993 static int 994 mv64xxx_i2c_remove(struct platform_device *dev) 995 { 996 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); 997 998 i2c_del_adapter(&drv_data->adapter); 999 free_irq(drv_data->irq, drv_data); 1000 reset_control_assert(drv_data->rstc); 1001 clk_disable_unprepare(drv_data->reg_clk); 1002 clk_disable_unprepare(drv_data->clk); 1003 1004 return 0; 1005 } 1006 1007 #ifdef CONFIG_PM 1008 static int mv64xxx_i2c_resume(struct device *dev) 1009 { 1010 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); 1011 1012 mv64xxx_i2c_hw_init(drv_data); 1013 1014 return 0; 1015 } 1016 1017 static const struct dev_pm_ops mv64xxx_i2c_pm = { 1018 .resume = mv64xxx_i2c_resume, 1019 }; 1020 1021 #define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm) 1022 #else 1023 #define mv64xxx_i2c_pm_ops NULL 1024 #endif 1025 1026 static struct platform_driver mv64xxx_i2c_driver = { 1027 .probe = mv64xxx_i2c_probe, 1028 .remove = mv64xxx_i2c_remove, 1029 .driver = { 1030 .name = MV64XXX_I2C_CTLR_NAME, 1031 .pm = mv64xxx_i2c_pm_ops, 1032 .of_match_table = mv64xxx_i2c_of_match_table, 1033 }, 1034 }; 1035 1036 module_platform_driver(mv64xxx_i2c_driver); 1037 1038 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 1039 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); 1040 MODULE_LICENSE("GPL"); 1041