1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_HANDSHAKE_RST 0x0020 42 #define I2C_FIFO_ADDR_CLR 0x0001 43 #define I2C_DELAY_LEN 0x0002 44 #define I2C_TIME_CLR_VALUE 0x0000 45 #define I2C_TIME_DEFAULT_VALUE 0x0003 46 #define I2C_WRRD_TRANAC_VALUE 0x0002 47 #define I2C_RD_TRANAC_VALUE 0x0001 48 #define I2C_SCL_MIS_COMP_VALUE 0x0000 49 #define I2C_CHN_CLR_FLAG 0x0000 50 51 #define I2C_DMA_CON_TX 0x0000 52 #define I2C_DMA_CON_RX 0x0001 53 #define I2C_DMA_ASYNC_MODE 0x0004 54 #define I2C_DMA_SKIP_CONFIG 0x0010 55 #define I2C_DMA_DIR_CHANGE 0x0200 56 #define I2C_DMA_START_EN 0x0001 57 #define I2C_DMA_INT_FLAG_NONE 0x0000 58 #define I2C_DMA_CLR_FLAG 0x0000 59 #define I2C_DMA_WARM_RST 0x0001 60 #define I2C_DMA_HARD_RST 0x0002 61 #define I2C_DMA_HANDSHAKE_RST 0x0004 62 63 #define MAX_SAMPLE_CNT_DIV 8 64 #define MAX_STEP_CNT_DIV 64 65 #define MAX_CLOCK_DIV 256 66 #define MAX_HS_STEP_CNT_DIV 8 67 #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 68 #define I2C_FAST_MODE_BUFFER (300 / 2) 69 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 70 71 #define I2C_CONTROL_RS (0x1 << 1) 72 #define I2C_CONTROL_DMA_EN (0x1 << 2) 73 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 74 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 75 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 77 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 78 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 79 #define I2C_CONTROL_WRAPPER (0x1 << 0) 80 81 #define I2C_DRV_NAME "i2c-mt65xx" 82 83 enum DMA_REGS_OFFSET { 84 OFFSET_INT_FLAG = 0x0, 85 OFFSET_INT_EN = 0x04, 86 OFFSET_EN = 0x08, 87 OFFSET_RST = 0x0c, 88 OFFSET_CON = 0x18, 89 OFFSET_TX_MEM_ADDR = 0x1c, 90 OFFSET_RX_MEM_ADDR = 0x20, 91 OFFSET_TX_LEN = 0x24, 92 OFFSET_RX_LEN = 0x28, 93 OFFSET_TX_4G_MODE = 0x54, 94 OFFSET_RX_4G_MODE = 0x58, 95 }; 96 97 enum i2c_trans_st_rs { 98 I2C_TRANS_STOP = 0, 99 I2C_TRANS_REPEATED_START, 100 }; 101 102 enum mtk_trans_op { 103 I2C_MASTER_WR = 1, 104 I2C_MASTER_RD, 105 I2C_MASTER_WRRD, 106 }; 107 108 enum I2C_REGS_OFFSET { 109 OFFSET_DATA_PORT, 110 OFFSET_SLAVE_ADDR, 111 OFFSET_INTR_MASK, 112 OFFSET_INTR_STAT, 113 OFFSET_CONTROL, 114 OFFSET_TRANSFER_LEN, 115 OFFSET_TRANSAC_LEN, 116 OFFSET_DELAY_LEN, 117 OFFSET_TIMING, 118 OFFSET_START, 119 OFFSET_EXT_CONF, 120 OFFSET_FIFO_STAT, 121 OFFSET_FIFO_THRESH, 122 OFFSET_FIFO_ADDR_CLR, 123 OFFSET_IO_CONFIG, 124 OFFSET_RSV_DEBUG, 125 OFFSET_HS, 126 OFFSET_SOFTRESET, 127 OFFSET_DCM_EN, 128 OFFSET_PATH_DIR, 129 OFFSET_DEBUGSTAT, 130 OFFSET_DEBUGCTRL, 131 OFFSET_TRANSFER_LEN_AUX, 132 OFFSET_CLOCK_DIV, 133 OFFSET_LTIMING, 134 OFFSET_SCL_HIGH_LOW_RATIO, 135 OFFSET_HS_SCL_HIGH_LOW_RATIO, 136 OFFSET_SCL_MIS_COMP_POINT, 137 OFFSET_STA_STO_AC_TIMING, 138 OFFSET_HS_STA_STO_AC_TIMING, 139 OFFSET_SDA_TIMING, 140 }; 141 142 static const u16 mt_i2c_regs_v1[] = { 143 [OFFSET_DATA_PORT] = 0x0, 144 [OFFSET_SLAVE_ADDR] = 0x4, 145 [OFFSET_INTR_MASK] = 0x8, 146 [OFFSET_INTR_STAT] = 0xc, 147 [OFFSET_CONTROL] = 0x10, 148 [OFFSET_TRANSFER_LEN] = 0x14, 149 [OFFSET_TRANSAC_LEN] = 0x18, 150 [OFFSET_DELAY_LEN] = 0x1c, 151 [OFFSET_TIMING] = 0x20, 152 [OFFSET_START] = 0x24, 153 [OFFSET_EXT_CONF] = 0x28, 154 [OFFSET_FIFO_STAT] = 0x30, 155 [OFFSET_FIFO_THRESH] = 0x34, 156 [OFFSET_FIFO_ADDR_CLR] = 0x38, 157 [OFFSET_IO_CONFIG] = 0x40, 158 [OFFSET_RSV_DEBUG] = 0x44, 159 [OFFSET_HS] = 0x48, 160 [OFFSET_SOFTRESET] = 0x50, 161 [OFFSET_DCM_EN] = 0x54, 162 [OFFSET_PATH_DIR] = 0x60, 163 [OFFSET_DEBUGSTAT] = 0x64, 164 [OFFSET_DEBUGCTRL] = 0x68, 165 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 166 [OFFSET_CLOCK_DIV] = 0x70, 167 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 168 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 169 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 170 [OFFSET_STA_STO_AC_TIMING] = 0x80, 171 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 172 [OFFSET_SDA_TIMING] = 0x88, 173 }; 174 175 static const u16 mt_i2c_regs_v2[] = { 176 [OFFSET_DATA_PORT] = 0x0, 177 [OFFSET_SLAVE_ADDR] = 0x4, 178 [OFFSET_INTR_MASK] = 0x8, 179 [OFFSET_INTR_STAT] = 0xc, 180 [OFFSET_CONTROL] = 0x10, 181 [OFFSET_TRANSFER_LEN] = 0x14, 182 [OFFSET_TRANSAC_LEN] = 0x18, 183 [OFFSET_DELAY_LEN] = 0x1c, 184 [OFFSET_TIMING] = 0x20, 185 [OFFSET_START] = 0x24, 186 [OFFSET_EXT_CONF] = 0x28, 187 [OFFSET_LTIMING] = 0x2c, 188 [OFFSET_HS] = 0x30, 189 [OFFSET_IO_CONFIG] = 0x34, 190 [OFFSET_FIFO_ADDR_CLR] = 0x38, 191 [OFFSET_SDA_TIMING] = 0x3c, 192 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 193 [OFFSET_CLOCK_DIV] = 0x48, 194 [OFFSET_SOFTRESET] = 0x50, 195 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 196 [OFFSET_DEBUGSTAT] = 0xe0, 197 [OFFSET_DEBUGCTRL] = 0xe8, 198 [OFFSET_FIFO_STAT] = 0xf4, 199 [OFFSET_FIFO_THRESH] = 0xf8, 200 [OFFSET_DCM_EN] = 0xf88, 201 }; 202 203 struct mtk_i2c_compatible { 204 const struct i2c_adapter_quirks *quirks; 205 const u16 *regs; 206 unsigned char pmic_i2c: 1; 207 unsigned char dcm: 1; 208 unsigned char auto_restart: 1; 209 unsigned char aux_len_reg: 1; 210 unsigned char timing_adjust: 1; 211 unsigned char dma_sync: 1; 212 unsigned char ltiming_adjust: 1; 213 unsigned char apdma_sync: 1; 214 unsigned char max_dma_support; 215 }; 216 217 struct mtk_i2c_ac_timing { 218 u16 htiming; 219 u16 ltiming; 220 u16 hs; 221 u16 ext; 222 u16 inter_clk_div; 223 u16 scl_hl_ratio; 224 u16 hs_scl_hl_ratio; 225 u16 sta_stop; 226 u16 hs_sta_stop; 227 u16 sda_timing; 228 }; 229 230 struct mtk_i2c { 231 struct i2c_adapter adap; /* i2c host adapter */ 232 struct device *dev; 233 struct completion msg_complete; 234 235 /* set in i2c probe */ 236 void __iomem *base; /* i2c base addr */ 237 void __iomem *pdmabase; /* dma base address*/ 238 struct clk *clk_main; /* main clock for i2c bus */ 239 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 240 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 241 struct clk *clk_arb; /* Arbitrator clock for i2c */ 242 bool have_pmic; /* can use i2c pins from PMIC */ 243 bool use_push_pull; /* IO config push-pull mode */ 244 245 u16 irq_stat; /* interrupt status */ 246 unsigned int clk_src_div; 247 unsigned int speed_hz; /* The speed in transfer */ 248 enum mtk_trans_op op; 249 u16 timing_reg; 250 u16 high_speed_reg; 251 u16 ltiming_reg; 252 unsigned char auto_restart; 253 bool ignore_restart_irq; 254 struct mtk_i2c_ac_timing ac_timing; 255 const struct mtk_i2c_compatible *dev_comp; 256 }; 257 258 /** 259 * struct i2c_spec_values: 260 * @min_low_ns: min LOW period of the SCL clock 261 * @min_su_sta_ns: min set-up time for a repeated START condition 262 * @max_hd_dat_ns: max data hold time 263 * @min_su_dat_ns: min data set-up time 264 */ 265 struct i2c_spec_values { 266 unsigned int min_low_ns; 267 unsigned int min_su_sta_ns; 268 unsigned int max_hd_dat_ns; 269 unsigned int min_su_dat_ns; 270 }; 271 272 static const struct i2c_spec_values standard_mode_spec = { 273 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 274 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 275 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 276 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 277 }; 278 279 static const struct i2c_spec_values fast_mode_spec = { 280 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 281 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 282 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 283 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 284 }; 285 286 static const struct i2c_spec_values fast_mode_plus_spec = { 287 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 288 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 289 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 290 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 291 }; 292 293 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 294 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 295 .max_num_msgs = 1, 296 .max_write_len = 255, 297 .max_read_len = 255, 298 .max_comb_1st_msg_len = 255, 299 .max_comb_2nd_msg_len = 31, 300 }; 301 302 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 303 .max_num_msgs = 255, 304 }; 305 306 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 307 .flags = I2C_AQ_NO_ZERO_LEN, 308 }; 309 310 static const struct mtk_i2c_compatible mt2712_compat = { 311 .regs = mt_i2c_regs_v1, 312 .pmic_i2c = 0, 313 .dcm = 1, 314 .auto_restart = 1, 315 .aux_len_reg = 1, 316 .timing_adjust = 1, 317 .dma_sync = 0, 318 .ltiming_adjust = 0, 319 .apdma_sync = 0, 320 .max_dma_support = 33, 321 }; 322 323 static const struct mtk_i2c_compatible mt6577_compat = { 324 .quirks = &mt6577_i2c_quirks, 325 .regs = mt_i2c_regs_v1, 326 .pmic_i2c = 0, 327 .dcm = 1, 328 .auto_restart = 0, 329 .aux_len_reg = 0, 330 .timing_adjust = 0, 331 .dma_sync = 0, 332 .ltiming_adjust = 0, 333 .apdma_sync = 0, 334 .max_dma_support = 32, 335 }; 336 337 static const struct mtk_i2c_compatible mt6589_compat = { 338 .quirks = &mt6577_i2c_quirks, 339 .regs = mt_i2c_regs_v1, 340 .pmic_i2c = 1, 341 .dcm = 0, 342 .auto_restart = 0, 343 .aux_len_reg = 0, 344 .timing_adjust = 0, 345 .dma_sync = 0, 346 .ltiming_adjust = 0, 347 .apdma_sync = 0, 348 .max_dma_support = 32, 349 }; 350 351 static const struct mtk_i2c_compatible mt7622_compat = { 352 .quirks = &mt7622_i2c_quirks, 353 .regs = mt_i2c_regs_v1, 354 .pmic_i2c = 0, 355 .dcm = 1, 356 .auto_restart = 1, 357 .aux_len_reg = 1, 358 .timing_adjust = 0, 359 .dma_sync = 0, 360 .ltiming_adjust = 0, 361 .apdma_sync = 0, 362 .max_dma_support = 32, 363 }; 364 365 static const struct mtk_i2c_compatible mt8173_compat = { 366 .regs = mt_i2c_regs_v1, 367 .pmic_i2c = 0, 368 .dcm = 1, 369 .auto_restart = 1, 370 .aux_len_reg = 1, 371 .timing_adjust = 0, 372 .dma_sync = 0, 373 .ltiming_adjust = 0, 374 .apdma_sync = 0, 375 .max_dma_support = 33, 376 }; 377 378 static const struct mtk_i2c_compatible mt8183_compat = { 379 .quirks = &mt8183_i2c_quirks, 380 .regs = mt_i2c_regs_v2, 381 .pmic_i2c = 0, 382 .dcm = 0, 383 .auto_restart = 1, 384 .aux_len_reg = 1, 385 .timing_adjust = 1, 386 .dma_sync = 1, 387 .ltiming_adjust = 1, 388 .apdma_sync = 0, 389 .max_dma_support = 33, 390 }; 391 392 static const struct mtk_i2c_compatible mt8192_compat = { 393 .quirks = &mt8183_i2c_quirks, 394 .regs = mt_i2c_regs_v2, 395 .pmic_i2c = 0, 396 .dcm = 0, 397 .auto_restart = 1, 398 .aux_len_reg = 1, 399 .timing_adjust = 1, 400 .dma_sync = 1, 401 .ltiming_adjust = 1, 402 .apdma_sync = 1, 403 .max_dma_support = 36, 404 }; 405 406 static const struct of_device_id mtk_i2c_of_match[] = { 407 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 408 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 409 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 410 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 411 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 412 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 413 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 414 {} 415 }; 416 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 417 418 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 419 { 420 return readw(i2c->base + i2c->dev_comp->regs[reg]); 421 } 422 423 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 424 enum I2C_REGS_OFFSET reg) 425 { 426 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 427 } 428 429 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 430 { 431 int ret; 432 433 ret = clk_prepare_enable(i2c->clk_dma); 434 if (ret) 435 return ret; 436 437 ret = clk_prepare_enable(i2c->clk_main); 438 if (ret) 439 goto err_main; 440 441 if (i2c->have_pmic) { 442 ret = clk_prepare_enable(i2c->clk_pmic); 443 if (ret) 444 goto err_pmic; 445 } 446 447 if (i2c->clk_arb) { 448 ret = clk_prepare_enable(i2c->clk_arb); 449 if (ret) 450 goto err_arb; 451 } 452 453 return 0; 454 455 err_arb: 456 if (i2c->have_pmic) 457 clk_disable_unprepare(i2c->clk_pmic); 458 err_pmic: 459 clk_disable_unprepare(i2c->clk_main); 460 err_main: 461 clk_disable_unprepare(i2c->clk_dma); 462 463 return ret; 464 } 465 466 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 467 { 468 if (i2c->clk_arb) 469 clk_disable_unprepare(i2c->clk_arb); 470 471 if (i2c->have_pmic) 472 clk_disable_unprepare(i2c->clk_pmic); 473 474 clk_disable_unprepare(i2c->clk_main); 475 clk_disable_unprepare(i2c->clk_dma); 476 } 477 478 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 479 { 480 u16 control_reg; 481 482 if (i2c->dev_comp->dma_sync) { 483 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 484 udelay(10); 485 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 486 udelay(10); 487 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 488 i2c->pdmabase + OFFSET_RST); 489 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 490 OFFSET_SOFTRESET); 491 udelay(10); 492 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 493 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 494 } else { 495 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 496 udelay(50); 497 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 498 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 499 } 500 501 /* Set ioconfig */ 502 if (i2c->use_push_pull) 503 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 504 else 505 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 506 507 if (i2c->dev_comp->dcm) 508 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 509 510 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 511 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 512 if (i2c->dev_comp->ltiming_adjust) 513 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 514 515 if (i2c->dev_comp->timing_adjust) { 516 mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF); 517 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 518 OFFSET_CLOCK_DIV); 519 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 520 OFFSET_SCL_MIS_COMP_POINT); 521 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 522 OFFSET_SDA_TIMING); 523 524 if (i2c->dev_comp->ltiming_adjust) { 525 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 526 OFFSET_TIMING); 527 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 528 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 529 OFFSET_LTIMING); 530 } else { 531 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 532 OFFSET_SCL_HIGH_LOW_RATIO); 533 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 534 OFFSET_HS_SCL_HIGH_LOW_RATIO); 535 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 536 OFFSET_STA_STO_AC_TIMING); 537 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 538 OFFSET_HS_STA_STO_AC_TIMING); 539 } 540 } 541 542 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 543 if (i2c->have_pmic) 544 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 545 546 control_reg = I2C_CONTROL_ACKERR_DET_EN | 547 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 548 if (i2c->dev_comp->dma_sync) 549 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 550 551 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 552 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 553 } 554 555 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 556 { 557 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 558 return &standard_mode_spec; 559 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 560 return &fast_mode_spec; 561 else 562 return &fast_mode_plus_spec; 563 } 564 565 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 566 { 567 if (target_speed > I2C_MAX_FAST_MODE_FREQ) 568 return MAX_HS_STEP_CNT_DIV; 569 else 570 return MAX_STEP_CNT_DIV; 571 } 572 573 /* 574 * Check and Calculate i2c ac-timing 575 * 576 * Hardware design: 577 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 578 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 579 * 580 * Sample_ns is rounded down for xxx_cnt_div would be greater 581 * than the smallest spec. 582 * The sda_timing is chosen as the middle value between 583 * the largest and smallest. 584 */ 585 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 586 unsigned int clk_src, 587 unsigned int check_speed, 588 unsigned int step_cnt, 589 unsigned int sample_cnt) 590 { 591 const struct i2c_spec_values *spec; 592 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 593 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 594 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 595 clk_src); 596 597 if (!i2c->dev_comp->timing_adjust) 598 return 0; 599 600 if (i2c->dev_comp->ltiming_adjust) 601 max_sta_cnt = 0x100; 602 603 spec = mtk_i2c_get_spec(check_speed); 604 605 if (i2c->dev_comp->ltiming_adjust) 606 clk_ns = 1000000000 / clk_src; 607 else 608 clk_ns = sample_ns / 2; 609 610 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); 611 if (su_sta_cnt > max_sta_cnt) 612 return -1; 613 614 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 615 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 616 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 617 if (low_cnt > step_cnt) { 618 high_cnt = 2 * step_cnt - low_cnt; 619 } else { 620 high_cnt = step_cnt; 621 low_cnt = step_cnt; 622 } 623 } else { 624 return -2; 625 } 626 627 sda_max = spec->max_hd_dat_ns / sample_ns; 628 if (sda_max > low_cnt) 629 sda_max = 0; 630 631 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 632 if (sda_min < low_cnt) 633 sda_min = 0; 634 635 if (sda_min > sda_max) 636 return -3; 637 638 if (check_speed > I2C_MAX_FAST_MODE_FREQ) { 639 if (i2c->dev_comp->ltiming_adjust) { 640 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 641 (sample_cnt << 12) | (high_cnt << 8); 642 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 643 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 644 (low_cnt << 9); 645 i2c->ac_timing.ext &= ~GENMASK(7, 1); 646 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 647 } else { 648 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 649 (high_cnt << 6) | low_cnt; 650 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 651 su_sta_cnt; 652 } 653 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 654 i2c->ac_timing.sda_timing |= (1 << 12) | 655 ((sda_max + sda_min) / 2) << 6; 656 } else { 657 if (i2c->dev_comp->ltiming_adjust) { 658 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 659 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 660 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 661 } else { 662 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 663 (high_cnt << 6) | low_cnt; 664 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 665 su_sta_cnt; 666 } 667 668 i2c->ac_timing.sda_timing = (1 << 12) | 669 (sda_max + sda_min) / 2; 670 } 671 672 return 0; 673 } 674 675 /* 676 * Calculate i2c port speed 677 * 678 * Hardware design: 679 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 680 * clock_div: fixed in hardware, but may be various in different SoCs 681 * 682 * The calculation want to pick the highest bus frequency that is still 683 * less than or equal to i2c->speed_hz. The calculation try to get 684 * sample_cnt and step_cn 685 */ 686 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 687 unsigned int target_speed, 688 unsigned int *timing_step_cnt, 689 unsigned int *timing_sample_cnt) 690 { 691 unsigned int step_cnt; 692 unsigned int sample_cnt; 693 unsigned int max_step_cnt; 694 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 695 unsigned int base_step_cnt; 696 unsigned int opt_div; 697 unsigned int best_mul; 698 unsigned int cnt_mul; 699 int ret = -EINVAL; 700 701 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 702 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 703 704 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 705 base_step_cnt = max_step_cnt; 706 /* Find the best combination */ 707 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 708 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 709 710 /* Search for the best pair (sample_cnt, step_cnt) with 711 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 712 * 0 < step_cnt < max_step_cnt 713 * sample_cnt * step_cnt >= opt_div 714 * optimizing for sample_cnt * step_cnt being minimal 715 */ 716 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 717 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 718 cnt_mul = step_cnt * sample_cnt; 719 if (step_cnt > max_step_cnt) 720 continue; 721 722 if (cnt_mul < best_mul) { 723 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 724 target_speed, step_cnt - 1, sample_cnt - 1); 725 if (ret) 726 continue; 727 728 best_mul = cnt_mul; 729 base_sample_cnt = sample_cnt; 730 base_step_cnt = step_cnt; 731 if (best_mul == opt_div) 732 break; 733 } 734 } 735 736 if (ret) 737 return -EINVAL; 738 739 sample_cnt = base_sample_cnt; 740 step_cnt = base_step_cnt; 741 742 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 743 /* In this case, hardware can't support such 744 * low i2c_bus_freq 745 */ 746 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 747 return -EINVAL; 748 } 749 750 *timing_step_cnt = step_cnt - 1; 751 *timing_sample_cnt = sample_cnt - 1; 752 753 return 0; 754 } 755 756 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 757 { 758 unsigned int clk_src; 759 unsigned int step_cnt; 760 unsigned int sample_cnt; 761 unsigned int l_step_cnt; 762 unsigned int l_sample_cnt; 763 unsigned int target_speed; 764 unsigned int clk_div; 765 unsigned int max_clk_div; 766 int ret; 767 768 target_speed = i2c->speed_hz; 769 parent_clk /= i2c->clk_src_div; 770 771 if (i2c->dev_comp->timing_adjust) 772 max_clk_div = MAX_CLOCK_DIV; 773 else 774 max_clk_div = 1; 775 776 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 777 clk_src = parent_clk / clk_div; 778 779 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 780 /* Set master code speed register */ 781 ret = mtk_i2c_calculate_speed(i2c, clk_src, 782 I2C_MAX_FAST_MODE_FREQ, 783 &l_step_cnt, 784 &l_sample_cnt); 785 if (ret < 0) 786 continue; 787 788 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 789 790 /* Set the high speed mode register */ 791 ret = mtk_i2c_calculate_speed(i2c, clk_src, 792 target_speed, &step_cnt, 793 &sample_cnt); 794 if (ret < 0) 795 continue; 796 797 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 798 (sample_cnt << 12) | (step_cnt << 8); 799 800 if (i2c->dev_comp->ltiming_adjust) 801 i2c->ltiming_reg = 802 (l_sample_cnt << 6) | l_step_cnt | 803 (sample_cnt << 12) | (step_cnt << 9); 804 } else { 805 ret = mtk_i2c_calculate_speed(i2c, clk_src, 806 target_speed, &l_step_cnt, 807 &l_sample_cnt); 808 if (ret < 0) 809 continue; 810 811 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 812 813 /* Disable the high speed transaction */ 814 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 815 816 if (i2c->dev_comp->ltiming_adjust) 817 i2c->ltiming_reg = 818 (l_sample_cnt << 6) | l_step_cnt; 819 } 820 821 break; 822 } 823 824 i2c->ac_timing.inter_clk_div = clk_div - 1; 825 826 return 0; 827 } 828 829 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 830 int num, int left_num) 831 { 832 u16 addr_reg; 833 u16 start_reg; 834 u16 control_reg; 835 u16 restart_flag = 0; 836 u16 dma_sync = 0; 837 u32 reg_4g_mode; 838 u8 *dma_rd_buf = NULL; 839 u8 *dma_wr_buf = NULL; 840 dma_addr_t rpaddr = 0; 841 dma_addr_t wpaddr = 0; 842 int ret; 843 844 i2c->irq_stat = 0; 845 846 if (i2c->auto_restart) 847 restart_flag = I2C_RS_TRANSFER; 848 849 reinit_completion(&i2c->msg_complete); 850 851 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 852 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 853 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 854 control_reg |= I2C_CONTROL_RS; 855 856 if (i2c->op == I2C_MASTER_WRRD) 857 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 858 859 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 860 861 addr_reg = i2c_8bit_addr_from_msg(msgs); 862 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 863 864 /* Clear interrupt status */ 865 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 866 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 867 868 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 869 870 /* Enable interrupt */ 871 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 872 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 873 874 /* Set transfer and transaction len */ 875 if (i2c->op == I2C_MASTER_WRRD) { 876 if (i2c->dev_comp->aux_len_reg) { 877 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 878 mtk_i2c_writew(i2c, (msgs + 1)->len, 879 OFFSET_TRANSFER_LEN_AUX); 880 } else { 881 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 882 OFFSET_TRANSFER_LEN); 883 } 884 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 885 } else { 886 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 887 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 888 } 889 890 if (i2c->dev_comp->apdma_sync) { 891 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 892 if (i2c->op == I2C_MASTER_WRRD) 893 dma_sync |= I2C_DMA_DIR_CHANGE; 894 } 895 896 /* Prepare buffer data to start transfer */ 897 if (i2c->op == I2C_MASTER_RD) { 898 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 899 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 900 901 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 902 if (!dma_rd_buf) 903 return -ENOMEM; 904 905 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 906 msgs->len, DMA_FROM_DEVICE); 907 if (dma_mapping_error(i2c->dev, rpaddr)) { 908 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 909 910 return -ENOMEM; 911 } 912 913 if (i2c->dev_comp->max_dma_support > 32) { 914 reg_4g_mode = upper_32_bits(rpaddr); 915 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 916 } 917 918 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 919 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 920 } else if (i2c->op == I2C_MASTER_WR) { 921 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 922 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 923 924 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 925 if (!dma_wr_buf) 926 return -ENOMEM; 927 928 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 929 msgs->len, DMA_TO_DEVICE); 930 if (dma_mapping_error(i2c->dev, wpaddr)) { 931 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 932 933 return -ENOMEM; 934 } 935 936 if (i2c->dev_comp->max_dma_support > 32) { 937 reg_4g_mode = upper_32_bits(wpaddr); 938 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 939 } 940 941 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 942 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 943 } else { 944 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 945 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 946 947 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 948 if (!dma_wr_buf) 949 return -ENOMEM; 950 951 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 952 msgs->len, DMA_TO_DEVICE); 953 if (dma_mapping_error(i2c->dev, wpaddr)) { 954 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 955 956 return -ENOMEM; 957 } 958 959 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 960 if (!dma_rd_buf) { 961 dma_unmap_single(i2c->dev, wpaddr, 962 msgs->len, DMA_TO_DEVICE); 963 964 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 965 966 return -ENOMEM; 967 } 968 969 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 970 (msgs + 1)->len, 971 DMA_FROM_DEVICE); 972 if (dma_mapping_error(i2c->dev, rpaddr)) { 973 dma_unmap_single(i2c->dev, wpaddr, 974 msgs->len, DMA_TO_DEVICE); 975 976 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 977 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 978 979 return -ENOMEM; 980 } 981 982 if (i2c->dev_comp->max_dma_support > 32) { 983 reg_4g_mode = upper_32_bits(wpaddr); 984 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 985 986 reg_4g_mode = upper_32_bits(rpaddr); 987 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 988 } 989 990 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 991 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 992 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 993 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 994 } 995 996 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 997 998 if (!i2c->auto_restart) { 999 start_reg = I2C_TRANSAC_START; 1000 } else { 1001 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1002 if (left_num >= 1) 1003 start_reg |= I2C_RS_MUL_CNFG; 1004 } 1005 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1006 1007 ret = wait_for_completion_timeout(&i2c->msg_complete, 1008 i2c->adap.timeout); 1009 1010 /* Clear interrupt mask */ 1011 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1012 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1013 1014 if (i2c->op == I2C_MASTER_WR) { 1015 dma_unmap_single(i2c->dev, wpaddr, 1016 msgs->len, DMA_TO_DEVICE); 1017 1018 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1019 } else if (i2c->op == I2C_MASTER_RD) { 1020 dma_unmap_single(i2c->dev, rpaddr, 1021 msgs->len, DMA_FROM_DEVICE); 1022 1023 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1024 } else { 1025 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1026 DMA_TO_DEVICE); 1027 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1028 DMA_FROM_DEVICE); 1029 1030 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1031 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1032 } 1033 1034 if (ret == 0) { 1035 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1036 mtk_i2c_init_hw(i2c); 1037 return -ETIMEDOUT; 1038 } 1039 1040 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1041 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1042 mtk_i2c_init_hw(i2c); 1043 return -ENXIO; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1050 struct i2c_msg msgs[], int num) 1051 { 1052 int ret; 1053 int left_num = num; 1054 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1055 1056 ret = mtk_i2c_clock_enable(i2c); 1057 if (ret) 1058 return ret; 1059 1060 i2c->auto_restart = i2c->dev_comp->auto_restart; 1061 1062 /* checking if we can skip restart and optimize using WRRD mode */ 1063 if (i2c->auto_restart && num == 2) { 1064 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1065 msgs[0].addr == msgs[1].addr) { 1066 i2c->auto_restart = 0; 1067 } 1068 } 1069 1070 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 1071 /* ignore the first restart irq after the master code, 1072 * otherwise the first transfer will be discarded. 1073 */ 1074 i2c->ignore_restart_irq = true; 1075 else 1076 i2c->ignore_restart_irq = false; 1077 1078 while (left_num--) { 1079 if (!msgs->buf) { 1080 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1081 ret = -EINVAL; 1082 goto err_exit; 1083 } 1084 1085 if (msgs->flags & I2C_M_RD) 1086 i2c->op = I2C_MASTER_RD; 1087 else 1088 i2c->op = I2C_MASTER_WR; 1089 1090 if (!i2c->auto_restart) { 1091 if (num > 1) { 1092 /* combined two messages into one transaction */ 1093 i2c->op = I2C_MASTER_WRRD; 1094 left_num--; 1095 } 1096 } 1097 1098 /* always use DMA mode. */ 1099 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1100 if (ret < 0) 1101 goto err_exit; 1102 1103 msgs++; 1104 } 1105 /* the return value is number of executed messages */ 1106 ret = num; 1107 1108 err_exit: 1109 mtk_i2c_clock_disable(i2c); 1110 return ret; 1111 } 1112 1113 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1114 { 1115 struct mtk_i2c *i2c = dev_id; 1116 u16 restart_flag = 0; 1117 u16 intr_stat; 1118 1119 if (i2c->auto_restart) 1120 restart_flag = I2C_RS_TRANSFER; 1121 1122 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1123 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1124 1125 /* 1126 * when occurs ack error, i2c controller generate two interrupts 1127 * first is the ack error interrupt, then the complete interrupt 1128 * i2c->irq_stat need keep the two interrupt value. 1129 */ 1130 i2c->irq_stat |= intr_stat; 1131 1132 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1133 i2c->ignore_restart_irq = false; 1134 i2c->irq_stat = 0; 1135 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1136 I2C_TRANSAC_START, OFFSET_START); 1137 } else { 1138 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1139 complete(&i2c->msg_complete); 1140 } 1141 1142 return IRQ_HANDLED; 1143 } 1144 1145 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1146 { 1147 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1148 return I2C_FUNC_I2C | 1149 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1150 else 1151 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1152 } 1153 1154 static const struct i2c_algorithm mtk_i2c_algorithm = { 1155 .master_xfer = mtk_i2c_transfer, 1156 .functionality = mtk_i2c_functionality, 1157 }; 1158 1159 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1160 { 1161 int ret; 1162 1163 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1164 if (ret < 0) 1165 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1166 1167 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1168 if (ret < 0) 1169 return ret; 1170 1171 if (i2c->clk_src_div == 0) 1172 return -EINVAL; 1173 1174 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1175 i2c->use_push_pull = 1176 of_property_read_bool(np, "mediatek,use-push-pull"); 1177 1178 return 0; 1179 } 1180 1181 static int mtk_i2c_probe(struct platform_device *pdev) 1182 { 1183 int ret = 0; 1184 struct mtk_i2c *i2c; 1185 struct clk *clk; 1186 struct resource *res; 1187 int irq; 1188 1189 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1190 if (!i2c) 1191 return -ENOMEM; 1192 1193 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1194 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1195 if (IS_ERR(i2c->base)) 1196 return PTR_ERR(i2c->base); 1197 1198 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1199 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1200 if (IS_ERR(i2c->pdmabase)) 1201 return PTR_ERR(i2c->pdmabase); 1202 1203 irq = platform_get_irq(pdev, 0); 1204 if (irq <= 0) 1205 return irq; 1206 1207 init_completion(&i2c->msg_complete); 1208 1209 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1210 i2c->adap.dev.of_node = pdev->dev.of_node; 1211 i2c->dev = &pdev->dev; 1212 i2c->adap.dev.parent = &pdev->dev; 1213 i2c->adap.owner = THIS_MODULE; 1214 i2c->adap.algo = &mtk_i2c_algorithm; 1215 i2c->adap.quirks = i2c->dev_comp->quirks; 1216 i2c->adap.timeout = 2 * HZ; 1217 i2c->adap.retries = 1; 1218 1219 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1220 if (ret) 1221 return -EINVAL; 1222 1223 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1224 return -EINVAL; 1225 1226 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1227 if (IS_ERR(i2c->clk_main)) { 1228 dev_err(&pdev->dev, "cannot get main clock\n"); 1229 return PTR_ERR(i2c->clk_main); 1230 } 1231 1232 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1233 if (IS_ERR(i2c->clk_dma)) { 1234 dev_err(&pdev->dev, "cannot get dma clock\n"); 1235 return PTR_ERR(i2c->clk_dma); 1236 } 1237 1238 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1239 if (IS_ERR(i2c->clk_arb)) 1240 i2c->clk_arb = NULL; 1241 1242 clk = i2c->clk_main; 1243 if (i2c->have_pmic) { 1244 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1245 if (IS_ERR(i2c->clk_pmic)) { 1246 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1247 return PTR_ERR(i2c->clk_pmic); 1248 } 1249 clk = i2c->clk_pmic; 1250 } 1251 1252 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1253 1254 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1255 if (ret) { 1256 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1257 return -EINVAL; 1258 } 1259 1260 if (i2c->dev_comp->max_dma_support > 32) { 1261 ret = dma_set_mask(&pdev->dev, 1262 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1263 if (ret) { 1264 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1265 return ret; 1266 } 1267 } 1268 1269 ret = mtk_i2c_clock_enable(i2c); 1270 if (ret) { 1271 dev_err(&pdev->dev, "clock enable failed!\n"); 1272 return ret; 1273 } 1274 mtk_i2c_init_hw(i2c); 1275 mtk_i2c_clock_disable(i2c); 1276 1277 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1278 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1279 I2C_DRV_NAME, i2c); 1280 if (ret < 0) { 1281 dev_err(&pdev->dev, 1282 "Request I2C IRQ %d fail\n", irq); 1283 return ret; 1284 } 1285 1286 i2c_set_adapdata(&i2c->adap, i2c); 1287 ret = i2c_add_adapter(&i2c->adap); 1288 if (ret) 1289 return ret; 1290 1291 platform_set_drvdata(pdev, i2c); 1292 1293 return 0; 1294 } 1295 1296 static int mtk_i2c_remove(struct platform_device *pdev) 1297 { 1298 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1299 1300 i2c_del_adapter(&i2c->adap); 1301 1302 return 0; 1303 } 1304 1305 #ifdef CONFIG_PM_SLEEP 1306 static int mtk_i2c_suspend_noirq(struct device *dev) 1307 { 1308 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1309 1310 i2c_mark_adapter_suspended(&i2c->adap); 1311 1312 return 0; 1313 } 1314 1315 static int mtk_i2c_resume_noirq(struct device *dev) 1316 { 1317 int ret; 1318 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1319 1320 ret = mtk_i2c_clock_enable(i2c); 1321 if (ret) { 1322 dev_err(dev, "clock enable failed!\n"); 1323 return ret; 1324 } 1325 1326 mtk_i2c_init_hw(i2c); 1327 1328 mtk_i2c_clock_disable(i2c); 1329 1330 i2c_mark_adapter_resumed(&i2c->adap); 1331 1332 return 0; 1333 } 1334 #endif 1335 1336 static const struct dev_pm_ops mtk_i2c_pm = { 1337 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1338 mtk_i2c_resume_noirq) 1339 }; 1340 1341 static struct platform_driver mtk_i2c_driver = { 1342 .probe = mtk_i2c_probe, 1343 .remove = mtk_i2c_remove, 1344 .driver = { 1345 .name = I2C_DRV_NAME, 1346 .pm = &mtk_i2c_pm, 1347 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1348 }, 1349 }; 1350 1351 module_platform_driver(mtk_i2c_driver); 1352 1353 MODULE_LICENSE("GPL v2"); 1354 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1355 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1356