xref: /openbmc/linux/drivers/i2c/busses/i2c-mt65xx.c (revision c93db682)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Xudong Chen <xudong.chen@mediatek.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 
29 #define I2C_RS_TRANSFER			(1 << 4)
30 #define I2C_ARB_LOST			(1 << 3)
31 #define I2C_HS_NACKERR			(1 << 2)
32 #define I2C_ACKERR			(1 << 1)
33 #define I2C_TRANSAC_COMP		(1 << 0)
34 #define I2C_TRANSAC_START		(1 << 0)
35 #define I2C_RS_MUL_CNFG			(1 << 15)
36 #define I2C_RS_MUL_TRIG			(1 << 14)
37 #define I2C_DCM_DISABLE			0x0000
38 #define I2C_IO_CONFIG_OPEN_DRAIN	0x0003
39 #define I2C_IO_CONFIG_PUSH_PULL		0x0000
40 #define I2C_SOFT_RST			0x0001
41 #define I2C_HANDSHAKE_RST		0x0020
42 #define I2C_FIFO_ADDR_CLR		0x0001
43 #define I2C_DELAY_LEN			0x0002
44 #define I2C_TIME_CLR_VALUE		0x0000
45 #define I2C_TIME_DEFAULT_VALUE		0x0003
46 #define I2C_WRRD_TRANAC_VALUE		0x0002
47 #define I2C_RD_TRANAC_VALUE		0x0001
48 #define I2C_SCL_MIS_COMP_VALUE		0x0000
49 #define I2C_CHN_CLR_FLAG		0x0000
50 
51 #define I2C_DMA_CON_TX			0x0000
52 #define I2C_DMA_CON_RX			0x0001
53 #define I2C_DMA_ASYNC_MODE		0x0004
54 #define I2C_DMA_SKIP_CONFIG		0x0010
55 #define I2C_DMA_DIR_CHANGE		0x0200
56 #define I2C_DMA_START_EN		0x0001
57 #define I2C_DMA_INT_FLAG_NONE		0x0000
58 #define I2C_DMA_CLR_FLAG		0x0000
59 #define I2C_DMA_WARM_RST		0x0001
60 #define I2C_DMA_HARD_RST		0x0002
61 #define I2C_DMA_HANDSHAKE_RST		0x0004
62 
63 #define MAX_SAMPLE_CNT_DIV		8
64 #define MAX_STEP_CNT_DIV		64
65 #define MAX_CLOCK_DIV			256
66 #define MAX_HS_STEP_CNT_DIV		8
67 #define I2C_STANDARD_MODE_BUFFER	(1000 / 2)
68 #define I2C_FAST_MODE_BUFFER		(300 / 2)
69 #define I2C_FAST_MODE_PLUS_BUFFER	(20 / 2)
70 
71 #define I2C_CONTROL_RS                  (0x1 << 1)
72 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
73 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
74 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
75 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
77 #define I2C_CONTROL_DMAACK_EN           (0x1 << 8)
78 #define I2C_CONTROL_ASYNC_MODE          (0x1 << 9)
79 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
80 
81 #define I2C_DRV_NAME		"i2c-mt65xx"
82 
83 enum DMA_REGS_OFFSET {
84 	OFFSET_INT_FLAG = 0x0,
85 	OFFSET_INT_EN = 0x04,
86 	OFFSET_EN = 0x08,
87 	OFFSET_RST = 0x0c,
88 	OFFSET_CON = 0x18,
89 	OFFSET_TX_MEM_ADDR = 0x1c,
90 	OFFSET_RX_MEM_ADDR = 0x20,
91 	OFFSET_TX_LEN = 0x24,
92 	OFFSET_RX_LEN = 0x28,
93 	OFFSET_TX_4G_MODE = 0x54,
94 	OFFSET_RX_4G_MODE = 0x58,
95 };
96 
97 enum i2c_trans_st_rs {
98 	I2C_TRANS_STOP = 0,
99 	I2C_TRANS_REPEATED_START,
100 };
101 
102 enum mtk_trans_op {
103 	I2C_MASTER_WR = 1,
104 	I2C_MASTER_RD,
105 	I2C_MASTER_WRRD,
106 };
107 
108 enum I2C_REGS_OFFSET {
109 	OFFSET_DATA_PORT,
110 	OFFSET_SLAVE_ADDR,
111 	OFFSET_INTR_MASK,
112 	OFFSET_INTR_STAT,
113 	OFFSET_CONTROL,
114 	OFFSET_TRANSFER_LEN,
115 	OFFSET_TRANSAC_LEN,
116 	OFFSET_DELAY_LEN,
117 	OFFSET_TIMING,
118 	OFFSET_START,
119 	OFFSET_EXT_CONF,
120 	OFFSET_FIFO_STAT,
121 	OFFSET_FIFO_THRESH,
122 	OFFSET_FIFO_ADDR_CLR,
123 	OFFSET_IO_CONFIG,
124 	OFFSET_RSV_DEBUG,
125 	OFFSET_HS,
126 	OFFSET_SOFTRESET,
127 	OFFSET_DCM_EN,
128 	OFFSET_PATH_DIR,
129 	OFFSET_DEBUGSTAT,
130 	OFFSET_DEBUGCTRL,
131 	OFFSET_TRANSFER_LEN_AUX,
132 	OFFSET_CLOCK_DIV,
133 	OFFSET_LTIMING,
134 	OFFSET_SCL_HIGH_LOW_RATIO,
135 	OFFSET_HS_SCL_HIGH_LOW_RATIO,
136 	OFFSET_SCL_MIS_COMP_POINT,
137 	OFFSET_STA_STO_AC_TIMING,
138 	OFFSET_HS_STA_STO_AC_TIMING,
139 	OFFSET_SDA_TIMING,
140 };
141 
142 static const u16 mt_i2c_regs_v1[] = {
143 	[OFFSET_DATA_PORT] = 0x0,
144 	[OFFSET_SLAVE_ADDR] = 0x4,
145 	[OFFSET_INTR_MASK] = 0x8,
146 	[OFFSET_INTR_STAT] = 0xc,
147 	[OFFSET_CONTROL] = 0x10,
148 	[OFFSET_TRANSFER_LEN] = 0x14,
149 	[OFFSET_TRANSAC_LEN] = 0x18,
150 	[OFFSET_DELAY_LEN] = 0x1c,
151 	[OFFSET_TIMING] = 0x20,
152 	[OFFSET_START] = 0x24,
153 	[OFFSET_EXT_CONF] = 0x28,
154 	[OFFSET_FIFO_STAT] = 0x30,
155 	[OFFSET_FIFO_THRESH] = 0x34,
156 	[OFFSET_FIFO_ADDR_CLR] = 0x38,
157 	[OFFSET_IO_CONFIG] = 0x40,
158 	[OFFSET_RSV_DEBUG] = 0x44,
159 	[OFFSET_HS] = 0x48,
160 	[OFFSET_SOFTRESET] = 0x50,
161 	[OFFSET_DCM_EN] = 0x54,
162 	[OFFSET_PATH_DIR] = 0x60,
163 	[OFFSET_DEBUGSTAT] = 0x64,
164 	[OFFSET_DEBUGCTRL] = 0x68,
165 	[OFFSET_TRANSFER_LEN_AUX] = 0x6c,
166 	[OFFSET_CLOCK_DIV] = 0x70,
167 	[OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
168 	[OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
169 	[OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
170 	[OFFSET_STA_STO_AC_TIMING] = 0x80,
171 	[OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
172 	[OFFSET_SDA_TIMING] = 0x88,
173 };
174 
175 static const u16 mt_i2c_regs_v2[] = {
176 	[OFFSET_DATA_PORT] = 0x0,
177 	[OFFSET_SLAVE_ADDR] = 0x4,
178 	[OFFSET_INTR_MASK] = 0x8,
179 	[OFFSET_INTR_STAT] = 0xc,
180 	[OFFSET_CONTROL] = 0x10,
181 	[OFFSET_TRANSFER_LEN] = 0x14,
182 	[OFFSET_TRANSAC_LEN] = 0x18,
183 	[OFFSET_DELAY_LEN] = 0x1c,
184 	[OFFSET_TIMING] = 0x20,
185 	[OFFSET_START] = 0x24,
186 	[OFFSET_EXT_CONF] = 0x28,
187 	[OFFSET_LTIMING] = 0x2c,
188 	[OFFSET_HS] = 0x30,
189 	[OFFSET_IO_CONFIG] = 0x34,
190 	[OFFSET_FIFO_ADDR_CLR] = 0x38,
191 	[OFFSET_SDA_TIMING] = 0x3c,
192 	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
193 	[OFFSET_CLOCK_DIV] = 0x48,
194 	[OFFSET_SOFTRESET] = 0x50,
195 	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
196 	[OFFSET_DEBUGSTAT] = 0xe0,
197 	[OFFSET_DEBUGCTRL] = 0xe8,
198 	[OFFSET_FIFO_STAT] = 0xf4,
199 	[OFFSET_FIFO_THRESH] = 0xf8,
200 	[OFFSET_DCM_EN] = 0xf88,
201 };
202 
203 struct mtk_i2c_compatible {
204 	const struct i2c_adapter_quirks *quirks;
205 	const u16 *regs;
206 	unsigned char pmic_i2c: 1;
207 	unsigned char dcm: 1;
208 	unsigned char auto_restart: 1;
209 	unsigned char aux_len_reg: 1;
210 	unsigned char timing_adjust: 1;
211 	unsigned char dma_sync: 1;
212 	unsigned char ltiming_adjust: 1;
213 	unsigned char apdma_sync: 1;
214 	unsigned char max_dma_support;
215 };
216 
217 struct mtk_i2c_ac_timing {
218 	u16 htiming;
219 	u16 ltiming;
220 	u16 hs;
221 	u16 ext;
222 	u16 inter_clk_div;
223 	u16 scl_hl_ratio;
224 	u16 hs_scl_hl_ratio;
225 	u16 sta_stop;
226 	u16 hs_sta_stop;
227 	u16 sda_timing;
228 };
229 
230 struct mtk_i2c {
231 	struct i2c_adapter adap;	/* i2c host adapter */
232 	struct device *dev;
233 	struct completion msg_complete;
234 	struct i2c_timings timing_info;
235 
236 	/* set in i2c probe */
237 	void __iomem *base;		/* i2c base addr */
238 	void __iomem *pdmabase;		/* dma base address*/
239 	struct clk *clk_main;		/* main clock for i2c bus */
240 	struct clk *clk_dma;		/* DMA clock for i2c via DMA */
241 	struct clk *clk_pmic;		/* PMIC clock for i2c from PMIC */
242 	struct clk *clk_arb;		/* Arbitrator clock for i2c */
243 	bool have_pmic;			/* can use i2c pins from PMIC */
244 	bool use_push_pull;		/* IO config push-pull mode */
245 
246 	u16 irq_stat;			/* interrupt status */
247 	unsigned int clk_src_div;
248 	unsigned int speed_hz;		/* The speed in transfer */
249 	enum mtk_trans_op op;
250 	u16 timing_reg;
251 	u16 high_speed_reg;
252 	u16 ltiming_reg;
253 	unsigned char auto_restart;
254 	bool ignore_restart_irq;
255 	struct mtk_i2c_ac_timing ac_timing;
256 	const struct mtk_i2c_compatible *dev_comp;
257 };
258 
259 /**
260  * struct i2c_spec_values:
261  * @min_low_ns: min LOW period of the SCL clock
262  * @min_su_sta_ns: min set-up time for a repeated START condition
263  * @max_hd_dat_ns: max data hold time
264  * @min_su_dat_ns: min data set-up time
265  */
266 struct i2c_spec_values {
267 	unsigned int min_low_ns;
268 	unsigned int min_su_sta_ns;
269 	unsigned int max_hd_dat_ns;
270 	unsigned int min_su_dat_ns;
271 };
272 
273 static const struct i2c_spec_values standard_mode_spec = {
274 	.min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
275 	.min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
276 	.max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
277 	.min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
278 };
279 
280 static const struct i2c_spec_values fast_mode_spec = {
281 	.min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
282 	.min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
283 	.max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
284 	.min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
285 };
286 
287 static const struct i2c_spec_values fast_mode_plus_spec = {
288 	.min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
289 	.min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
290 	.max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
291 	.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
292 };
293 
294 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
295 	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
296 	.max_num_msgs = 1,
297 	.max_write_len = 255,
298 	.max_read_len = 255,
299 	.max_comb_1st_msg_len = 255,
300 	.max_comb_2nd_msg_len = 31,
301 };
302 
303 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
304 	.max_num_msgs = 255,
305 };
306 
307 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
308 	.flags = I2C_AQ_NO_ZERO_LEN,
309 };
310 
311 static const struct mtk_i2c_compatible mt2712_compat = {
312 	.regs = mt_i2c_regs_v1,
313 	.pmic_i2c = 0,
314 	.dcm = 1,
315 	.auto_restart = 1,
316 	.aux_len_reg = 1,
317 	.timing_adjust = 1,
318 	.dma_sync = 0,
319 	.ltiming_adjust = 0,
320 	.apdma_sync = 0,
321 	.max_dma_support = 33,
322 };
323 
324 static const struct mtk_i2c_compatible mt6577_compat = {
325 	.quirks = &mt6577_i2c_quirks,
326 	.regs = mt_i2c_regs_v1,
327 	.pmic_i2c = 0,
328 	.dcm = 1,
329 	.auto_restart = 0,
330 	.aux_len_reg = 0,
331 	.timing_adjust = 0,
332 	.dma_sync = 0,
333 	.ltiming_adjust = 0,
334 	.apdma_sync = 0,
335 	.max_dma_support = 32,
336 };
337 
338 static const struct mtk_i2c_compatible mt6589_compat = {
339 	.quirks = &mt6577_i2c_quirks,
340 	.regs = mt_i2c_regs_v1,
341 	.pmic_i2c = 1,
342 	.dcm = 0,
343 	.auto_restart = 0,
344 	.aux_len_reg = 0,
345 	.timing_adjust = 0,
346 	.dma_sync = 0,
347 	.ltiming_adjust = 0,
348 	.apdma_sync = 0,
349 	.max_dma_support = 32,
350 };
351 
352 static const struct mtk_i2c_compatible mt7622_compat = {
353 	.quirks = &mt7622_i2c_quirks,
354 	.regs = mt_i2c_regs_v1,
355 	.pmic_i2c = 0,
356 	.dcm = 1,
357 	.auto_restart = 1,
358 	.aux_len_reg = 1,
359 	.timing_adjust = 0,
360 	.dma_sync = 0,
361 	.ltiming_adjust = 0,
362 	.apdma_sync = 0,
363 	.max_dma_support = 32,
364 };
365 
366 static const struct mtk_i2c_compatible mt8173_compat = {
367 	.regs = mt_i2c_regs_v1,
368 	.pmic_i2c = 0,
369 	.dcm = 1,
370 	.auto_restart = 1,
371 	.aux_len_reg = 1,
372 	.timing_adjust = 0,
373 	.dma_sync = 0,
374 	.ltiming_adjust = 0,
375 	.apdma_sync = 0,
376 	.max_dma_support = 33,
377 };
378 
379 static const struct mtk_i2c_compatible mt8183_compat = {
380 	.quirks = &mt8183_i2c_quirks,
381 	.regs = mt_i2c_regs_v2,
382 	.pmic_i2c = 0,
383 	.dcm = 0,
384 	.auto_restart = 1,
385 	.aux_len_reg = 1,
386 	.timing_adjust = 1,
387 	.dma_sync = 1,
388 	.ltiming_adjust = 1,
389 	.apdma_sync = 0,
390 	.max_dma_support = 33,
391 };
392 
393 static const struct mtk_i2c_compatible mt8192_compat = {
394 	.quirks = &mt8183_i2c_quirks,
395 	.regs = mt_i2c_regs_v2,
396 	.pmic_i2c = 0,
397 	.dcm = 0,
398 	.auto_restart = 1,
399 	.aux_len_reg = 1,
400 	.timing_adjust = 1,
401 	.dma_sync = 1,
402 	.ltiming_adjust = 1,
403 	.apdma_sync = 1,
404 	.max_dma_support = 36,
405 };
406 
407 static const struct of_device_id mtk_i2c_of_match[] = {
408 	{ .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
409 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
410 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
411 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
412 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
413 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
414 	{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
415 	{}
416 };
417 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
418 
419 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
420 {
421 	return readw(i2c->base + i2c->dev_comp->regs[reg]);
422 }
423 
424 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
425 			   enum I2C_REGS_OFFSET reg)
426 {
427 	writew(val, i2c->base + i2c->dev_comp->regs[reg]);
428 }
429 
430 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
431 {
432 	int ret;
433 
434 	ret = clk_prepare_enable(i2c->clk_dma);
435 	if (ret)
436 		return ret;
437 
438 	ret = clk_prepare_enable(i2c->clk_main);
439 	if (ret)
440 		goto err_main;
441 
442 	if (i2c->have_pmic) {
443 		ret = clk_prepare_enable(i2c->clk_pmic);
444 		if (ret)
445 			goto err_pmic;
446 	}
447 
448 	if (i2c->clk_arb) {
449 		ret = clk_prepare_enable(i2c->clk_arb);
450 		if (ret)
451 			goto err_arb;
452 	}
453 
454 	return 0;
455 
456 err_arb:
457 	if (i2c->have_pmic)
458 		clk_disable_unprepare(i2c->clk_pmic);
459 err_pmic:
460 	clk_disable_unprepare(i2c->clk_main);
461 err_main:
462 	clk_disable_unprepare(i2c->clk_dma);
463 
464 	return ret;
465 }
466 
467 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
468 {
469 	if (i2c->clk_arb)
470 		clk_disable_unprepare(i2c->clk_arb);
471 
472 	if (i2c->have_pmic)
473 		clk_disable_unprepare(i2c->clk_pmic);
474 
475 	clk_disable_unprepare(i2c->clk_main);
476 	clk_disable_unprepare(i2c->clk_dma);
477 }
478 
479 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
480 {
481 	u16 control_reg;
482 
483 	if (i2c->dev_comp->apdma_sync) {
484 		writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
485 		udelay(10);
486 		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
487 		udelay(10);
488 		writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
489 		       i2c->pdmabase + OFFSET_RST);
490 		mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
491 			       OFFSET_SOFTRESET);
492 		udelay(10);
493 		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
494 		mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
495 	} else {
496 		writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
497 		udelay(50);
498 		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
499 		mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
500 	}
501 
502 	/* Set ioconfig */
503 	if (i2c->use_push_pull)
504 		mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
505 	else
506 		mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
507 
508 	if (i2c->dev_comp->dcm)
509 		mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
510 
511 	mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
512 	mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
513 	if (i2c->dev_comp->ltiming_adjust)
514 		mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
515 
516 	if (i2c->dev_comp->timing_adjust) {
517 		mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
518 		mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
519 			       OFFSET_CLOCK_DIV);
520 		mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
521 			       OFFSET_SCL_MIS_COMP_POINT);
522 		mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
523 			       OFFSET_SDA_TIMING);
524 
525 		if (i2c->dev_comp->ltiming_adjust) {
526 			mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
527 				       OFFSET_TIMING);
528 			mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
529 			mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
530 				       OFFSET_LTIMING);
531 		} else {
532 			mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
533 				       OFFSET_SCL_HIGH_LOW_RATIO);
534 			mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
535 				       OFFSET_HS_SCL_HIGH_LOW_RATIO);
536 			mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
537 				       OFFSET_STA_STO_AC_TIMING);
538 			mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
539 				       OFFSET_HS_STA_STO_AC_TIMING);
540 		}
541 	}
542 
543 	/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
544 	if (i2c->have_pmic)
545 		mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
546 
547 	control_reg = I2C_CONTROL_ACKERR_DET_EN |
548 		      I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
549 	if (i2c->dev_comp->dma_sync)
550 		control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
551 
552 	mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
553 	mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
554 }
555 
556 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
557 {
558 	if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
559 		return &standard_mode_spec;
560 	else if (speed <= I2C_MAX_FAST_MODE_FREQ)
561 		return &fast_mode_spec;
562 	else
563 		return &fast_mode_plus_spec;
564 }
565 
566 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
567 {
568 	if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
569 		return MAX_HS_STEP_CNT_DIV;
570 	else
571 		return MAX_STEP_CNT_DIV;
572 }
573 
574 /*
575  * Check and Calculate i2c ac-timing
576  *
577  * Hardware design:
578  * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
579  * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
580  *
581  * Sample_ns is rounded down for xxx_cnt_div would be greater
582  * than the smallest spec.
583  * The sda_timing is chosen as the middle value between
584  * the largest and smallest.
585  */
586 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
587 				   unsigned int clk_src,
588 				   unsigned int check_speed,
589 				   unsigned int step_cnt,
590 				   unsigned int sample_cnt)
591 {
592 	const struct i2c_spec_values *spec;
593 	unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
594 	unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
595 	unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
596 					 clk_src);
597 
598 	if (!i2c->dev_comp->timing_adjust)
599 		return 0;
600 
601 	if (i2c->dev_comp->ltiming_adjust)
602 		max_sta_cnt = 0x100;
603 
604 	spec = mtk_i2c_get_spec(check_speed);
605 
606 	if (i2c->dev_comp->ltiming_adjust)
607 		clk_ns = 1000000000 / clk_src;
608 	else
609 		clk_ns = sample_ns / 2;
610 
611 	su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
612 				  i2c->timing_info.scl_int_delay_ns, clk_ns);
613 	if (su_sta_cnt > max_sta_cnt)
614 		return -1;
615 
616 	low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
617 	max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
618 	if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
619 		if (low_cnt > step_cnt) {
620 			high_cnt = 2 * step_cnt - low_cnt;
621 		} else {
622 			high_cnt = step_cnt;
623 			low_cnt = step_cnt;
624 		}
625 	} else {
626 		return -2;
627 	}
628 
629 	sda_max = spec->max_hd_dat_ns / sample_ns;
630 	if (sda_max > low_cnt)
631 		sda_max = 0;
632 
633 	sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
634 	if (sda_min < low_cnt)
635 		sda_min = 0;
636 
637 	if (sda_min > sda_max)
638 		return -3;
639 
640 	if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
641 		if (i2c->dev_comp->ltiming_adjust) {
642 			i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
643 				(sample_cnt << 12) | (high_cnt << 8);
644 			i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
645 			i2c->ac_timing.ltiming |= (sample_cnt << 12) |
646 				(low_cnt << 9);
647 			i2c->ac_timing.ext &= ~GENMASK(7, 1);
648 			i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
649 		} else {
650 			i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
651 				(high_cnt << 6) | low_cnt;
652 			i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
653 				su_sta_cnt;
654 		}
655 		i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
656 		i2c->ac_timing.sda_timing |= (1 << 12) |
657 			((sda_max + sda_min) / 2) << 6;
658 	} else {
659 		if (i2c->dev_comp->ltiming_adjust) {
660 			i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
661 			i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
662 			i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
663 		} else {
664 			i2c->ac_timing.scl_hl_ratio = (1 << 12) |
665 				(high_cnt << 6) | low_cnt;
666 			i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
667 				su_sta_cnt;
668 		}
669 
670 		i2c->ac_timing.sda_timing = (1 << 12) |
671 			(sda_max + sda_min) / 2;
672 	}
673 
674 	return 0;
675 }
676 
677 /*
678  * Calculate i2c port speed
679  *
680  * Hardware design:
681  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
682  * clock_div: fixed in hardware, but may be various in different SoCs
683  *
684  * The calculation want to pick the highest bus frequency that is still
685  * less than or equal to i2c->speed_hz. The calculation try to get
686  * sample_cnt and step_cn
687  */
688 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
689 				   unsigned int target_speed,
690 				   unsigned int *timing_step_cnt,
691 				   unsigned int *timing_sample_cnt)
692 {
693 	unsigned int step_cnt;
694 	unsigned int sample_cnt;
695 	unsigned int max_step_cnt;
696 	unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
697 	unsigned int base_step_cnt;
698 	unsigned int opt_div;
699 	unsigned int best_mul;
700 	unsigned int cnt_mul;
701 	int ret = -EINVAL;
702 
703 	if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
704 		target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
705 
706 	max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
707 	base_step_cnt = max_step_cnt;
708 	/* Find the best combination */
709 	opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
710 	best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
711 
712 	/* Search for the best pair (sample_cnt, step_cnt) with
713 	 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
714 	 * 0 < step_cnt < max_step_cnt
715 	 * sample_cnt * step_cnt >= opt_div
716 	 * optimizing for sample_cnt * step_cnt being minimal
717 	 */
718 	for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
719 		step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
720 		cnt_mul = step_cnt * sample_cnt;
721 		if (step_cnt > max_step_cnt)
722 			continue;
723 
724 		if (cnt_mul < best_mul) {
725 			ret = mtk_i2c_check_ac_timing(i2c, clk_src,
726 				target_speed, step_cnt - 1, sample_cnt - 1);
727 			if (ret)
728 				continue;
729 
730 			best_mul = cnt_mul;
731 			base_sample_cnt = sample_cnt;
732 			base_step_cnt = step_cnt;
733 			if (best_mul == opt_div)
734 				break;
735 		}
736 	}
737 
738 	if (ret)
739 		return -EINVAL;
740 
741 	sample_cnt = base_sample_cnt;
742 	step_cnt = base_step_cnt;
743 
744 	if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
745 		/* In this case, hardware can't support such
746 		 * low i2c_bus_freq
747 		 */
748 		dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n",	target_speed);
749 		return -EINVAL;
750 	}
751 
752 	*timing_step_cnt = step_cnt - 1;
753 	*timing_sample_cnt = sample_cnt - 1;
754 
755 	return 0;
756 }
757 
758 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
759 {
760 	unsigned int clk_src;
761 	unsigned int step_cnt;
762 	unsigned int sample_cnt;
763 	unsigned int l_step_cnt;
764 	unsigned int l_sample_cnt;
765 	unsigned int target_speed;
766 	unsigned int clk_div;
767 	unsigned int max_clk_div;
768 	int ret;
769 
770 	target_speed = i2c->speed_hz;
771 	parent_clk /= i2c->clk_src_div;
772 
773 	if (i2c->dev_comp->timing_adjust)
774 		max_clk_div = MAX_CLOCK_DIV;
775 	else
776 		max_clk_div = 1;
777 
778 	for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
779 		clk_src = parent_clk / clk_div;
780 
781 		if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
782 			/* Set master code speed register */
783 			ret = mtk_i2c_calculate_speed(i2c, clk_src,
784 						      I2C_MAX_FAST_MODE_FREQ,
785 						      &l_step_cnt,
786 						      &l_sample_cnt);
787 			if (ret < 0)
788 				continue;
789 
790 			i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
791 
792 			/* Set the high speed mode register */
793 			ret = mtk_i2c_calculate_speed(i2c, clk_src,
794 						      target_speed, &step_cnt,
795 						      &sample_cnt);
796 			if (ret < 0)
797 				continue;
798 
799 			i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
800 					(sample_cnt << 12) | (step_cnt << 8);
801 
802 			if (i2c->dev_comp->ltiming_adjust)
803 				i2c->ltiming_reg =
804 					(l_sample_cnt << 6) | l_step_cnt |
805 					(sample_cnt << 12) | (step_cnt << 9);
806 		} else {
807 			ret = mtk_i2c_calculate_speed(i2c, clk_src,
808 						      target_speed, &l_step_cnt,
809 						      &l_sample_cnt);
810 			if (ret < 0)
811 				continue;
812 
813 			i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
814 
815 			/* Disable the high speed transaction */
816 			i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
817 
818 			if (i2c->dev_comp->ltiming_adjust)
819 				i2c->ltiming_reg =
820 					(l_sample_cnt << 6) | l_step_cnt;
821 		}
822 
823 		break;
824 	}
825 
826 	i2c->ac_timing.inter_clk_div = clk_div - 1;
827 
828 	return 0;
829 }
830 
831 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
832 			       int num, int left_num)
833 {
834 	u16 addr_reg;
835 	u16 start_reg;
836 	u16 control_reg;
837 	u16 restart_flag = 0;
838 	u16 dma_sync = 0;
839 	u32 reg_4g_mode;
840 	u8 *dma_rd_buf = NULL;
841 	u8 *dma_wr_buf = NULL;
842 	dma_addr_t rpaddr = 0;
843 	dma_addr_t wpaddr = 0;
844 	int ret;
845 
846 	i2c->irq_stat = 0;
847 
848 	if (i2c->auto_restart)
849 		restart_flag = I2C_RS_TRANSFER;
850 
851 	reinit_completion(&i2c->msg_complete);
852 
853 	control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
854 			~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
855 	if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
856 		control_reg |= I2C_CONTROL_RS;
857 
858 	if (i2c->op == I2C_MASTER_WRRD)
859 		control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
860 
861 	mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
862 
863 	addr_reg = i2c_8bit_addr_from_msg(msgs);
864 	mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
865 
866 	/* Clear interrupt status */
867 	mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
868 			    I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
869 
870 	mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
871 
872 	/* Enable interrupt */
873 	mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
874 			    I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
875 
876 	/* Set transfer and transaction len */
877 	if (i2c->op == I2C_MASTER_WRRD) {
878 		if (i2c->dev_comp->aux_len_reg) {
879 			mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
880 			mtk_i2c_writew(i2c, (msgs + 1)->len,
881 					    OFFSET_TRANSFER_LEN_AUX);
882 		} else {
883 			mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
884 					    OFFSET_TRANSFER_LEN);
885 		}
886 		mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
887 	} else {
888 		mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
889 		mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
890 	}
891 
892 	if (i2c->dev_comp->apdma_sync) {
893 		dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
894 		if (i2c->op == I2C_MASTER_WRRD)
895 			dma_sync |= I2C_DMA_DIR_CHANGE;
896 	}
897 
898 	/* Prepare buffer data to start transfer */
899 	if (i2c->op == I2C_MASTER_RD) {
900 		writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
901 		writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
902 
903 		dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
904 		if (!dma_rd_buf)
905 			return -ENOMEM;
906 
907 		rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
908 					msgs->len, DMA_FROM_DEVICE);
909 		if (dma_mapping_error(i2c->dev, rpaddr)) {
910 			i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
911 
912 			return -ENOMEM;
913 		}
914 
915 		if (i2c->dev_comp->max_dma_support > 32) {
916 			reg_4g_mode = upper_32_bits(rpaddr);
917 			writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
918 		}
919 
920 		writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
921 		writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
922 	} else if (i2c->op == I2C_MASTER_WR) {
923 		writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
924 		writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
925 
926 		dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
927 		if (!dma_wr_buf)
928 			return -ENOMEM;
929 
930 		wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
931 					msgs->len, DMA_TO_DEVICE);
932 		if (dma_mapping_error(i2c->dev, wpaddr)) {
933 			i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
934 
935 			return -ENOMEM;
936 		}
937 
938 		if (i2c->dev_comp->max_dma_support > 32) {
939 			reg_4g_mode = upper_32_bits(wpaddr);
940 			writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
941 		}
942 
943 		writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
944 		writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
945 	} else {
946 		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
947 		writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
948 
949 		dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
950 		if (!dma_wr_buf)
951 			return -ENOMEM;
952 
953 		wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
954 					msgs->len, DMA_TO_DEVICE);
955 		if (dma_mapping_error(i2c->dev, wpaddr)) {
956 			i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
957 
958 			return -ENOMEM;
959 		}
960 
961 		dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
962 		if (!dma_rd_buf) {
963 			dma_unmap_single(i2c->dev, wpaddr,
964 					 msgs->len, DMA_TO_DEVICE);
965 
966 			i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
967 
968 			return -ENOMEM;
969 		}
970 
971 		rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
972 					(msgs + 1)->len,
973 					DMA_FROM_DEVICE);
974 		if (dma_mapping_error(i2c->dev, rpaddr)) {
975 			dma_unmap_single(i2c->dev, wpaddr,
976 					 msgs->len, DMA_TO_DEVICE);
977 
978 			i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
979 			i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
980 
981 			return -ENOMEM;
982 		}
983 
984 		if (i2c->dev_comp->max_dma_support > 32) {
985 			reg_4g_mode = upper_32_bits(wpaddr);
986 			writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
987 
988 			reg_4g_mode = upper_32_bits(rpaddr);
989 			writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
990 		}
991 
992 		writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
993 		writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
994 		writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
995 		writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
996 	}
997 
998 	writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
999 
1000 	if (!i2c->auto_restart) {
1001 		start_reg = I2C_TRANSAC_START;
1002 	} else {
1003 		start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1004 		if (left_num >= 1)
1005 			start_reg |= I2C_RS_MUL_CNFG;
1006 	}
1007 	mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1008 
1009 	ret = wait_for_completion_timeout(&i2c->msg_complete,
1010 					  i2c->adap.timeout);
1011 
1012 	/* Clear interrupt mask */
1013 	mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1014 			    I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1015 
1016 	if (i2c->op == I2C_MASTER_WR) {
1017 		dma_unmap_single(i2c->dev, wpaddr,
1018 				 msgs->len, DMA_TO_DEVICE);
1019 
1020 		i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1021 	} else if (i2c->op == I2C_MASTER_RD) {
1022 		dma_unmap_single(i2c->dev, rpaddr,
1023 				 msgs->len, DMA_FROM_DEVICE);
1024 
1025 		i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1026 	} else {
1027 		dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1028 				 DMA_TO_DEVICE);
1029 		dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1030 				 DMA_FROM_DEVICE);
1031 
1032 		i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1033 		i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1034 	}
1035 
1036 	if (ret == 0) {
1037 		dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1038 		mtk_i2c_init_hw(i2c);
1039 		return -ETIMEDOUT;
1040 	}
1041 
1042 	if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1043 		dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1044 		mtk_i2c_init_hw(i2c);
1045 		return -ENXIO;
1046 	}
1047 
1048 	return 0;
1049 }
1050 
1051 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1052 			    struct i2c_msg msgs[], int num)
1053 {
1054 	int ret;
1055 	int left_num = num;
1056 	struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1057 
1058 	ret = mtk_i2c_clock_enable(i2c);
1059 	if (ret)
1060 		return ret;
1061 
1062 	i2c->auto_restart = i2c->dev_comp->auto_restart;
1063 
1064 	/* checking if we can skip restart and optimize using WRRD mode */
1065 	if (i2c->auto_restart && num == 2) {
1066 		if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1067 		    msgs[0].addr == msgs[1].addr) {
1068 			i2c->auto_restart = 0;
1069 		}
1070 	}
1071 
1072 	if (i2c->auto_restart && num >= 2 &&
1073 		i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1074 		/* ignore the first restart irq after the master code,
1075 		 * otherwise the first transfer will be discarded.
1076 		 */
1077 		i2c->ignore_restart_irq = true;
1078 	else
1079 		i2c->ignore_restart_irq = false;
1080 
1081 	while (left_num--) {
1082 		if (!msgs->buf) {
1083 			dev_dbg(i2c->dev, "data buffer is NULL.\n");
1084 			ret = -EINVAL;
1085 			goto err_exit;
1086 		}
1087 
1088 		if (msgs->flags & I2C_M_RD)
1089 			i2c->op = I2C_MASTER_RD;
1090 		else
1091 			i2c->op = I2C_MASTER_WR;
1092 
1093 		if (!i2c->auto_restart) {
1094 			if (num > 1) {
1095 				/* combined two messages into one transaction */
1096 				i2c->op = I2C_MASTER_WRRD;
1097 				left_num--;
1098 			}
1099 		}
1100 
1101 		/* always use DMA mode. */
1102 		ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1103 		if (ret < 0)
1104 			goto err_exit;
1105 
1106 		msgs++;
1107 	}
1108 	/* the return value is number of executed messages */
1109 	ret = num;
1110 
1111 err_exit:
1112 	mtk_i2c_clock_disable(i2c);
1113 	return ret;
1114 }
1115 
1116 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1117 {
1118 	struct mtk_i2c *i2c = dev_id;
1119 	u16 restart_flag = 0;
1120 	u16 intr_stat;
1121 
1122 	if (i2c->auto_restart)
1123 		restart_flag = I2C_RS_TRANSFER;
1124 
1125 	intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1126 	mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1127 
1128 	/*
1129 	 * when occurs ack error, i2c controller generate two interrupts
1130 	 * first is the ack error interrupt, then the complete interrupt
1131 	 * i2c->irq_stat need keep the two interrupt value.
1132 	 */
1133 	i2c->irq_stat |= intr_stat;
1134 
1135 	if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1136 		i2c->ignore_restart_irq = false;
1137 		i2c->irq_stat = 0;
1138 		mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1139 				    I2C_TRANSAC_START, OFFSET_START);
1140 	} else {
1141 		if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1142 			complete(&i2c->msg_complete);
1143 	}
1144 
1145 	return IRQ_HANDLED;
1146 }
1147 
1148 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1149 {
1150 	if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1151 		return I2C_FUNC_I2C |
1152 			(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1153 	else
1154 		return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1155 }
1156 
1157 static const struct i2c_algorithm mtk_i2c_algorithm = {
1158 	.master_xfer = mtk_i2c_transfer,
1159 	.functionality = mtk_i2c_functionality,
1160 };
1161 
1162 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1163 {
1164 	int ret;
1165 
1166 	ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1167 	if (ret < 0)
1168 		i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1169 
1170 	ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1171 	if (ret < 0)
1172 		return ret;
1173 
1174 	if (i2c->clk_src_div == 0)
1175 		return -EINVAL;
1176 
1177 	i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1178 	i2c->use_push_pull =
1179 		of_property_read_bool(np, "mediatek,use-push-pull");
1180 
1181 	i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1182 
1183 	return 0;
1184 }
1185 
1186 static int mtk_i2c_probe(struct platform_device *pdev)
1187 {
1188 	int ret = 0;
1189 	struct mtk_i2c *i2c;
1190 	struct clk *clk;
1191 	struct resource *res;
1192 	int irq;
1193 
1194 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1195 	if (!i2c)
1196 		return -ENOMEM;
1197 
1198 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199 	i2c->base = devm_ioremap_resource(&pdev->dev, res);
1200 	if (IS_ERR(i2c->base))
1201 		return PTR_ERR(i2c->base);
1202 
1203 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1204 	i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1205 	if (IS_ERR(i2c->pdmabase))
1206 		return PTR_ERR(i2c->pdmabase);
1207 
1208 	irq = platform_get_irq(pdev, 0);
1209 	if (irq <= 0)
1210 		return irq;
1211 
1212 	init_completion(&i2c->msg_complete);
1213 
1214 	i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1215 	i2c->adap.dev.of_node = pdev->dev.of_node;
1216 	i2c->dev = &pdev->dev;
1217 	i2c->adap.dev.parent = &pdev->dev;
1218 	i2c->adap.owner = THIS_MODULE;
1219 	i2c->adap.algo = &mtk_i2c_algorithm;
1220 	i2c->adap.quirks = i2c->dev_comp->quirks;
1221 	i2c->adap.timeout = 2 * HZ;
1222 	i2c->adap.retries = 1;
1223 
1224 	ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1225 	if (ret)
1226 		return -EINVAL;
1227 
1228 	if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1229 		return -EINVAL;
1230 
1231 	i2c->clk_main = devm_clk_get(&pdev->dev, "main");
1232 	if (IS_ERR(i2c->clk_main)) {
1233 		dev_err(&pdev->dev, "cannot get main clock\n");
1234 		return PTR_ERR(i2c->clk_main);
1235 	}
1236 
1237 	i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
1238 	if (IS_ERR(i2c->clk_dma)) {
1239 		dev_err(&pdev->dev, "cannot get dma clock\n");
1240 		return PTR_ERR(i2c->clk_dma);
1241 	}
1242 
1243 	i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
1244 	if (IS_ERR(i2c->clk_arb))
1245 		i2c->clk_arb = NULL;
1246 
1247 	clk = i2c->clk_main;
1248 	if (i2c->have_pmic) {
1249 		i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
1250 		if (IS_ERR(i2c->clk_pmic)) {
1251 			dev_err(&pdev->dev, "cannot get pmic clock\n");
1252 			return PTR_ERR(i2c->clk_pmic);
1253 		}
1254 		clk = i2c->clk_pmic;
1255 	}
1256 
1257 	strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1258 
1259 	ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
1260 	if (ret) {
1261 		dev_err(&pdev->dev, "Failed to set the speed.\n");
1262 		return -EINVAL;
1263 	}
1264 
1265 	if (i2c->dev_comp->max_dma_support > 32) {
1266 		ret = dma_set_mask(&pdev->dev,
1267 				DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1268 		if (ret) {
1269 			dev_err(&pdev->dev, "dma_set_mask return error.\n");
1270 			return ret;
1271 		}
1272 	}
1273 
1274 	ret = mtk_i2c_clock_enable(i2c);
1275 	if (ret) {
1276 		dev_err(&pdev->dev, "clock enable failed!\n");
1277 		return ret;
1278 	}
1279 	mtk_i2c_init_hw(i2c);
1280 	mtk_i2c_clock_disable(i2c);
1281 
1282 	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1283 			       IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1284 			       I2C_DRV_NAME, i2c);
1285 	if (ret < 0) {
1286 		dev_err(&pdev->dev,
1287 			"Request I2C IRQ %d fail\n", irq);
1288 		return ret;
1289 	}
1290 
1291 	i2c_set_adapdata(&i2c->adap, i2c);
1292 	ret = i2c_add_adapter(&i2c->adap);
1293 	if (ret)
1294 		return ret;
1295 
1296 	platform_set_drvdata(pdev, i2c);
1297 
1298 	return 0;
1299 }
1300 
1301 static int mtk_i2c_remove(struct platform_device *pdev)
1302 {
1303 	struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1304 
1305 	i2c_del_adapter(&i2c->adap);
1306 
1307 	return 0;
1308 }
1309 
1310 #ifdef CONFIG_PM_SLEEP
1311 static int mtk_i2c_suspend_noirq(struct device *dev)
1312 {
1313 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
1314 
1315 	i2c_mark_adapter_suspended(&i2c->adap);
1316 
1317 	return 0;
1318 }
1319 
1320 static int mtk_i2c_resume_noirq(struct device *dev)
1321 {
1322 	int ret;
1323 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
1324 
1325 	ret = mtk_i2c_clock_enable(i2c);
1326 	if (ret) {
1327 		dev_err(dev, "clock enable failed!\n");
1328 		return ret;
1329 	}
1330 
1331 	mtk_i2c_init_hw(i2c);
1332 
1333 	mtk_i2c_clock_disable(i2c);
1334 
1335 	i2c_mark_adapter_resumed(&i2c->adap);
1336 
1337 	return 0;
1338 }
1339 #endif
1340 
1341 static const struct dev_pm_ops mtk_i2c_pm = {
1342 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1343 				      mtk_i2c_resume_noirq)
1344 };
1345 
1346 static struct platform_driver mtk_i2c_driver = {
1347 	.probe = mtk_i2c_probe,
1348 	.remove = mtk_i2c_remove,
1349 	.driver = {
1350 		.name = I2C_DRV_NAME,
1351 		.pm = &mtk_i2c_pm,
1352 		.of_match_table = of_match_ptr(mtk_i2c_of_match),
1353 	},
1354 };
1355 
1356 module_platform_driver(mtk_i2c_driver);
1357 
1358 MODULE_LICENSE("GPL v2");
1359 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1360 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
1361