1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Xudong Chen <xudong.chen@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/err.h> 21 #include <linux/errno.h> 22 #include <linux/i2c.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/mm.h> 28 #include <linux/module.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/platform_device.h> 32 #include <linux/scatterlist.h> 33 #include <linux/sched.h> 34 #include <linux/slab.h> 35 36 #define I2C_RS_TRANSFER (1 << 4) 37 #define I2C_HS_NACKERR (1 << 2) 38 #define I2C_ACKERR (1 << 1) 39 #define I2C_TRANSAC_COMP (1 << 0) 40 #define I2C_TRANSAC_START (1 << 0) 41 #define I2C_RS_MUL_CNFG (1 << 15) 42 #define I2C_RS_MUL_TRIG (1 << 14) 43 #define I2C_DCM_DISABLE 0x0000 44 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 45 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 46 #define I2C_SOFT_RST 0x0001 47 #define I2C_FIFO_ADDR_CLR 0x0001 48 #define I2C_DELAY_LEN 0x0002 49 #define I2C_ST_START_CON 0x8001 50 #define I2C_FS_START_CON 0x1800 51 #define I2C_TIME_CLR_VALUE 0x0000 52 #define I2C_TIME_DEFAULT_VALUE 0x0003 53 #define I2C_FS_TIME_INIT_VALUE 0x1303 54 #define I2C_WRRD_TRANAC_VALUE 0x0002 55 #define I2C_RD_TRANAC_VALUE 0x0001 56 57 #define I2C_DMA_CON_TX 0x0000 58 #define I2C_DMA_CON_RX 0x0001 59 #define I2C_DMA_START_EN 0x0001 60 #define I2C_DMA_INT_FLAG_NONE 0x0000 61 #define I2C_DMA_CLR_FLAG 0x0000 62 63 #define I2C_DEFAULT_SPEED 100000 /* hz */ 64 #define MAX_FS_MODE_SPEED 400000 65 #define MAX_HS_MODE_SPEED 3400000 66 #define MAX_SAMPLE_CNT_DIV 8 67 #define MAX_STEP_CNT_DIV 64 68 #define MAX_HS_STEP_CNT_DIV 8 69 70 #define I2C_CONTROL_RS (0x1 << 1) 71 #define I2C_CONTROL_DMA_EN (0x1 << 2) 72 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 73 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 74 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 75 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 76 #define I2C_CONTROL_WRAPPER (0x1 << 0) 77 78 #define I2C_DRV_NAME "i2c-mt65xx" 79 80 enum DMA_REGS_OFFSET { 81 OFFSET_INT_FLAG = 0x0, 82 OFFSET_INT_EN = 0x04, 83 OFFSET_EN = 0x08, 84 OFFSET_CON = 0x18, 85 OFFSET_TX_MEM_ADDR = 0x1c, 86 OFFSET_RX_MEM_ADDR = 0x20, 87 OFFSET_TX_LEN = 0x24, 88 OFFSET_RX_LEN = 0x28, 89 }; 90 91 enum i2c_trans_st_rs { 92 I2C_TRANS_STOP = 0, 93 I2C_TRANS_REPEATED_START, 94 }; 95 96 enum mtk_trans_op { 97 I2C_MASTER_WR = 1, 98 I2C_MASTER_RD, 99 I2C_MASTER_WRRD, 100 }; 101 102 enum I2C_REGS_OFFSET { 103 OFFSET_DATA_PORT = 0x0, 104 OFFSET_SLAVE_ADDR = 0x04, 105 OFFSET_INTR_MASK = 0x08, 106 OFFSET_INTR_STAT = 0x0c, 107 OFFSET_CONTROL = 0x10, 108 OFFSET_TRANSFER_LEN = 0x14, 109 OFFSET_TRANSAC_LEN = 0x18, 110 OFFSET_DELAY_LEN = 0x1c, 111 OFFSET_TIMING = 0x20, 112 OFFSET_START = 0x24, 113 OFFSET_EXT_CONF = 0x28, 114 OFFSET_FIFO_STAT = 0x30, 115 OFFSET_FIFO_THRESH = 0x34, 116 OFFSET_FIFO_ADDR_CLR = 0x38, 117 OFFSET_IO_CONFIG = 0x40, 118 OFFSET_RSV_DEBUG = 0x44, 119 OFFSET_HS = 0x48, 120 OFFSET_SOFTRESET = 0x50, 121 OFFSET_DCM_EN = 0x54, 122 OFFSET_PATH_DIR = 0x60, 123 OFFSET_DEBUGSTAT = 0x64, 124 OFFSET_DEBUGCTRL = 0x68, 125 OFFSET_TRANSFER_LEN_AUX = 0x6c, 126 }; 127 128 struct mtk_i2c_compatible { 129 const struct i2c_adapter_quirks *quirks; 130 unsigned char pmic_i2c: 1; 131 unsigned char dcm: 1; 132 unsigned char auto_restart: 1; 133 }; 134 135 struct mtk_i2c { 136 struct i2c_adapter adap; /* i2c host adapter */ 137 struct device *dev; 138 struct completion msg_complete; 139 140 /* set in i2c probe */ 141 void __iomem *base; /* i2c base addr */ 142 void __iomem *pdmabase; /* dma base address*/ 143 struct clk *clk_main; /* main clock for i2c bus */ 144 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 145 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 146 bool have_pmic; /* can use i2c pins from PMIC */ 147 bool use_push_pull; /* IO config push-pull mode */ 148 149 u16 irq_stat; /* interrupt status */ 150 unsigned int speed_hz; /* The speed in transfer */ 151 enum mtk_trans_op op; 152 u16 timing_reg; 153 u16 high_speed_reg; 154 const struct mtk_i2c_compatible *dev_comp; 155 }; 156 157 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 158 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 159 .max_num_msgs = 1, 160 .max_write_len = 255, 161 .max_read_len = 255, 162 .max_comb_1st_msg_len = 255, 163 .max_comb_2nd_msg_len = 31, 164 }; 165 166 static const struct i2c_adapter_quirks mt8173_i2c_quirks = { 167 .max_num_msgs = 65535, 168 .max_write_len = 65535, 169 .max_read_len = 65535, 170 .max_comb_1st_msg_len = 65535, 171 .max_comb_2nd_msg_len = 65535, 172 }; 173 174 static const struct mtk_i2c_compatible mt6577_compat = { 175 .quirks = &mt6577_i2c_quirks, 176 .pmic_i2c = 0, 177 .dcm = 1, 178 .auto_restart = 0, 179 }; 180 181 static const struct mtk_i2c_compatible mt6589_compat = { 182 .quirks = &mt6577_i2c_quirks, 183 .pmic_i2c = 1, 184 .dcm = 0, 185 .auto_restart = 0, 186 }; 187 188 static const struct mtk_i2c_compatible mt8173_compat = { 189 .quirks = &mt8173_i2c_quirks, 190 .pmic_i2c = 0, 191 .dcm = 1, 192 .auto_restart = 1, 193 }; 194 195 static const struct of_device_id mtk_i2c_of_match[] = { 196 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 197 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 198 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 199 {} 200 }; 201 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 202 203 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 204 { 205 int ret; 206 207 ret = clk_prepare_enable(i2c->clk_dma); 208 if (ret) 209 return ret; 210 211 ret = clk_prepare_enable(i2c->clk_main); 212 if (ret) 213 goto err_main; 214 215 if (i2c->have_pmic) { 216 ret = clk_prepare_enable(i2c->clk_pmic); 217 if (ret) 218 goto err_pmic; 219 } 220 return 0; 221 222 err_pmic: 223 clk_disable_unprepare(i2c->clk_main); 224 err_main: 225 clk_disable_unprepare(i2c->clk_dma); 226 227 return ret; 228 } 229 230 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 231 { 232 if (i2c->have_pmic) 233 clk_disable_unprepare(i2c->clk_pmic); 234 235 clk_disable_unprepare(i2c->clk_main); 236 clk_disable_unprepare(i2c->clk_dma); 237 } 238 239 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 240 { 241 u16 control_reg; 242 243 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET); 244 245 /* Set ioconfig */ 246 if (i2c->use_push_pull) 247 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG); 248 else 249 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG); 250 251 if (i2c->dev_comp->dcm) 252 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN); 253 254 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING); 255 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS); 256 257 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 258 if (i2c->have_pmic) 259 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR); 260 261 control_reg = I2C_CONTROL_ACKERR_DET_EN | 262 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 263 writew(control_reg, i2c->base + OFFSET_CONTROL); 264 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN); 265 } 266 267 /* 268 * Calculate i2c port speed 269 * 270 * Hardware design: 271 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 272 * clock_div: fixed in hardware, but may be various in different SoCs 273 * 274 * The calculation want to pick the highest bus frequency that is still 275 * less than or equal to i2c->speed_hz. The calculation try to get 276 * sample_cnt and step_cn 277 */ 278 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk, 279 unsigned int clock_div) 280 { 281 unsigned int clk_src; 282 unsigned int step_cnt; 283 unsigned int sample_cnt; 284 unsigned int max_step_cnt; 285 unsigned int target_speed; 286 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 287 unsigned int base_step_cnt; 288 unsigned int opt_div; 289 unsigned int best_mul; 290 unsigned int cnt_mul; 291 292 clk_src = parent_clk / clock_div; 293 target_speed = i2c->speed_hz; 294 295 if (target_speed > MAX_HS_MODE_SPEED) 296 target_speed = MAX_HS_MODE_SPEED; 297 298 if (target_speed > MAX_FS_MODE_SPEED) 299 max_step_cnt = MAX_HS_STEP_CNT_DIV; 300 else 301 max_step_cnt = MAX_STEP_CNT_DIV; 302 303 base_step_cnt = max_step_cnt; 304 /* Find the best combination */ 305 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 306 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 307 308 /* Search for the best pair (sample_cnt, step_cnt) with 309 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 310 * 0 < step_cnt < max_step_cnt 311 * sample_cnt * step_cnt >= opt_div 312 * optimizing for sample_cnt * step_cnt being minimal 313 */ 314 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 315 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 316 cnt_mul = step_cnt * sample_cnt; 317 if (step_cnt > max_step_cnt) 318 continue; 319 320 if (cnt_mul < best_mul) { 321 best_mul = cnt_mul; 322 base_sample_cnt = sample_cnt; 323 base_step_cnt = step_cnt; 324 if (best_mul == opt_div) 325 break; 326 } 327 } 328 329 sample_cnt = base_sample_cnt; 330 step_cnt = base_step_cnt; 331 332 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 333 /* In this case, hardware can't support such 334 * low i2c_bus_freq 335 */ 336 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 337 return -EINVAL; 338 } 339 340 step_cnt--; 341 sample_cnt--; 342 343 if (target_speed > MAX_FS_MODE_SPEED) { 344 /* Set the high speed mode register */ 345 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE; 346 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 347 (sample_cnt << 12) | (step_cnt << 8); 348 } else { 349 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0); 350 /* Disable the high speed transaction */ 351 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 352 } 353 354 return 0; 355 } 356 357 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 358 int num, int left_num) 359 { 360 u16 addr_reg; 361 u16 start_reg; 362 u16 control_reg; 363 u16 restart_flag = 0; 364 dma_addr_t rpaddr = 0; 365 dma_addr_t wpaddr = 0; 366 int ret; 367 368 i2c->irq_stat = 0; 369 370 if (i2c->dev_comp->auto_restart) 371 restart_flag = I2C_RS_TRANSFER; 372 373 reinit_completion(&i2c->msg_complete); 374 375 control_reg = readw(i2c->base + OFFSET_CONTROL) & 376 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 377 if ((i2c->speed_hz > 400000) || (left_num >= 1)) 378 control_reg |= I2C_CONTROL_RS; 379 380 if (i2c->op == I2C_MASTER_WRRD) 381 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 382 383 writew(control_reg, i2c->base + OFFSET_CONTROL); 384 385 /* set start condition */ 386 if (i2c->speed_hz <= 100000) 387 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF); 388 else 389 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF); 390 391 addr_reg = msgs->addr << 1; 392 if (i2c->op == I2C_MASTER_RD) 393 addr_reg |= 0x1; 394 395 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR); 396 397 /* Clear interrupt status */ 398 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 399 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); 400 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR); 401 402 /* Enable interrupt */ 403 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 404 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK); 405 406 /* Set transfer and transaction len */ 407 if (i2c->op == I2C_MASTER_WRRD) { 408 writew(msgs->len | ((msgs + 1)->len) << 8, 409 i2c->base + OFFSET_TRANSFER_LEN); 410 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN); 411 } else { 412 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); 413 writew(num, i2c->base + OFFSET_TRANSAC_LEN); 414 } 415 416 /* Prepare buffer data to start transfer */ 417 if (i2c->op == I2C_MASTER_RD) { 418 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 419 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); 420 rpaddr = dma_map_single(i2c->dev, msgs->buf, 421 msgs->len, DMA_FROM_DEVICE); 422 if (dma_mapping_error(i2c->dev, rpaddr)) 423 return -ENOMEM; 424 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 425 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 426 } else if (i2c->op == I2C_MASTER_WR) { 427 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 428 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); 429 wpaddr = dma_map_single(i2c->dev, msgs->buf, 430 msgs->len, DMA_TO_DEVICE); 431 if (dma_mapping_error(i2c->dev, wpaddr)) 432 return -ENOMEM; 433 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 434 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 435 } else { 436 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 437 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); 438 wpaddr = dma_map_single(i2c->dev, msgs->buf, 439 msgs->len, DMA_TO_DEVICE); 440 if (dma_mapping_error(i2c->dev, wpaddr)) 441 return -ENOMEM; 442 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf, 443 (msgs + 1)->len, 444 DMA_FROM_DEVICE); 445 if (dma_mapping_error(i2c->dev, rpaddr)) { 446 dma_unmap_single(i2c->dev, wpaddr, 447 msgs->len, DMA_TO_DEVICE); 448 return -ENOMEM; 449 } 450 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 451 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 452 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 453 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 454 } 455 456 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 457 458 if (!i2c->dev_comp->auto_restart) { 459 start_reg = I2C_TRANSAC_START; 460 } else { 461 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 462 if (left_num >= 1) 463 start_reg |= I2C_RS_MUL_CNFG; 464 } 465 writew(start_reg, i2c->base + OFFSET_START); 466 467 ret = wait_for_completion_timeout(&i2c->msg_complete, 468 i2c->adap.timeout); 469 470 /* Clear interrupt mask */ 471 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 472 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK); 473 474 if (i2c->op == I2C_MASTER_WR) { 475 dma_unmap_single(i2c->dev, wpaddr, 476 msgs->len, DMA_TO_DEVICE); 477 } else if (i2c->op == I2C_MASTER_RD) { 478 dma_unmap_single(i2c->dev, rpaddr, 479 msgs->len, DMA_FROM_DEVICE); 480 } else { 481 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 482 DMA_TO_DEVICE); 483 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 484 DMA_FROM_DEVICE); 485 } 486 487 if (ret == 0) { 488 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 489 mtk_i2c_init_hw(i2c); 490 return -ETIMEDOUT; 491 } 492 493 completion_done(&i2c->msg_complete); 494 495 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 496 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 497 mtk_i2c_init_hw(i2c); 498 return -ENXIO; 499 } 500 501 return 0; 502 } 503 504 static int mtk_i2c_transfer(struct i2c_adapter *adap, 505 struct i2c_msg msgs[], int num) 506 { 507 int ret; 508 int left_num = num; 509 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 510 511 ret = mtk_i2c_clock_enable(i2c); 512 if (ret) 513 return ret; 514 515 while (left_num--) { 516 if (!msgs->buf) { 517 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 518 ret = -EINVAL; 519 goto err_exit; 520 } 521 522 if (msgs->flags & I2C_M_RD) 523 i2c->op = I2C_MASTER_RD; 524 else 525 i2c->op = I2C_MASTER_WR; 526 527 if (!i2c->dev_comp->auto_restart) { 528 if (num > 1) { 529 /* combined two messages into one transaction */ 530 i2c->op = I2C_MASTER_WRRD; 531 left_num--; 532 } 533 } 534 535 /* always use DMA mode. */ 536 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 537 if (ret < 0) 538 goto err_exit; 539 540 msgs++; 541 } 542 /* the return value is number of executed messages */ 543 ret = num; 544 545 err_exit: 546 mtk_i2c_clock_disable(i2c); 547 return ret; 548 } 549 550 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 551 { 552 struct mtk_i2c *i2c = dev_id; 553 u16 restart_flag = 0; 554 555 if (i2c->dev_comp->auto_restart) 556 restart_flag = I2C_RS_TRANSFER; 557 558 i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT); 559 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR 560 | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); 561 562 complete(&i2c->msg_complete); 563 564 return IRQ_HANDLED; 565 } 566 567 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 568 { 569 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 570 } 571 572 static const struct i2c_algorithm mtk_i2c_algorithm = { 573 .master_xfer = mtk_i2c_transfer, 574 .functionality = mtk_i2c_functionality, 575 }; 576 577 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c, 578 unsigned int *clk_src_div) 579 { 580 int ret; 581 582 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 583 if (ret < 0) 584 i2c->speed_hz = I2C_DEFAULT_SPEED; 585 586 ret = of_property_read_u32(np, "clock-div", clk_src_div); 587 if (ret < 0) 588 return ret; 589 590 if (*clk_src_div == 0) 591 return -EINVAL; 592 593 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 594 i2c->use_push_pull = 595 of_property_read_bool(np, "mediatek,use-push-pull"); 596 597 return 0; 598 } 599 600 static int mtk_i2c_probe(struct platform_device *pdev) 601 { 602 const struct of_device_id *of_id; 603 int ret = 0; 604 struct mtk_i2c *i2c; 605 struct clk *clk; 606 unsigned int clk_src_div; 607 struct resource *res; 608 int irq; 609 610 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 611 if (!i2c) 612 return -ENOMEM; 613 614 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div); 615 if (ret) 616 return -EINVAL; 617 618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 619 i2c->base = devm_ioremap_resource(&pdev->dev, res); 620 if (IS_ERR(i2c->base)) 621 return PTR_ERR(i2c->base); 622 623 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 624 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 625 if (IS_ERR(i2c->pdmabase)) 626 return PTR_ERR(i2c->pdmabase); 627 628 irq = platform_get_irq(pdev, 0); 629 if (irq <= 0) 630 return irq; 631 632 init_completion(&i2c->msg_complete); 633 634 of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node); 635 if (!of_id) 636 return -EINVAL; 637 638 i2c->dev_comp = of_id->data; 639 i2c->adap.dev.of_node = pdev->dev.of_node; 640 i2c->dev = &pdev->dev; 641 i2c->adap.dev.parent = &pdev->dev; 642 i2c->adap.owner = THIS_MODULE; 643 i2c->adap.algo = &mtk_i2c_algorithm; 644 i2c->adap.quirks = i2c->dev_comp->quirks; 645 i2c->adap.timeout = 2 * HZ; 646 i2c->adap.retries = 1; 647 648 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 649 return -EINVAL; 650 651 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 652 if (IS_ERR(i2c->clk_main)) { 653 dev_err(&pdev->dev, "cannot get main clock\n"); 654 return PTR_ERR(i2c->clk_main); 655 } 656 657 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 658 if (IS_ERR(i2c->clk_dma)) { 659 dev_err(&pdev->dev, "cannot get dma clock\n"); 660 return PTR_ERR(i2c->clk_dma); 661 } 662 663 clk = i2c->clk_main; 664 if (i2c->have_pmic) { 665 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 666 if (IS_ERR(i2c->clk_pmic)) { 667 dev_err(&pdev->dev, "cannot get pmic clock\n"); 668 return PTR_ERR(i2c->clk_pmic); 669 } 670 clk = i2c->clk_pmic; 671 } 672 673 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 674 675 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div); 676 if (ret) { 677 dev_err(&pdev->dev, "Failed to set the speed.\n"); 678 return -EINVAL; 679 } 680 681 ret = mtk_i2c_clock_enable(i2c); 682 if (ret) { 683 dev_err(&pdev->dev, "clock enable failed!\n"); 684 return ret; 685 } 686 mtk_i2c_init_hw(i2c); 687 mtk_i2c_clock_disable(i2c); 688 689 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 690 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 691 if (ret < 0) { 692 dev_err(&pdev->dev, 693 "Request I2C IRQ %d fail\n", irq); 694 return ret; 695 } 696 697 i2c_set_adapdata(&i2c->adap, i2c); 698 ret = i2c_add_adapter(&i2c->adap); 699 if (ret) { 700 dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n"); 701 return ret; 702 } 703 704 platform_set_drvdata(pdev, i2c); 705 706 return 0; 707 } 708 709 static int mtk_i2c_remove(struct platform_device *pdev) 710 { 711 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 712 713 i2c_del_adapter(&i2c->adap); 714 715 return 0; 716 } 717 718 static struct platform_driver mtk_i2c_driver = { 719 .probe = mtk_i2c_probe, 720 .remove = mtk_i2c_remove, 721 .driver = { 722 .name = I2C_DRV_NAME, 723 .of_match_table = of_match_ptr(mtk_i2c_of_match), 724 }, 725 }; 726 727 module_platform_driver(mtk_i2c_driver); 728 729 MODULE_LICENSE("GPL v2"); 730 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 731 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 732