1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_FIFO_ADDR_CLR 0x0001 42 #define I2C_DELAY_LEN 0x0002 43 #define I2C_TIME_CLR_VALUE 0x0000 44 #define I2C_TIME_DEFAULT_VALUE 0x0003 45 #define I2C_WRRD_TRANAC_VALUE 0x0002 46 #define I2C_RD_TRANAC_VALUE 0x0001 47 #define I2C_SCL_MIS_COMP_VALUE 0x0000 48 49 #define I2C_DMA_CON_TX 0x0000 50 #define I2C_DMA_CON_RX 0x0001 51 #define I2C_DMA_START_EN 0x0001 52 #define I2C_DMA_INT_FLAG_NONE 0x0000 53 #define I2C_DMA_CLR_FLAG 0x0000 54 #define I2C_DMA_HARD_RST 0x0002 55 #define I2C_DMA_4G_MODE 0x0001 56 57 #define MAX_SAMPLE_CNT_DIV 8 58 #define MAX_STEP_CNT_DIV 64 59 #define MAX_CLOCK_DIV 256 60 #define MAX_HS_STEP_CNT_DIV 8 61 #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 62 #define I2C_FAST_MODE_BUFFER (300 / 2) 63 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 64 65 #define I2C_CONTROL_RS (0x1 << 1) 66 #define I2C_CONTROL_DMA_EN (0x1 << 2) 67 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 68 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 69 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 70 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 71 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 72 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 73 #define I2C_CONTROL_WRAPPER (0x1 << 0) 74 75 #define I2C_DRV_NAME "i2c-mt65xx" 76 77 enum DMA_REGS_OFFSET { 78 OFFSET_INT_FLAG = 0x0, 79 OFFSET_INT_EN = 0x04, 80 OFFSET_EN = 0x08, 81 OFFSET_RST = 0x0c, 82 OFFSET_CON = 0x18, 83 OFFSET_TX_MEM_ADDR = 0x1c, 84 OFFSET_RX_MEM_ADDR = 0x20, 85 OFFSET_TX_LEN = 0x24, 86 OFFSET_RX_LEN = 0x28, 87 OFFSET_TX_4G_MODE = 0x54, 88 OFFSET_RX_4G_MODE = 0x58, 89 }; 90 91 enum i2c_trans_st_rs { 92 I2C_TRANS_STOP = 0, 93 I2C_TRANS_REPEATED_START, 94 }; 95 96 enum mtk_trans_op { 97 I2C_MASTER_WR = 1, 98 I2C_MASTER_RD, 99 I2C_MASTER_WRRD, 100 }; 101 102 enum I2C_REGS_OFFSET { 103 OFFSET_DATA_PORT, 104 OFFSET_SLAVE_ADDR, 105 OFFSET_INTR_MASK, 106 OFFSET_INTR_STAT, 107 OFFSET_CONTROL, 108 OFFSET_TRANSFER_LEN, 109 OFFSET_TRANSAC_LEN, 110 OFFSET_DELAY_LEN, 111 OFFSET_TIMING, 112 OFFSET_START, 113 OFFSET_EXT_CONF, 114 OFFSET_FIFO_STAT, 115 OFFSET_FIFO_THRESH, 116 OFFSET_FIFO_ADDR_CLR, 117 OFFSET_IO_CONFIG, 118 OFFSET_RSV_DEBUG, 119 OFFSET_HS, 120 OFFSET_SOFTRESET, 121 OFFSET_DCM_EN, 122 OFFSET_PATH_DIR, 123 OFFSET_DEBUGSTAT, 124 OFFSET_DEBUGCTRL, 125 OFFSET_TRANSFER_LEN_AUX, 126 OFFSET_CLOCK_DIV, 127 OFFSET_LTIMING, 128 OFFSET_SCL_HIGH_LOW_RATIO, 129 OFFSET_HS_SCL_HIGH_LOW_RATIO, 130 OFFSET_SCL_MIS_COMP_POINT, 131 OFFSET_STA_STO_AC_TIMING, 132 OFFSET_HS_STA_STO_AC_TIMING, 133 OFFSET_SDA_TIMING, 134 }; 135 136 static const u16 mt_i2c_regs_v1[] = { 137 [OFFSET_DATA_PORT] = 0x0, 138 [OFFSET_SLAVE_ADDR] = 0x4, 139 [OFFSET_INTR_MASK] = 0x8, 140 [OFFSET_INTR_STAT] = 0xc, 141 [OFFSET_CONTROL] = 0x10, 142 [OFFSET_TRANSFER_LEN] = 0x14, 143 [OFFSET_TRANSAC_LEN] = 0x18, 144 [OFFSET_DELAY_LEN] = 0x1c, 145 [OFFSET_TIMING] = 0x20, 146 [OFFSET_START] = 0x24, 147 [OFFSET_EXT_CONF] = 0x28, 148 [OFFSET_FIFO_STAT] = 0x30, 149 [OFFSET_FIFO_THRESH] = 0x34, 150 [OFFSET_FIFO_ADDR_CLR] = 0x38, 151 [OFFSET_IO_CONFIG] = 0x40, 152 [OFFSET_RSV_DEBUG] = 0x44, 153 [OFFSET_HS] = 0x48, 154 [OFFSET_SOFTRESET] = 0x50, 155 [OFFSET_DCM_EN] = 0x54, 156 [OFFSET_PATH_DIR] = 0x60, 157 [OFFSET_DEBUGSTAT] = 0x64, 158 [OFFSET_DEBUGCTRL] = 0x68, 159 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 160 [OFFSET_CLOCK_DIV] = 0x70, 161 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 162 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 163 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 164 [OFFSET_STA_STO_AC_TIMING] = 0x80, 165 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 166 [OFFSET_SDA_TIMING] = 0x88, 167 }; 168 169 static const u16 mt_i2c_regs_v2[] = { 170 [OFFSET_DATA_PORT] = 0x0, 171 [OFFSET_SLAVE_ADDR] = 0x4, 172 [OFFSET_INTR_MASK] = 0x8, 173 [OFFSET_INTR_STAT] = 0xc, 174 [OFFSET_CONTROL] = 0x10, 175 [OFFSET_TRANSFER_LEN] = 0x14, 176 [OFFSET_TRANSAC_LEN] = 0x18, 177 [OFFSET_DELAY_LEN] = 0x1c, 178 [OFFSET_TIMING] = 0x20, 179 [OFFSET_START] = 0x24, 180 [OFFSET_EXT_CONF] = 0x28, 181 [OFFSET_LTIMING] = 0x2c, 182 [OFFSET_HS] = 0x30, 183 [OFFSET_IO_CONFIG] = 0x34, 184 [OFFSET_FIFO_ADDR_CLR] = 0x38, 185 [OFFSET_SDA_TIMING] = 0x3c, 186 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 187 [OFFSET_CLOCK_DIV] = 0x48, 188 [OFFSET_SOFTRESET] = 0x50, 189 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 190 [OFFSET_DEBUGSTAT] = 0xe0, 191 [OFFSET_DEBUGCTRL] = 0xe8, 192 [OFFSET_FIFO_STAT] = 0xf4, 193 [OFFSET_FIFO_THRESH] = 0xf8, 194 [OFFSET_DCM_EN] = 0xf88, 195 }; 196 197 struct mtk_i2c_compatible { 198 const struct i2c_adapter_quirks *quirks; 199 const u16 *regs; 200 unsigned char pmic_i2c: 1; 201 unsigned char dcm: 1; 202 unsigned char auto_restart: 1; 203 unsigned char aux_len_reg: 1; 204 unsigned char support_33bits: 1; 205 unsigned char timing_adjust: 1; 206 unsigned char dma_sync: 1; 207 unsigned char ltiming_adjust: 1; 208 }; 209 210 struct mtk_i2c_ac_timing { 211 u16 htiming; 212 u16 ltiming; 213 u16 hs; 214 u16 ext; 215 u16 inter_clk_div; 216 u16 scl_hl_ratio; 217 u16 hs_scl_hl_ratio; 218 u16 sta_stop; 219 u16 hs_sta_stop; 220 u16 sda_timing; 221 }; 222 223 struct mtk_i2c { 224 struct i2c_adapter adap; /* i2c host adapter */ 225 struct device *dev; 226 struct completion msg_complete; 227 228 /* set in i2c probe */ 229 void __iomem *base; /* i2c base addr */ 230 void __iomem *pdmabase; /* dma base address*/ 231 struct clk *clk_main; /* main clock for i2c bus */ 232 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 233 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 234 struct clk *clk_arb; /* Arbitrator clock for i2c */ 235 bool have_pmic; /* can use i2c pins from PMIC */ 236 bool use_push_pull; /* IO config push-pull mode */ 237 238 u16 irq_stat; /* interrupt status */ 239 unsigned int clk_src_div; 240 unsigned int speed_hz; /* The speed in transfer */ 241 enum mtk_trans_op op; 242 u16 timing_reg; 243 u16 high_speed_reg; 244 u16 ltiming_reg; 245 unsigned char auto_restart; 246 bool ignore_restart_irq; 247 struct mtk_i2c_ac_timing ac_timing; 248 const struct mtk_i2c_compatible *dev_comp; 249 }; 250 251 /** 252 * struct i2c_spec_values: 253 * min_low_ns: min LOW period of the SCL clock 254 * min_su_sta_ns: min set-up time for a repeated START condition 255 * max_hd_dat_ns: max data hold time 256 * min_su_dat_ns: min data set-up time 257 */ 258 struct i2c_spec_values { 259 unsigned int min_low_ns; 260 unsigned int min_high_ns; 261 unsigned int min_su_sta_ns; 262 unsigned int max_hd_dat_ns; 263 unsigned int min_su_dat_ns; 264 }; 265 266 static const struct i2c_spec_values standard_mode_spec = { 267 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 268 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 269 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 270 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 271 }; 272 273 static const struct i2c_spec_values fast_mode_spec = { 274 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 275 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 276 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 277 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 278 }; 279 280 static const struct i2c_spec_values fast_mode_plus_spec = { 281 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 282 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 283 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 284 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 285 }; 286 287 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 288 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 289 .max_num_msgs = 1, 290 .max_write_len = 255, 291 .max_read_len = 255, 292 .max_comb_1st_msg_len = 255, 293 .max_comb_2nd_msg_len = 31, 294 }; 295 296 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 297 .max_num_msgs = 255, 298 }; 299 300 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 301 .flags = I2C_AQ_NO_ZERO_LEN, 302 }; 303 304 static const struct mtk_i2c_compatible mt2712_compat = { 305 .regs = mt_i2c_regs_v1, 306 .pmic_i2c = 0, 307 .dcm = 1, 308 .auto_restart = 1, 309 .aux_len_reg = 1, 310 .support_33bits = 1, 311 .timing_adjust = 1, 312 .dma_sync = 0, 313 .ltiming_adjust = 0, 314 }; 315 316 static const struct mtk_i2c_compatible mt6577_compat = { 317 .quirks = &mt6577_i2c_quirks, 318 .regs = mt_i2c_regs_v1, 319 .pmic_i2c = 0, 320 .dcm = 1, 321 .auto_restart = 0, 322 .aux_len_reg = 0, 323 .support_33bits = 0, 324 .timing_adjust = 0, 325 .dma_sync = 0, 326 .ltiming_adjust = 0, 327 }; 328 329 static const struct mtk_i2c_compatible mt6589_compat = { 330 .quirks = &mt6577_i2c_quirks, 331 .regs = mt_i2c_regs_v1, 332 .pmic_i2c = 1, 333 .dcm = 0, 334 .auto_restart = 0, 335 .aux_len_reg = 0, 336 .support_33bits = 0, 337 .timing_adjust = 0, 338 .dma_sync = 0, 339 .ltiming_adjust = 0, 340 }; 341 342 static const struct mtk_i2c_compatible mt7622_compat = { 343 .quirks = &mt7622_i2c_quirks, 344 .regs = mt_i2c_regs_v1, 345 .pmic_i2c = 0, 346 .dcm = 1, 347 .auto_restart = 1, 348 .aux_len_reg = 1, 349 .support_33bits = 0, 350 .timing_adjust = 0, 351 .dma_sync = 0, 352 .ltiming_adjust = 0, 353 }; 354 355 static const struct mtk_i2c_compatible mt8173_compat = { 356 .regs = mt_i2c_regs_v1, 357 .pmic_i2c = 0, 358 .dcm = 1, 359 .auto_restart = 1, 360 .aux_len_reg = 1, 361 .support_33bits = 1, 362 .timing_adjust = 0, 363 .dma_sync = 0, 364 .ltiming_adjust = 0, 365 }; 366 367 static const struct mtk_i2c_compatible mt8183_compat = { 368 .quirks = &mt8183_i2c_quirks, 369 .regs = mt_i2c_regs_v2, 370 .pmic_i2c = 0, 371 .dcm = 0, 372 .auto_restart = 1, 373 .aux_len_reg = 1, 374 .support_33bits = 1, 375 .timing_adjust = 1, 376 .dma_sync = 1, 377 .ltiming_adjust = 1, 378 }; 379 380 static const struct of_device_id mtk_i2c_of_match[] = { 381 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 382 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 383 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 384 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 385 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 386 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 387 {} 388 }; 389 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 390 391 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 392 { 393 return readw(i2c->base + i2c->dev_comp->regs[reg]); 394 } 395 396 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 397 enum I2C_REGS_OFFSET reg) 398 { 399 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 400 } 401 402 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 403 { 404 int ret; 405 406 ret = clk_prepare_enable(i2c->clk_dma); 407 if (ret) 408 return ret; 409 410 ret = clk_prepare_enable(i2c->clk_main); 411 if (ret) 412 goto err_main; 413 414 if (i2c->have_pmic) { 415 ret = clk_prepare_enable(i2c->clk_pmic); 416 if (ret) 417 goto err_pmic; 418 } 419 420 if (i2c->clk_arb) { 421 ret = clk_prepare_enable(i2c->clk_arb); 422 if (ret) 423 goto err_arb; 424 } 425 426 return 0; 427 428 err_arb: 429 if (i2c->have_pmic) 430 clk_disable_unprepare(i2c->clk_pmic); 431 err_pmic: 432 clk_disable_unprepare(i2c->clk_main); 433 err_main: 434 clk_disable_unprepare(i2c->clk_dma); 435 436 return ret; 437 } 438 439 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 440 { 441 if (i2c->clk_arb) 442 clk_disable_unprepare(i2c->clk_arb); 443 444 if (i2c->have_pmic) 445 clk_disable_unprepare(i2c->clk_pmic); 446 447 clk_disable_unprepare(i2c->clk_main); 448 clk_disable_unprepare(i2c->clk_dma); 449 } 450 451 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 452 { 453 u16 control_reg; 454 455 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 456 457 /* Set ioconfig */ 458 if (i2c->use_push_pull) 459 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 460 else 461 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 462 463 if (i2c->dev_comp->dcm) 464 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 465 466 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 467 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 468 if (i2c->dev_comp->ltiming_adjust) 469 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 470 471 if (i2c->dev_comp->timing_adjust) { 472 mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF); 473 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 474 OFFSET_CLOCK_DIV); 475 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 476 OFFSET_SCL_MIS_COMP_POINT); 477 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 478 OFFSET_SDA_TIMING); 479 480 if (i2c->dev_comp->ltiming_adjust) { 481 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 482 OFFSET_TIMING); 483 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 484 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 485 OFFSET_LTIMING); 486 } else { 487 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 488 OFFSET_SCL_HIGH_LOW_RATIO); 489 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 490 OFFSET_HS_SCL_HIGH_LOW_RATIO); 491 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 492 OFFSET_STA_STO_AC_TIMING); 493 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 494 OFFSET_HS_STA_STO_AC_TIMING); 495 } 496 } 497 498 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 499 if (i2c->have_pmic) 500 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 501 502 control_reg = I2C_CONTROL_ACKERR_DET_EN | 503 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 504 if (i2c->dev_comp->dma_sync) 505 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 506 507 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 508 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 509 510 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 511 udelay(50); 512 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 513 } 514 515 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 516 { 517 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 518 return &standard_mode_spec; 519 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 520 return &fast_mode_spec; 521 else 522 return &fast_mode_plus_spec; 523 } 524 525 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 526 { 527 if (target_speed > I2C_MAX_FAST_MODE_FREQ) 528 return MAX_HS_STEP_CNT_DIV; 529 else 530 return MAX_STEP_CNT_DIV; 531 } 532 533 /* 534 * Check and Calculate i2c ac-timing 535 * 536 * Hardware design: 537 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 538 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 539 * 540 * Sample_ns is rounded down for xxx_cnt_div would be greater 541 * than the smallest spec. 542 * The sda_timing is chosen as the middle value between 543 * the largest and smallest. 544 */ 545 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 546 unsigned int clk_src, 547 unsigned int check_speed, 548 unsigned int step_cnt, 549 unsigned int sample_cnt) 550 { 551 const struct i2c_spec_values *spec; 552 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 553 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 554 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 555 clk_src); 556 557 if (!i2c->dev_comp->timing_adjust) 558 return 0; 559 560 if (i2c->dev_comp->ltiming_adjust) 561 max_sta_cnt = 0x100; 562 563 spec = mtk_i2c_get_spec(check_speed); 564 565 if (i2c->dev_comp->ltiming_adjust) 566 clk_ns = 1000000000 / clk_src; 567 else 568 clk_ns = sample_ns / 2; 569 570 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); 571 if (su_sta_cnt > max_sta_cnt) 572 return -1; 573 574 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 575 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 576 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 577 if (low_cnt > step_cnt) { 578 high_cnt = 2 * step_cnt - low_cnt; 579 } else { 580 high_cnt = step_cnt; 581 low_cnt = step_cnt; 582 } 583 } else { 584 return -2; 585 } 586 587 sda_max = spec->max_hd_dat_ns / sample_ns; 588 if (sda_max > low_cnt) 589 sda_max = 0; 590 591 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 592 if (sda_min < low_cnt) 593 sda_min = 0; 594 595 if (sda_min > sda_max) 596 return -3; 597 598 if (check_speed > I2C_MAX_FAST_MODE_FREQ) { 599 if (i2c->dev_comp->ltiming_adjust) { 600 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 601 (sample_cnt << 12) | (high_cnt << 8); 602 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 603 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 604 (low_cnt << 9); 605 i2c->ac_timing.ext &= ~GENMASK(7, 1); 606 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 607 } else { 608 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 609 (high_cnt << 6) | low_cnt; 610 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 611 su_sta_cnt; 612 } 613 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 614 i2c->ac_timing.sda_timing |= (1 << 12) | 615 ((sda_max + sda_min) / 2) << 6; 616 } else { 617 if (i2c->dev_comp->ltiming_adjust) { 618 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 619 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 620 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 621 } else { 622 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 623 (high_cnt << 6) | low_cnt; 624 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 625 su_sta_cnt; 626 } 627 628 i2c->ac_timing.sda_timing = (1 << 12) | 629 (sda_max + sda_min) / 2; 630 } 631 632 return 0; 633 } 634 635 /* 636 * Calculate i2c port speed 637 * 638 * Hardware design: 639 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 640 * clock_div: fixed in hardware, but may be various in different SoCs 641 * 642 * The calculation want to pick the highest bus frequency that is still 643 * less than or equal to i2c->speed_hz. The calculation try to get 644 * sample_cnt and step_cn 645 */ 646 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 647 unsigned int target_speed, 648 unsigned int *timing_step_cnt, 649 unsigned int *timing_sample_cnt) 650 { 651 unsigned int step_cnt; 652 unsigned int sample_cnt; 653 unsigned int max_step_cnt; 654 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 655 unsigned int base_step_cnt; 656 unsigned int opt_div; 657 unsigned int best_mul; 658 unsigned int cnt_mul; 659 int ret = -EINVAL; 660 661 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 662 target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ; 663 664 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 665 base_step_cnt = max_step_cnt; 666 /* Find the best combination */ 667 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 668 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 669 670 /* Search for the best pair (sample_cnt, step_cnt) with 671 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 672 * 0 < step_cnt < max_step_cnt 673 * sample_cnt * step_cnt >= opt_div 674 * optimizing for sample_cnt * step_cnt being minimal 675 */ 676 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 677 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 678 cnt_mul = step_cnt * sample_cnt; 679 if (step_cnt > max_step_cnt) 680 continue; 681 682 if (cnt_mul < best_mul) { 683 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 684 target_speed, step_cnt - 1, sample_cnt - 1); 685 if (ret) 686 continue; 687 688 best_mul = cnt_mul; 689 base_sample_cnt = sample_cnt; 690 base_step_cnt = step_cnt; 691 if (best_mul == opt_div) 692 break; 693 } 694 } 695 696 if (ret) 697 return -EINVAL; 698 699 sample_cnt = base_sample_cnt; 700 step_cnt = base_step_cnt; 701 702 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 703 /* In this case, hardware can't support such 704 * low i2c_bus_freq 705 */ 706 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 707 return -EINVAL; 708 } 709 710 *timing_step_cnt = step_cnt - 1; 711 *timing_sample_cnt = sample_cnt - 1; 712 713 return 0; 714 } 715 716 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 717 { 718 unsigned int clk_src; 719 unsigned int step_cnt; 720 unsigned int sample_cnt; 721 unsigned int l_step_cnt; 722 unsigned int l_sample_cnt; 723 unsigned int target_speed; 724 unsigned int clk_div; 725 unsigned int max_clk_div; 726 int ret; 727 728 target_speed = i2c->speed_hz; 729 parent_clk /= i2c->clk_src_div; 730 731 if (i2c->dev_comp->timing_adjust) 732 max_clk_div = MAX_CLOCK_DIV; 733 else 734 max_clk_div = 1; 735 736 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 737 clk_src = parent_clk / clk_div; 738 739 if (target_speed > I2C_MAX_FAST_MODE_FREQ) { 740 /* Set master code speed register */ 741 ret = mtk_i2c_calculate_speed(i2c, clk_src, 742 I2C_MAX_FAST_MODE_FREQ, 743 &l_step_cnt, 744 &l_sample_cnt); 745 if (ret < 0) 746 continue; 747 748 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 749 750 /* Set the high speed mode register */ 751 ret = mtk_i2c_calculate_speed(i2c, clk_src, 752 target_speed, &step_cnt, 753 &sample_cnt); 754 if (ret < 0) 755 continue; 756 757 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 758 (sample_cnt << 12) | (step_cnt << 8); 759 760 if (i2c->dev_comp->ltiming_adjust) 761 i2c->ltiming_reg = 762 (l_sample_cnt << 6) | l_step_cnt | 763 (sample_cnt << 12) | (step_cnt << 9); 764 } else { 765 ret = mtk_i2c_calculate_speed(i2c, clk_src, 766 target_speed, &l_step_cnt, 767 &l_sample_cnt); 768 if (ret < 0) 769 continue; 770 771 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 772 773 /* Disable the high speed transaction */ 774 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 775 776 if (i2c->dev_comp->ltiming_adjust) 777 i2c->ltiming_reg = 778 (l_sample_cnt << 6) | l_step_cnt; 779 } 780 781 break; 782 } 783 784 i2c->ac_timing.inter_clk_div = clk_div - 1; 785 786 return 0; 787 } 788 789 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr) 790 { 791 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG; 792 } 793 794 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 795 int num, int left_num) 796 { 797 u16 addr_reg; 798 u16 start_reg; 799 u16 control_reg; 800 u16 restart_flag = 0; 801 u32 reg_4g_mode; 802 u8 *dma_rd_buf = NULL; 803 u8 *dma_wr_buf = NULL; 804 dma_addr_t rpaddr = 0; 805 dma_addr_t wpaddr = 0; 806 int ret; 807 808 i2c->irq_stat = 0; 809 810 if (i2c->auto_restart) 811 restart_flag = I2C_RS_TRANSFER; 812 813 reinit_completion(&i2c->msg_complete); 814 815 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 816 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 817 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 818 control_reg |= I2C_CONTROL_RS; 819 820 if (i2c->op == I2C_MASTER_WRRD) 821 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 822 823 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 824 825 addr_reg = i2c_8bit_addr_from_msg(msgs); 826 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 827 828 /* Clear interrupt status */ 829 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 830 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 831 832 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 833 834 /* Enable interrupt */ 835 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 836 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 837 838 /* Set transfer and transaction len */ 839 if (i2c->op == I2C_MASTER_WRRD) { 840 if (i2c->dev_comp->aux_len_reg) { 841 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 842 mtk_i2c_writew(i2c, (msgs + 1)->len, 843 OFFSET_TRANSFER_LEN_AUX); 844 } else { 845 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 846 OFFSET_TRANSFER_LEN); 847 } 848 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 849 } else { 850 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 851 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 852 } 853 854 /* Prepare buffer data to start transfer */ 855 if (i2c->op == I2C_MASTER_RD) { 856 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 857 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); 858 859 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 860 if (!dma_rd_buf) 861 return -ENOMEM; 862 863 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 864 msgs->len, DMA_FROM_DEVICE); 865 if (dma_mapping_error(i2c->dev, rpaddr)) { 866 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 867 868 return -ENOMEM; 869 } 870 871 if (i2c->dev_comp->support_33bits) { 872 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 873 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 874 } 875 876 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 877 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 878 } else if (i2c->op == I2C_MASTER_WR) { 879 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 880 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); 881 882 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 883 if (!dma_wr_buf) 884 return -ENOMEM; 885 886 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 887 msgs->len, DMA_TO_DEVICE); 888 if (dma_mapping_error(i2c->dev, wpaddr)) { 889 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 890 891 return -ENOMEM; 892 } 893 894 if (i2c->dev_comp->support_33bits) { 895 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 896 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 897 } 898 899 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 900 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 901 } else { 902 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 903 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); 904 905 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 906 if (!dma_wr_buf) 907 return -ENOMEM; 908 909 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 910 msgs->len, DMA_TO_DEVICE); 911 if (dma_mapping_error(i2c->dev, wpaddr)) { 912 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 913 914 return -ENOMEM; 915 } 916 917 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 918 if (!dma_rd_buf) { 919 dma_unmap_single(i2c->dev, wpaddr, 920 msgs->len, DMA_TO_DEVICE); 921 922 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 923 924 return -ENOMEM; 925 } 926 927 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 928 (msgs + 1)->len, 929 DMA_FROM_DEVICE); 930 if (dma_mapping_error(i2c->dev, rpaddr)) { 931 dma_unmap_single(i2c->dev, wpaddr, 932 msgs->len, DMA_TO_DEVICE); 933 934 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 935 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 936 937 return -ENOMEM; 938 } 939 940 if (i2c->dev_comp->support_33bits) { 941 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 942 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 943 944 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 945 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 946 } 947 948 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 949 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 950 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 951 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 952 } 953 954 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 955 956 if (!i2c->auto_restart) { 957 start_reg = I2C_TRANSAC_START; 958 } else { 959 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 960 if (left_num >= 1) 961 start_reg |= I2C_RS_MUL_CNFG; 962 } 963 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 964 965 ret = wait_for_completion_timeout(&i2c->msg_complete, 966 i2c->adap.timeout); 967 968 /* Clear interrupt mask */ 969 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 970 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 971 972 if (i2c->op == I2C_MASTER_WR) { 973 dma_unmap_single(i2c->dev, wpaddr, 974 msgs->len, DMA_TO_DEVICE); 975 976 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 977 } else if (i2c->op == I2C_MASTER_RD) { 978 dma_unmap_single(i2c->dev, rpaddr, 979 msgs->len, DMA_FROM_DEVICE); 980 981 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 982 } else { 983 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 984 DMA_TO_DEVICE); 985 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 986 DMA_FROM_DEVICE); 987 988 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 989 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 990 } 991 992 if (ret == 0) { 993 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 994 mtk_i2c_init_hw(i2c); 995 return -ETIMEDOUT; 996 } 997 998 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 999 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1000 mtk_i2c_init_hw(i2c); 1001 return -ENXIO; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1008 struct i2c_msg msgs[], int num) 1009 { 1010 int ret; 1011 int left_num = num; 1012 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1013 1014 ret = mtk_i2c_clock_enable(i2c); 1015 if (ret) 1016 return ret; 1017 1018 i2c->auto_restart = i2c->dev_comp->auto_restart; 1019 1020 /* checking if we can skip restart and optimize using WRRD mode */ 1021 if (i2c->auto_restart && num == 2) { 1022 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1023 msgs[0].addr == msgs[1].addr) { 1024 i2c->auto_restart = 0; 1025 } 1026 } 1027 1028 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 1029 /* ignore the first restart irq after the master code, 1030 * otherwise the first transfer will be discarded. 1031 */ 1032 i2c->ignore_restart_irq = true; 1033 else 1034 i2c->ignore_restart_irq = false; 1035 1036 while (left_num--) { 1037 if (!msgs->buf) { 1038 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1039 ret = -EINVAL; 1040 goto err_exit; 1041 } 1042 1043 if (msgs->flags & I2C_M_RD) 1044 i2c->op = I2C_MASTER_RD; 1045 else 1046 i2c->op = I2C_MASTER_WR; 1047 1048 if (!i2c->auto_restart) { 1049 if (num > 1) { 1050 /* combined two messages into one transaction */ 1051 i2c->op = I2C_MASTER_WRRD; 1052 left_num--; 1053 } 1054 } 1055 1056 /* always use DMA mode. */ 1057 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1058 if (ret < 0) 1059 goto err_exit; 1060 1061 msgs++; 1062 } 1063 /* the return value is number of executed messages */ 1064 ret = num; 1065 1066 err_exit: 1067 mtk_i2c_clock_disable(i2c); 1068 return ret; 1069 } 1070 1071 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1072 { 1073 struct mtk_i2c *i2c = dev_id; 1074 u16 restart_flag = 0; 1075 u16 intr_stat; 1076 1077 if (i2c->auto_restart) 1078 restart_flag = I2C_RS_TRANSFER; 1079 1080 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1081 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1082 1083 /* 1084 * when occurs ack error, i2c controller generate two interrupts 1085 * first is the ack error interrupt, then the complete interrupt 1086 * i2c->irq_stat need keep the two interrupt value. 1087 */ 1088 i2c->irq_stat |= intr_stat; 1089 1090 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1091 i2c->ignore_restart_irq = false; 1092 i2c->irq_stat = 0; 1093 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1094 I2C_TRANSAC_START, OFFSET_START); 1095 } else { 1096 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1097 complete(&i2c->msg_complete); 1098 } 1099 1100 return IRQ_HANDLED; 1101 } 1102 1103 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1104 { 1105 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1106 return I2C_FUNC_I2C | 1107 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1108 else 1109 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1110 } 1111 1112 static const struct i2c_algorithm mtk_i2c_algorithm = { 1113 .master_xfer = mtk_i2c_transfer, 1114 .functionality = mtk_i2c_functionality, 1115 }; 1116 1117 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1118 { 1119 int ret; 1120 1121 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1122 if (ret < 0) 1123 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1124 1125 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1126 if (ret < 0) 1127 return ret; 1128 1129 if (i2c->clk_src_div == 0) 1130 return -EINVAL; 1131 1132 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1133 i2c->use_push_pull = 1134 of_property_read_bool(np, "mediatek,use-push-pull"); 1135 1136 return 0; 1137 } 1138 1139 static int mtk_i2c_probe(struct platform_device *pdev) 1140 { 1141 int ret = 0; 1142 struct mtk_i2c *i2c; 1143 struct clk *clk; 1144 struct resource *res; 1145 int irq; 1146 1147 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1148 if (!i2c) 1149 return -ENOMEM; 1150 1151 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1152 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1153 if (IS_ERR(i2c->base)) 1154 return PTR_ERR(i2c->base); 1155 1156 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1157 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1158 if (IS_ERR(i2c->pdmabase)) 1159 return PTR_ERR(i2c->pdmabase); 1160 1161 irq = platform_get_irq(pdev, 0); 1162 if (irq <= 0) 1163 return irq; 1164 1165 init_completion(&i2c->msg_complete); 1166 1167 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1168 i2c->adap.dev.of_node = pdev->dev.of_node; 1169 i2c->dev = &pdev->dev; 1170 i2c->adap.dev.parent = &pdev->dev; 1171 i2c->adap.owner = THIS_MODULE; 1172 i2c->adap.algo = &mtk_i2c_algorithm; 1173 i2c->adap.quirks = i2c->dev_comp->quirks; 1174 i2c->adap.timeout = 2 * HZ; 1175 i2c->adap.retries = 1; 1176 1177 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1178 if (ret) 1179 return -EINVAL; 1180 1181 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1182 return -EINVAL; 1183 1184 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1185 if (IS_ERR(i2c->clk_main)) { 1186 dev_err(&pdev->dev, "cannot get main clock\n"); 1187 return PTR_ERR(i2c->clk_main); 1188 } 1189 1190 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1191 if (IS_ERR(i2c->clk_dma)) { 1192 dev_err(&pdev->dev, "cannot get dma clock\n"); 1193 return PTR_ERR(i2c->clk_dma); 1194 } 1195 1196 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1197 if (IS_ERR(i2c->clk_arb)) 1198 i2c->clk_arb = NULL; 1199 1200 clk = i2c->clk_main; 1201 if (i2c->have_pmic) { 1202 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1203 if (IS_ERR(i2c->clk_pmic)) { 1204 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1205 return PTR_ERR(i2c->clk_pmic); 1206 } 1207 clk = i2c->clk_pmic; 1208 } 1209 1210 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1211 1212 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1213 if (ret) { 1214 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1215 return -EINVAL; 1216 } 1217 1218 if (i2c->dev_comp->support_33bits) { 1219 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33)); 1220 if (ret) { 1221 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1222 return ret; 1223 } 1224 } 1225 1226 ret = mtk_i2c_clock_enable(i2c); 1227 if (ret) { 1228 dev_err(&pdev->dev, "clock enable failed!\n"); 1229 return ret; 1230 } 1231 mtk_i2c_init_hw(i2c); 1232 mtk_i2c_clock_disable(i2c); 1233 1234 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1235 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 1236 if (ret < 0) { 1237 dev_err(&pdev->dev, 1238 "Request I2C IRQ %d fail\n", irq); 1239 return ret; 1240 } 1241 1242 i2c_set_adapdata(&i2c->adap, i2c); 1243 ret = i2c_add_adapter(&i2c->adap); 1244 if (ret) 1245 return ret; 1246 1247 platform_set_drvdata(pdev, i2c); 1248 1249 return 0; 1250 } 1251 1252 static int mtk_i2c_remove(struct platform_device *pdev) 1253 { 1254 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1255 1256 i2c_del_adapter(&i2c->adap); 1257 1258 return 0; 1259 } 1260 1261 #ifdef CONFIG_PM_SLEEP 1262 static int mtk_i2c_resume(struct device *dev) 1263 { 1264 int ret; 1265 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1266 1267 ret = mtk_i2c_clock_enable(i2c); 1268 if (ret) { 1269 dev_err(dev, "clock enable failed!\n"); 1270 return ret; 1271 } 1272 1273 mtk_i2c_init_hw(i2c); 1274 1275 mtk_i2c_clock_disable(i2c); 1276 1277 return 0; 1278 } 1279 #endif 1280 1281 static const struct dev_pm_ops mtk_i2c_pm = { 1282 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume) 1283 }; 1284 1285 static struct platform_driver mtk_i2c_driver = { 1286 .probe = mtk_i2c_probe, 1287 .remove = mtk_i2c_remove, 1288 .driver = { 1289 .name = I2C_DRV_NAME, 1290 .pm = &mtk_i2c_pm, 1291 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1292 }, 1293 }; 1294 1295 module_platform_driver(mtk_i2c_driver); 1296 1297 MODULE_LICENSE("GPL v2"); 1298 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1299 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1300