1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Xudong Chen <xudong.chen@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/err.h> 21 #include <linux/errno.h> 22 #include <linux/i2c.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/mm.h> 28 #include <linux/module.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/platform_device.h> 32 #include <linux/scatterlist.h> 33 #include <linux/sched.h> 34 #include <linux/slab.h> 35 36 #define I2C_RS_TRANSFER (1 << 4) 37 #define I2C_HS_NACKERR (1 << 2) 38 #define I2C_ACKERR (1 << 1) 39 #define I2C_TRANSAC_COMP (1 << 0) 40 #define I2C_TRANSAC_START (1 << 0) 41 #define I2C_RS_MUL_CNFG (1 << 15) 42 #define I2C_RS_MUL_TRIG (1 << 14) 43 #define I2C_DCM_DISABLE 0x0000 44 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 45 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 46 #define I2C_SOFT_RST 0x0001 47 #define I2C_FIFO_ADDR_CLR 0x0001 48 #define I2C_DELAY_LEN 0x0002 49 #define I2C_ST_START_CON 0x8001 50 #define I2C_FS_START_CON 0x1800 51 #define I2C_TIME_CLR_VALUE 0x0000 52 #define I2C_TIME_DEFAULT_VALUE 0x0003 53 #define I2C_WRRD_TRANAC_VALUE 0x0002 54 #define I2C_RD_TRANAC_VALUE 0x0001 55 56 #define I2C_DMA_CON_TX 0x0000 57 #define I2C_DMA_CON_RX 0x0001 58 #define I2C_DMA_START_EN 0x0001 59 #define I2C_DMA_INT_FLAG_NONE 0x0000 60 #define I2C_DMA_CLR_FLAG 0x0000 61 #define I2C_DMA_HARD_RST 0x0002 62 #define I2C_DMA_4G_MODE 0x0001 63 64 #define I2C_DEFAULT_CLK_DIV 5 65 #define I2C_DEFAULT_SPEED 100000 /* hz */ 66 #define MAX_FS_MODE_SPEED 400000 67 #define MAX_HS_MODE_SPEED 3400000 68 #define MAX_SAMPLE_CNT_DIV 8 69 #define MAX_STEP_CNT_DIV 64 70 #define MAX_HS_STEP_CNT_DIV 8 71 72 #define I2C_CONTROL_RS (0x1 << 1) 73 #define I2C_CONTROL_DMA_EN (0x1 << 2) 74 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 75 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 76 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 77 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 78 #define I2C_CONTROL_WRAPPER (0x1 << 0) 79 80 #define I2C_DRV_NAME "i2c-mt65xx" 81 82 enum DMA_REGS_OFFSET { 83 OFFSET_INT_FLAG = 0x0, 84 OFFSET_INT_EN = 0x04, 85 OFFSET_EN = 0x08, 86 OFFSET_RST = 0x0c, 87 OFFSET_CON = 0x18, 88 OFFSET_TX_MEM_ADDR = 0x1c, 89 OFFSET_RX_MEM_ADDR = 0x20, 90 OFFSET_TX_LEN = 0x24, 91 OFFSET_RX_LEN = 0x28, 92 OFFSET_TX_4G_MODE = 0x54, 93 OFFSET_RX_4G_MODE = 0x58, 94 }; 95 96 enum i2c_trans_st_rs { 97 I2C_TRANS_STOP = 0, 98 I2C_TRANS_REPEATED_START, 99 }; 100 101 enum mtk_trans_op { 102 I2C_MASTER_WR = 1, 103 I2C_MASTER_RD, 104 I2C_MASTER_WRRD, 105 }; 106 107 enum I2C_REGS_OFFSET { 108 OFFSET_DATA_PORT = 0x0, 109 OFFSET_SLAVE_ADDR = 0x04, 110 OFFSET_INTR_MASK = 0x08, 111 OFFSET_INTR_STAT = 0x0c, 112 OFFSET_CONTROL = 0x10, 113 OFFSET_TRANSFER_LEN = 0x14, 114 OFFSET_TRANSAC_LEN = 0x18, 115 OFFSET_DELAY_LEN = 0x1c, 116 OFFSET_TIMING = 0x20, 117 OFFSET_START = 0x24, 118 OFFSET_EXT_CONF = 0x28, 119 OFFSET_FIFO_STAT = 0x30, 120 OFFSET_FIFO_THRESH = 0x34, 121 OFFSET_FIFO_ADDR_CLR = 0x38, 122 OFFSET_IO_CONFIG = 0x40, 123 OFFSET_RSV_DEBUG = 0x44, 124 OFFSET_HS = 0x48, 125 OFFSET_SOFTRESET = 0x50, 126 OFFSET_DCM_EN = 0x54, 127 OFFSET_PATH_DIR = 0x60, 128 OFFSET_DEBUGSTAT = 0x64, 129 OFFSET_DEBUGCTRL = 0x68, 130 OFFSET_TRANSFER_LEN_AUX = 0x6c, 131 OFFSET_CLOCK_DIV = 0x70, 132 }; 133 134 struct mtk_i2c_compatible { 135 const struct i2c_adapter_quirks *quirks; 136 unsigned char pmic_i2c: 1; 137 unsigned char dcm: 1; 138 unsigned char auto_restart: 1; 139 unsigned char aux_len_reg: 1; 140 unsigned char support_33bits: 1; 141 unsigned char timing_adjust: 1; 142 }; 143 144 struct mtk_i2c { 145 struct i2c_adapter adap; /* i2c host adapter */ 146 struct device *dev; 147 struct completion msg_complete; 148 149 /* set in i2c probe */ 150 void __iomem *base; /* i2c base addr */ 151 void __iomem *pdmabase; /* dma base address*/ 152 struct clk *clk_main; /* main clock for i2c bus */ 153 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 154 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 155 bool have_pmic; /* can use i2c pins from PMIC */ 156 bool use_push_pull; /* IO config push-pull mode */ 157 158 u16 irq_stat; /* interrupt status */ 159 unsigned int clk_src_div; 160 unsigned int speed_hz; /* The speed in transfer */ 161 enum mtk_trans_op op; 162 u16 timing_reg; 163 u16 high_speed_reg; 164 unsigned char auto_restart; 165 bool ignore_restart_irq; 166 const struct mtk_i2c_compatible *dev_comp; 167 }; 168 169 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 170 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 171 .max_num_msgs = 1, 172 .max_write_len = 255, 173 .max_read_len = 255, 174 .max_comb_1st_msg_len = 255, 175 .max_comb_2nd_msg_len = 31, 176 }; 177 178 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 179 .max_num_msgs = 255, 180 }; 181 182 static const struct mtk_i2c_compatible mt2712_compat = { 183 .pmic_i2c = 0, 184 .dcm = 1, 185 .auto_restart = 1, 186 .aux_len_reg = 1, 187 .support_33bits = 1, 188 .timing_adjust = 1, 189 }; 190 191 static const struct mtk_i2c_compatible mt6577_compat = { 192 .quirks = &mt6577_i2c_quirks, 193 .pmic_i2c = 0, 194 .dcm = 1, 195 .auto_restart = 0, 196 .aux_len_reg = 0, 197 .support_33bits = 0, 198 .timing_adjust = 0, 199 }; 200 201 static const struct mtk_i2c_compatible mt6589_compat = { 202 .quirks = &mt6577_i2c_quirks, 203 .pmic_i2c = 1, 204 .dcm = 0, 205 .auto_restart = 0, 206 .aux_len_reg = 0, 207 .support_33bits = 0, 208 .timing_adjust = 0, 209 }; 210 211 static const struct mtk_i2c_compatible mt7622_compat = { 212 .quirks = &mt7622_i2c_quirks, 213 .pmic_i2c = 0, 214 .dcm = 1, 215 .auto_restart = 1, 216 .aux_len_reg = 1, 217 .support_33bits = 0, 218 .timing_adjust = 0, 219 }; 220 221 static const struct mtk_i2c_compatible mt8173_compat = { 222 .pmic_i2c = 0, 223 .dcm = 1, 224 .auto_restart = 1, 225 .aux_len_reg = 1, 226 .support_33bits = 1, 227 .timing_adjust = 0, 228 }; 229 230 static const struct of_device_id mtk_i2c_of_match[] = { 231 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 232 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 233 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 234 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 235 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 236 {} 237 }; 238 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 239 240 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 241 { 242 int ret; 243 244 ret = clk_prepare_enable(i2c->clk_dma); 245 if (ret) 246 return ret; 247 248 ret = clk_prepare_enable(i2c->clk_main); 249 if (ret) 250 goto err_main; 251 252 if (i2c->have_pmic) { 253 ret = clk_prepare_enable(i2c->clk_pmic); 254 if (ret) 255 goto err_pmic; 256 } 257 return 0; 258 259 err_pmic: 260 clk_disable_unprepare(i2c->clk_main); 261 err_main: 262 clk_disable_unprepare(i2c->clk_dma); 263 264 return ret; 265 } 266 267 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 268 { 269 if (i2c->have_pmic) 270 clk_disable_unprepare(i2c->clk_pmic); 271 272 clk_disable_unprepare(i2c->clk_main); 273 clk_disable_unprepare(i2c->clk_dma); 274 } 275 276 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 277 { 278 u16 control_reg; 279 280 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET); 281 282 /* Set ioconfig */ 283 if (i2c->use_push_pull) 284 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG); 285 else 286 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG); 287 288 if (i2c->dev_comp->dcm) 289 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN); 290 291 if (i2c->dev_comp->timing_adjust) 292 writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV); 293 294 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING); 295 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS); 296 297 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 298 if (i2c->have_pmic) 299 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR); 300 301 control_reg = I2C_CONTROL_ACKERR_DET_EN | 302 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 303 writew(control_reg, i2c->base + OFFSET_CONTROL); 304 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN); 305 306 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 307 udelay(50); 308 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 309 } 310 311 /* 312 * Calculate i2c port speed 313 * 314 * Hardware design: 315 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 316 * clock_div: fixed in hardware, but may be various in different SoCs 317 * 318 * The calculation want to pick the highest bus frequency that is still 319 * less than or equal to i2c->speed_hz. The calculation try to get 320 * sample_cnt and step_cn 321 */ 322 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 323 unsigned int target_speed, 324 unsigned int *timing_step_cnt, 325 unsigned int *timing_sample_cnt) 326 { 327 unsigned int step_cnt; 328 unsigned int sample_cnt; 329 unsigned int max_step_cnt; 330 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 331 unsigned int base_step_cnt; 332 unsigned int opt_div; 333 unsigned int best_mul; 334 unsigned int cnt_mul; 335 336 if (target_speed > MAX_HS_MODE_SPEED) 337 target_speed = MAX_HS_MODE_SPEED; 338 339 if (target_speed > MAX_FS_MODE_SPEED) 340 max_step_cnt = MAX_HS_STEP_CNT_DIV; 341 else 342 max_step_cnt = MAX_STEP_CNT_DIV; 343 344 base_step_cnt = max_step_cnt; 345 /* Find the best combination */ 346 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 347 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 348 349 /* Search for the best pair (sample_cnt, step_cnt) with 350 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 351 * 0 < step_cnt < max_step_cnt 352 * sample_cnt * step_cnt >= opt_div 353 * optimizing for sample_cnt * step_cnt being minimal 354 */ 355 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 356 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 357 cnt_mul = step_cnt * sample_cnt; 358 if (step_cnt > max_step_cnt) 359 continue; 360 361 if (cnt_mul < best_mul) { 362 best_mul = cnt_mul; 363 base_sample_cnt = sample_cnt; 364 base_step_cnt = step_cnt; 365 if (best_mul == opt_div) 366 break; 367 } 368 } 369 370 sample_cnt = base_sample_cnt; 371 step_cnt = base_step_cnt; 372 373 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 374 /* In this case, hardware can't support such 375 * low i2c_bus_freq 376 */ 377 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 378 return -EINVAL; 379 } 380 381 *timing_step_cnt = step_cnt - 1; 382 *timing_sample_cnt = sample_cnt - 1; 383 384 return 0; 385 } 386 387 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 388 { 389 unsigned int clk_src; 390 unsigned int step_cnt; 391 unsigned int sample_cnt; 392 unsigned int target_speed; 393 int ret; 394 395 clk_src = parent_clk / i2c->clk_src_div; 396 target_speed = i2c->speed_hz; 397 398 if (target_speed > MAX_FS_MODE_SPEED) { 399 /* Set master code speed register */ 400 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED, 401 &step_cnt, &sample_cnt); 402 if (ret < 0) 403 return ret; 404 405 i2c->timing_reg = (sample_cnt << 8) | step_cnt; 406 407 /* Set the high speed mode register */ 408 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 409 &step_cnt, &sample_cnt); 410 if (ret < 0) 411 return ret; 412 413 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 414 (sample_cnt << 12) | (step_cnt << 8); 415 } else { 416 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 417 &step_cnt, &sample_cnt); 418 if (ret < 0) 419 return ret; 420 421 i2c->timing_reg = (sample_cnt << 8) | step_cnt; 422 423 /* Disable the high speed transaction */ 424 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 425 } 426 427 return 0; 428 } 429 430 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr) 431 { 432 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG; 433 } 434 435 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 436 int num, int left_num) 437 { 438 u16 addr_reg; 439 u16 start_reg; 440 u16 control_reg; 441 u16 restart_flag = 0; 442 u32 reg_4g_mode; 443 dma_addr_t rpaddr = 0; 444 dma_addr_t wpaddr = 0; 445 int ret; 446 447 i2c->irq_stat = 0; 448 449 if (i2c->auto_restart) 450 restart_flag = I2C_RS_TRANSFER; 451 452 reinit_completion(&i2c->msg_complete); 453 454 control_reg = readw(i2c->base + OFFSET_CONTROL) & 455 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 456 if ((i2c->speed_hz > 400000) || (left_num >= 1)) 457 control_reg |= I2C_CONTROL_RS; 458 459 if (i2c->op == I2C_MASTER_WRRD) 460 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 461 462 writew(control_reg, i2c->base + OFFSET_CONTROL); 463 464 /* set start condition */ 465 if (i2c->speed_hz <= 100000) 466 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF); 467 else 468 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF); 469 470 addr_reg = i2c_8bit_addr_from_msg(msgs); 471 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR); 472 473 /* Clear interrupt status */ 474 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 475 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); 476 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR); 477 478 /* Enable interrupt */ 479 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 480 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK); 481 482 /* Set transfer and transaction len */ 483 if (i2c->op == I2C_MASTER_WRRD) { 484 if (i2c->dev_comp->aux_len_reg) { 485 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); 486 writew((msgs + 1)->len, i2c->base + 487 OFFSET_TRANSFER_LEN_AUX); 488 } else { 489 writew(msgs->len | ((msgs + 1)->len) << 8, 490 i2c->base + OFFSET_TRANSFER_LEN); 491 } 492 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN); 493 } else { 494 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); 495 writew(num, i2c->base + OFFSET_TRANSAC_LEN); 496 } 497 498 /* Prepare buffer data to start transfer */ 499 if (i2c->op == I2C_MASTER_RD) { 500 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 501 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); 502 rpaddr = dma_map_single(i2c->dev, msgs->buf, 503 msgs->len, DMA_FROM_DEVICE); 504 if (dma_mapping_error(i2c->dev, rpaddr)) 505 return -ENOMEM; 506 507 if (i2c->dev_comp->support_33bits) { 508 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 509 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 510 } 511 512 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 513 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 514 } else if (i2c->op == I2C_MASTER_WR) { 515 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 516 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); 517 wpaddr = dma_map_single(i2c->dev, msgs->buf, 518 msgs->len, DMA_TO_DEVICE); 519 if (dma_mapping_error(i2c->dev, wpaddr)) 520 return -ENOMEM; 521 522 if (i2c->dev_comp->support_33bits) { 523 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 524 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 525 } 526 527 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 528 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 529 } else { 530 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 531 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); 532 wpaddr = dma_map_single(i2c->dev, msgs->buf, 533 msgs->len, DMA_TO_DEVICE); 534 if (dma_mapping_error(i2c->dev, wpaddr)) 535 return -ENOMEM; 536 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf, 537 (msgs + 1)->len, 538 DMA_FROM_DEVICE); 539 if (dma_mapping_error(i2c->dev, rpaddr)) { 540 dma_unmap_single(i2c->dev, wpaddr, 541 msgs->len, DMA_TO_DEVICE); 542 return -ENOMEM; 543 } 544 545 if (i2c->dev_comp->support_33bits) { 546 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 547 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 548 549 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 550 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 551 } 552 553 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 554 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 555 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 556 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 557 } 558 559 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 560 561 if (!i2c->auto_restart) { 562 start_reg = I2C_TRANSAC_START; 563 } else { 564 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 565 if (left_num >= 1) 566 start_reg |= I2C_RS_MUL_CNFG; 567 } 568 writew(start_reg, i2c->base + OFFSET_START); 569 570 ret = wait_for_completion_timeout(&i2c->msg_complete, 571 i2c->adap.timeout); 572 573 /* Clear interrupt mask */ 574 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 575 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK); 576 577 if (i2c->op == I2C_MASTER_WR) { 578 dma_unmap_single(i2c->dev, wpaddr, 579 msgs->len, DMA_TO_DEVICE); 580 } else if (i2c->op == I2C_MASTER_RD) { 581 dma_unmap_single(i2c->dev, rpaddr, 582 msgs->len, DMA_FROM_DEVICE); 583 } else { 584 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 585 DMA_TO_DEVICE); 586 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 587 DMA_FROM_DEVICE); 588 } 589 590 if (ret == 0) { 591 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 592 mtk_i2c_init_hw(i2c); 593 return -ETIMEDOUT; 594 } 595 596 completion_done(&i2c->msg_complete); 597 598 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 599 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 600 mtk_i2c_init_hw(i2c); 601 return -ENXIO; 602 } 603 604 return 0; 605 } 606 607 static int mtk_i2c_transfer(struct i2c_adapter *adap, 608 struct i2c_msg msgs[], int num) 609 { 610 int ret; 611 int left_num = num; 612 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 613 614 ret = mtk_i2c_clock_enable(i2c); 615 if (ret) 616 return ret; 617 618 i2c->auto_restart = i2c->dev_comp->auto_restart; 619 620 /* checking if we can skip restart and optimize using WRRD mode */ 621 if (i2c->auto_restart && num == 2) { 622 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 623 msgs[0].addr == msgs[1].addr) { 624 i2c->auto_restart = 0; 625 } 626 } 627 628 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED) 629 /* ignore the first restart irq after the master code, 630 * otherwise the first transfer will be discarded. 631 */ 632 i2c->ignore_restart_irq = true; 633 else 634 i2c->ignore_restart_irq = false; 635 636 while (left_num--) { 637 if (!msgs->buf) { 638 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 639 ret = -EINVAL; 640 goto err_exit; 641 } 642 643 if (msgs->flags & I2C_M_RD) 644 i2c->op = I2C_MASTER_RD; 645 else 646 i2c->op = I2C_MASTER_WR; 647 648 if (!i2c->auto_restart) { 649 if (num > 1) { 650 /* combined two messages into one transaction */ 651 i2c->op = I2C_MASTER_WRRD; 652 left_num--; 653 } 654 } 655 656 /* always use DMA mode. */ 657 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 658 if (ret < 0) 659 goto err_exit; 660 661 msgs++; 662 } 663 /* the return value is number of executed messages */ 664 ret = num; 665 666 err_exit: 667 mtk_i2c_clock_disable(i2c); 668 return ret; 669 } 670 671 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 672 { 673 struct mtk_i2c *i2c = dev_id; 674 u16 restart_flag = 0; 675 u16 intr_stat; 676 677 if (i2c->auto_restart) 678 restart_flag = I2C_RS_TRANSFER; 679 680 intr_stat = readw(i2c->base + OFFSET_INTR_STAT); 681 writew(intr_stat, i2c->base + OFFSET_INTR_STAT); 682 683 /* 684 * when occurs ack error, i2c controller generate two interrupts 685 * first is the ack error interrupt, then the complete interrupt 686 * i2c->irq_stat need keep the two interrupt value. 687 */ 688 i2c->irq_stat |= intr_stat; 689 690 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 691 i2c->ignore_restart_irq = false; 692 i2c->irq_stat = 0; 693 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START, 694 i2c->base + OFFSET_START); 695 } else { 696 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 697 complete(&i2c->msg_complete); 698 } 699 700 return IRQ_HANDLED; 701 } 702 703 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 704 { 705 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 706 } 707 708 static const struct i2c_algorithm mtk_i2c_algorithm = { 709 .master_xfer = mtk_i2c_transfer, 710 .functionality = mtk_i2c_functionality, 711 }; 712 713 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 714 { 715 int ret; 716 717 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 718 if (ret < 0) 719 i2c->speed_hz = I2C_DEFAULT_SPEED; 720 721 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 722 if (ret < 0) 723 return ret; 724 725 if (i2c->clk_src_div == 0) 726 return -EINVAL; 727 728 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 729 i2c->use_push_pull = 730 of_property_read_bool(np, "mediatek,use-push-pull"); 731 732 return 0; 733 } 734 735 static int mtk_i2c_probe(struct platform_device *pdev) 736 { 737 const struct of_device_id *of_id; 738 int ret = 0; 739 struct mtk_i2c *i2c; 740 struct clk *clk; 741 struct resource *res; 742 int irq; 743 744 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 745 if (!i2c) 746 return -ENOMEM; 747 748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 749 i2c->base = devm_ioremap_resource(&pdev->dev, res); 750 if (IS_ERR(i2c->base)) 751 return PTR_ERR(i2c->base); 752 753 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 754 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 755 if (IS_ERR(i2c->pdmabase)) 756 return PTR_ERR(i2c->pdmabase); 757 758 irq = platform_get_irq(pdev, 0); 759 if (irq <= 0) 760 return irq; 761 762 init_completion(&i2c->msg_complete); 763 764 of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node); 765 if (!of_id) 766 return -EINVAL; 767 768 i2c->dev_comp = of_id->data; 769 i2c->adap.dev.of_node = pdev->dev.of_node; 770 i2c->dev = &pdev->dev; 771 i2c->adap.dev.parent = &pdev->dev; 772 i2c->adap.owner = THIS_MODULE; 773 i2c->adap.algo = &mtk_i2c_algorithm; 774 i2c->adap.quirks = i2c->dev_comp->quirks; 775 i2c->adap.timeout = 2 * HZ; 776 i2c->adap.retries = 1; 777 778 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 779 if (ret) 780 return -EINVAL; 781 782 if (i2c->dev_comp->timing_adjust) 783 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV; 784 785 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 786 return -EINVAL; 787 788 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 789 if (IS_ERR(i2c->clk_main)) { 790 dev_err(&pdev->dev, "cannot get main clock\n"); 791 return PTR_ERR(i2c->clk_main); 792 } 793 794 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 795 if (IS_ERR(i2c->clk_dma)) { 796 dev_err(&pdev->dev, "cannot get dma clock\n"); 797 return PTR_ERR(i2c->clk_dma); 798 } 799 800 clk = i2c->clk_main; 801 if (i2c->have_pmic) { 802 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 803 if (IS_ERR(i2c->clk_pmic)) { 804 dev_err(&pdev->dev, "cannot get pmic clock\n"); 805 return PTR_ERR(i2c->clk_pmic); 806 } 807 clk = i2c->clk_pmic; 808 } 809 810 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 811 812 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 813 if (ret) { 814 dev_err(&pdev->dev, "Failed to set the speed.\n"); 815 return -EINVAL; 816 } 817 818 if (i2c->dev_comp->support_33bits) { 819 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33)); 820 if (ret) { 821 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 822 return ret; 823 } 824 } 825 826 ret = mtk_i2c_clock_enable(i2c); 827 if (ret) { 828 dev_err(&pdev->dev, "clock enable failed!\n"); 829 return ret; 830 } 831 mtk_i2c_init_hw(i2c); 832 mtk_i2c_clock_disable(i2c); 833 834 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 835 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 836 if (ret < 0) { 837 dev_err(&pdev->dev, 838 "Request I2C IRQ %d fail\n", irq); 839 return ret; 840 } 841 842 i2c_set_adapdata(&i2c->adap, i2c); 843 ret = i2c_add_adapter(&i2c->adap); 844 if (ret) 845 return ret; 846 847 platform_set_drvdata(pdev, i2c); 848 849 return 0; 850 } 851 852 static int mtk_i2c_remove(struct platform_device *pdev) 853 { 854 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 855 856 i2c_del_adapter(&i2c->adap); 857 858 return 0; 859 } 860 861 #ifdef CONFIG_PM_SLEEP 862 static int mtk_i2c_resume(struct device *dev) 863 { 864 int ret; 865 struct mtk_i2c *i2c = dev_get_drvdata(dev); 866 867 ret = mtk_i2c_clock_enable(i2c); 868 if (ret) { 869 dev_err(dev, "clock enable failed!\n"); 870 return ret; 871 } 872 873 mtk_i2c_init_hw(i2c); 874 875 mtk_i2c_clock_disable(i2c); 876 877 return 0; 878 } 879 #endif 880 881 static const struct dev_pm_ops mtk_i2c_pm = { 882 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume) 883 }; 884 885 static struct platform_driver mtk_i2c_driver = { 886 .probe = mtk_i2c_probe, 887 .remove = mtk_i2c_remove, 888 .driver = { 889 .name = I2C_DRV_NAME, 890 .pm = &mtk_i2c_pm, 891 .of_match_table = of_match_ptr(mtk_i2c_of_match), 892 }, 893 }; 894 895 module_platform_driver(mtk_i2c_driver); 896 897 MODULE_LICENSE("GPL v2"); 898 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 899 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 900