1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 30 #define I2C_RS_TRANSFER (1 << 4) 31 #define I2C_ARB_LOST (1 << 3) 32 #define I2C_HS_NACKERR (1 << 2) 33 #define I2C_ACKERR (1 << 1) 34 #define I2C_TRANSAC_COMP (1 << 0) 35 #define I2C_TRANSAC_START (1 << 0) 36 #define I2C_RS_MUL_CNFG (1 << 15) 37 #define I2C_RS_MUL_TRIG (1 << 14) 38 #define I2C_DCM_DISABLE 0x0000 39 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 40 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 41 #define I2C_SOFT_RST 0x0001 42 #define I2C_HANDSHAKE_RST 0x0020 43 #define I2C_FIFO_ADDR_CLR 0x0001 44 #define I2C_DELAY_LEN 0x0002 45 #define I2C_ST_START_CON 0x8001 46 #define I2C_FS_START_CON 0x1800 47 #define I2C_TIME_CLR_VALUE 0x0000 48 #define I2C_TIME_DEFAULT_VALUE 0x0003 49 #define I2C_WRRD_TRANAC_VALUE 0x0002 50 #define I2C_RD_TRANAC_VALUE 0x0001 51 #define I2C_SCL_MIS_COMP_VALUE 0x0000 52 #define I2C_CHN_CLR_FLAG 0x0000 53 #define I2C_RELIABILITY 0x0010 54 #define I2C_DMAACK_ENABLE 0x0008 55 56 #define I2C_DMA_CON_TX 0x0000 57 #define I2C_DMA_CON_RX 0x0001 58 #define I2C_DMA_ASYNC_MODE 0x0004 59 #define I2C_DMA_SKIP_CONFIG 0x0010 60 #define I2C_DMA_DIR_CHANGE 0x0200 61 #define I2C_DMA_START_EN 0x0001 62 #define I2C_DMA_INT_FLAG_NONE 0x0000 63 #define I2C_DMA_CLR_FLAG 0x0000 64 #define I2C_DMA_WARM_RST 0x0001 65 #define I2C_DMA_HARD_RST 0x0002 66 #define I2C_DMA_HANDSHAKE_RST 0x0004 67 68 #define MAX_SAMPLE_CNT_DIV 8 69 #define MAX_STEP_CNT_DIV 64 70 #define MAX_CLOCK_DIV_8BITS 256 71 #define MAX_CLOCK_DIV_5BITS 32 72 #define MAX_HS_STEP_CNT_DIV 8 73 #define I2C_STANDARD_MODE_BUFFER (1000 / 3) 74 #define I2C_FAST_MODE_BUFFER (300 / 3) 75 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) 76 77 #define I2C_CONTROL_RS (0x1 << 1) 78 #define I2C_CONTROL_DMA_EN (0x1 << 2) 79 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 80 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 81 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 82 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 83 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 84 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 85 #define I2C_CONTROL_WRAPPER (0x1 << 0) 86 87 #define I2C_DRV_NAME "i2c-mt65xx" 88 89 /** 90 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C 91 * 92 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus 93 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA 94 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC 95 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c 96 * @I2C_MT65XX_CLK_MAX: Number of supported clocks 97 */ 98 enum i2c_mt65xx_clks { 99 I2C_MT65XX_CLK_MAIN = 0, 100 I2C_MT65XX_CLK_DMA, 101 I2C_MT65XX_CLK_PMIC, 102 I2C_MT65XX_CLK_ARB, 103 I2C_MT65XX_CLK_MAX 104 }; 105 106 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { 107 "main", "dma", "pmic", "arb" 108 }; 109 110 enum DMA_REGS_OFFSET { 111 OFFSET_INT_FLAG = 0x0, 112 OFFSET_INT_EN = 0x04, 113 OFFSET_EN = 0x08, 114 OFFSET_RST = 0x0c, 115 OFFSET_CON = 0x18, 116 OFFSET_TX_MEM_ADDR = 0x1c, 117 OFFSET_RX_MEM_ADDR = 0x20, 118 OFFSET_TX_LEN = 0x24, 119 OFFSET_RX_LEN = 0x28, 120 OFFSET_TX_4G_MODE = 0x54, 121 OFFSET_RX_4G_MODE = 0x58, 122 }; 123 124 enum i2c_trans_st_rs { 125 I2C_TRANS_STOP = 0, 126 I2C_TRANS_REPEATED_START, 127 }; 128 129 enum mtk_trans_op { 130 I2C_MASTER_WR = 1, 131 I2C_MASTER_RD, 132 I2C_MASTER_WRRD, 133 }; 134 135 enum I2C_REGS_OFFSET { 136 OFFSET_DATA_PORT, 137 OFFSET_SLAVE_ADDR, 138 OFFSET_INTR_MASK, 139 OFFSET_INTR_STAT, 140 OFFSET_CONTROL, 141 OFFSET_TRANSFER_LEN, 142 OFFSET_TRANSAC_LEN, 143 OFFSET_DELAY_LEN, 144 OFFSET_TIMING, 145 OFFSET_START, 146 OFFSET_EXT_CONF, 147 OFFSET_FIFO_STAT, 148 OFFSET_FIFO_THRESH, 149 OFFSET_FIFO_ADDR_CLR, 150 OFFSET_IO_CONFIG, 151 OFFSET_RSV_DEBUG, 152 OFFSET_HS, 153 OFFSET_SOFTRESET, 154 OFFSET_DCM_EN, 155 OFFSET_MULTI_DMA, 156 OFFSET_PATH_DIR, 157 OFFSET_DEBUGSTAT, 158 OFFSET_DEBUGCTRL, 159 OFFSET_TRANSFER_LEN_AUX, 160 OFFSET_CLOCK_DIV, 161 OFFSET_LTIMING, 162 OFFSET_SCL_HIGH_LOW_RATIO, 163 OFFSET_HS_SCL_HIGH_LOW_RATIO, 164 OFFSET_SCL_MIS_COMP_POINT, 165 OFFSET_STA_STO_AC_TIMING, 166 OFFSET_HS_STA_STO_AC_TIMING, 167 OFFSET_SDA_TIMING, 168 }; 169 170 static const u16 mt_i2c_regs_v1[] = { 171 [OFFSET_DATA_PORT] = 0x0, 172 [OFFSET_SLAVE_ADDR] = 0x4, 173 [OFFSET_INTR_MASK] = 0x8, 174 [OFFSET_INTR_STAT] = 0xc, 175 [OFFSET_CONTROL] = 0x10, 176 [OFFSET_TRANSFER_LEN] = 0x14, 177 [OFFSET_TRANSAC_LEN] = 0x18, 178 [OFFSET_DELAY_LEN] = 0x1c, 179 [OFFSET_TIMING] = 0x20, 180 [OFFSET_START] = 0x24, 181 [OFFSET_EXT_CONF] = 0x28, 182 [OFFSET_FIFO_STAT] = 0x30, 183 [OFFSET_FIFO_THRESH] = 0x34, 184 [OFFSET_FIFO_ADDR_CLR] = 0x38, 185 [OFFSET_IO_CONFIG] = 0x40, 186 [OFFSET_RSV_DEBUG] = 0x44, 187 [OFFSET_HS] = 0x48, 188 [OFFSET_SOFTRESET] = 0x50, 189 [OFFSET_DCM_EN] = 0x54, 190 [OFFSET_PATH_DIR] = 0x60, 191 [OFFSET_DEBUGSTAT] = 0x64, 192 [OFFSET_DEBUGCTRL] = 0x68, 193 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 194 [OFFSET_CLOCK_DIV] = 0x70, 195 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 196 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 197 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 198 [OFFSET_STA_STO_AC_TIMING] = 0x80, 199 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 200 [OFFSET_SDA_TIMING] = 0x88, 201 }; 202 203 static const u16 mt_i2c_regs_v2[] = { 204 [OFFSET_DATA_PORT] = 0x0, 205 [OFFSET_SLAVE_ADDR] = 0x4, 206 [OFFSET_INTR_MASK] = 0x8, 207 [OFFSET_INTR_STAT] = 0xc, 208 [OFFSET_CONTROL] = 0x10, 209 [OFFSET_TRANSFER_LEN] = 0x14, 210 [OFFSET_TRANSAC_LEN] = 0x18, 211 [OFFSET_DELAY_LEN] = 0x1c, 212 [OFFSET_TIMING] = 0x20, 213 [OFFSET_START] = 0x24, 214 [OFFSET_EXT_CONF] = 0x28, 215 [OFFSET_LTIMING] = 0x2c, 216 [OFFSET_HS] = 0x30, 217 [OFFSET_IO_CONFIG] = 0x34, 218 [OFFSET_FIFO_ADDR_CLR] = 0x38, 219 [OFFSET_SDA_TIMING] = 0x3c, 220 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 221 [OFFSET_CLOCK_DIV] = 0x48, 222 [OFFSET_SOFTRESET] = 0x50, 223 [OFFSET_MULTI_DMA] = 0x8c, 224 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 225 [OFFSET_DEBUGSTAT] = 0xe4, 226 [OFFSET_DEBUGCTRL] = 0xe8, 227 [OFFSET_FIFO_STAT] = 0xf4, 228 [OFFSET_FIFO_THRESH] = 0xf8, 229 [OFFSET_DCM_EN] = 0xf88, 230 }; 231 232 static const u16 mt_i2c_regs_v3[] = { 233 [OFFSET_DATA_PORT] = 0x0, 234 [OFFSET_INTR_MASK] = 0x8, 235 [OFFSET_INTR_STAT] = 0xc, 236 [OFFSET_CONTROL] = 0x10, 237 [OFFSET_TRANSFER_LEN] = 0x14, 238 [OFFSET_TRANSAC_LEN] = 0x18, 239 [OFFSET_DELAY_LEN] = 0x1c, 240 [OFFSET_TIMING] = 0x20, 241 [OFFSET_START] = 0x24, 242 [OFFSET_EXT_CONF] = 0x28, 243 [OFFSET_LTIMING] = 0x2c, 244 [OFFSET_HS] = 0x30, 245 [OFFSET_IO_CONFIG] = 0x34, 246 [OFFSET_FIFO_ADDR_CLR] = 0x38, 247 [OFFSET_SDA_TIMING] = 0x3c, 248 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 249 [OFFSET_CLOCK_DIV] = 0x48, 250 [OFFSET_SOFTRESET] = 0x50, 251 [OFFSET_MULTI_DMA] = 0x8c, 252 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 253 [OFFSET_SLAVE_ADDR] = 0x94, 254 [OFFSET_DEBUGSTAT] = 0xe4, 255 [OFFSET_DEBUGCTRL] = 0xe8, 256 [OFFSET_FIFO_STAT] = 0xf4, 257 [OFFSET_FIFO_THRESH] = 0xf8, 258 [OFFSET_DCM_EN] = 0xf88, 259 }; 260 261 struct mtk_i2c_compatible { 262 const struct i2c_adapter_quirks *quirks; 263 const u16 *regs; 264 unsigned char pmic_i2c: 1; 265 unsigned char dcm: 1; 266 unsigned char auto_restart: 1; 267 unsigned char aux_len_reg: 1; 268 unsigned char timing_adjust: 1; 269 unsigned char dma_sync: 1; 270 unsigned char ltiming_adjust: 1; 271 unsigned char apdma_sync: 1; 272 unsigned char max_dma_support; 273 }; 274 275 struct mtk_i2c_ac_timing { 276 u16 htiming; 277 u16 ltiming; 278 u16 hs; 279 u16 ext; 280 u16 inter_clk_div; 281 u16 scl_hl_ratio; 282 u16 hs_scl_hl_ratio; 283 u16 sta_stop; 284 u16 hs_sta_stop; 285 u16 sda_timing; 286 }; 287 288 struct mtk_i2c { 289 struct i2c_adapter adap; /* i2c host adapter */ 290 struct device *dev; 291 struct completion msg_complete; 292 struct i2c_timings timing_info; 293 294 /* set in i2c probe */ 295 void __iomem *base; /* i2c base addr */ 296 void __iomem *pdmabase; /* dma base address*/ 297 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ 298 bool have_pmic; /* can use i2c pins from PMIC */ 299 bool use_push_pull; /* IO config push-pull mode */ 300 301 u16 irq_stat; /* interrupt status */ 302 unsigned int clk_src_div; 303 unsigned int speed_hz; /* The speed in transfer */ 304 enum mtk_trans_op op; 305 u16 timing_reg; 306 u16 high_speed_reg; 307 u16 ltiming_reg; 308 unsigned char auto_restart; 309 bool ignore_restart_irq; 310 struct mtk_i2c_ac_timing ac_timing; 311 const struct mtk_i2c_compatible *dev_comp; 312 }; 313 314 /** 315 * struct i2c_spec_values: 316 * @min_low_ns: min LOW period of the SCL clock 317 * @min_su_sta_ns: min set-up time for a repeated START condition 318 * @max_hd_dat_ns: max data hold time 319 * @min_su_dat_ns: min data set-up time 320 */ 321 struct i2c_spec_values { 322 unsigned int min_low_ns; 323 unsigned int min_su_sta_ns; 324 unsigned int max_hd_dat_ns; 325 unsigned int min_su_dat_ns; 326 }; 327 328 static const struct i2c_spec_values standard_mode_spec = { 329 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 330 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 331 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 332 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 333 }; 334 335 static const struct i2c_spec_values fast_mode_spec = { 336 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 337 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 338 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 339 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 340 }; 341 342 static const struct i2c_spec_values fast_mode_plus_spec = { 343 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 344 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 345 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 346 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 347 }; 348 349 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 350 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 351 .max_num_msgs = 1, 352 .max_write_len = 255, 353 .max_read_len = 255, 354 .max_comb_1st_msg_len = 255, 355 .max_comb_2nd_msg_len = 31, 356 }; 357 358 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 359 .max_num_msgs = 255, 360 }; 361 362 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 363 .flags = I2C_AQ_NO_ZERO_LEN, 364 }; 365 366 static const struct mtk_i2c_compatible mt2712_compat = { 367 .regs = mt_i2c_regs_v1, 368 .pmic_i2c = 0, 369 .dcm = 1, 370 .auto_restart = 1, 371 .aux_len_reg = 1, 372 .timing_adjust = 1, 373 .dma_sync = 0, 374 .ltiming_adjust = 0, 375 .apdma_sync = 0, 376 .max_dma_support = 33, 377 }; 378 379 static const struct mtk_i2c_compatible mt6577_compat = { 380 .quirks = &mt6577_i2c_quirks, 381 .regs = mt_i2c_regs_v1, 382 .pmic_i2c = 0, 383 .dcm = 1, 384 .auto_restart = 0, 385 .aux_len_reg = 0, 386 .timing_adjust = 0, 387 .dma_sync = 0, 388 .ltiming_adjust = 0, 389 .apdma_sync = 0, 390 .max_dma_support = 32, 391 }; 392 393 static const struct mtk_i2c_compatible mt6589_compat = { 394 .quirks = &mt6577_i2c_quirks, 395 .regs = mt_i2c_regs_v1, 396 .pmic_i2c = 1, 397 .dcm = 0, 398 .auto_restart = 0, 399 .aux_len_reg = 0, 400 .timing_adjust = 0, 401 .dma_sync = 0, 402 .ltiming_adjust = 0, 403 .apdma_sync = 0, 404 .max_dma_support = 32, 405 }; 406 407 static const struct mtk_i2c_compatible mt7622_compat = { 408 .quirks = &mt7622_i2c_quirks, 409 .regs = mt_i2c_regs_v1, 410 .pmic_i2c = 0, 411 .dcm = 1, 412 .auto_restart = 1, 413 .aux_len_reg = 1, 414 .timing_adjust = 0, 415 .dma_sync = 0, 416 .ltiming_adjust = 0, 417 .apdma_sync = 0, 418 .max_dma_support = 32, 419 }; 420 421 static const struct mtk_i2c_compatible mt8168_compat = { 422 .regs = mt_i2c_regs_v1, 423 .pmic_i2c = 0, 424 .dcm = 1, 425 .auto_restart = 1, 426 .aux_len_reg = 1, 427 .timing_adjust = 1, 428 .dma_sync = 1, 429 .ltiming_adjust = 0, 430 .apdma_sync = 0, 431 .max_dma_support = 33, 432 }; 433 434 static const struct mtk_i2c_compatible mt7986_compat = { 435 .quirks = &mt7622_i2c_quirks, 436 .regs = mt_i2c_regs_v1, 437 .pmic_i2c = 0, 438 .dcm = 1, 439 .auto_restart = 1, 440 .aux_len_reg = 1, 441 .timing_adjust = 0, 442 .dma_sync = 1, 443 .ltiming_adjust = 0, 444 .max_dma_support = 32, 445 }; 446 447 static const struct mtk_i2c_compatible mt8173_compat = { 448 .regs = mt_i2c_regs_v1, 449 .pmic_i2c = 0, 450 .dcm = 1, 451 .auto_restart = 1, 452 .aux_len_reg = 1, 453 .timing_adjust = 0, 454 .dma_sync = 0, 455 .ltiming_adjust = 0, 456 .apdma_sync = 0, 457 .max_dma_support = 33, 458 }; 459 460 static const struct mtk_i2c_compatible mt8183_compat = { 461 .quirks = &mt8183_i2c_quirks, 462 .regs = mt_i2c_regs_v2, 463 .pmic_i2c = 0, 464 .dcm = 0, 465 .auto_restart = 1, 466 .aux_len_reg = 1, 467 .timing_adjust = 1, 468 .dma_sync = 1, 469 .ltiming_adjust = 1, 470 .apdma_sync = 0, 471 .max_dma_support = 33, 472 }; 473 474 static const struct mtk_i2c_compatible mt8186_compat = { 475 .regs = mt_i2c_regs_v2, 476 .pmic_i2c = 0, 477 .dcm = 0, 478 .auto_restart = 1, 479 .aux_len_reg = 1, 480 .timing_adjust = 1, 481 .dma_sync = 0, 482 .ltiming_adjust = 1, 483 .apdma_sync = 0, 484 .max_dma_support = 36, 485 }; 486 487 static const struct mtk_i2c_compatible mt8188_compat = { 488 .regs = mt_i2c_regs_v3, 489 .pmic_i2c = 0, 490 .dcm = 0, 491 .auto_restart = 1, 492 .aux_len_reg = 1, 493 .timing_adjust = 1, 494 .dma_sync = 0, 495 .ltiming_adjust = 1, 496 .apdma_sync = 1, 497 .max_dma_support = 36, 498 }; 499 500 static const struct mtk_i2c_compatible mt8192_compat = { 501 .quirks = &mt8183_i2c_quirks, 502 .regs = mt_i2c_regs_v2, 503 .pmic_i2c = 0, 504 .dcm = 0, 505 .auto_restart = 1, 506 .aux_len_reg = 1, 507 .timing_adjust = 1, 508 .dma_sync = 1, 509 .ltiming_adjust = 1, 510 .apdma_sync = 1, 511 .max_dma_support = 36, 512 }; 513 514 static const struct of_device_id mtk_i2c_of_match[] = { 515 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 516 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 517 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 518 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 519 { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, 520 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, 521 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 522 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 523 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, 524 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, 525 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 526 {} 527 }; 528 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 529 530 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 531 { 532 return readw(i2c->base + i2c->dev_comp->regs[reg]); 533 } 534 535 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 536 enum I2C_REGS_OFFSET reg) 537 { 538 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 539 } 540 541 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 542 { 543 u16 control_reg; 544 u16 intr_stat_reg; 545 u16 ext_conf_val; 546 547 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); 548 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 549 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); 550 551 if (i2c->dev_comp->apdma_sync) { 552 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 553 udelay(10); 554 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 555 udelay(10); 556 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 557 i2c->pdmabase + OFFSET_RST); 558 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 559 OFFSET_SOFTRESET); 560 udelay(10); 561 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 562 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 563 } else { 564 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 565 udelay(50); 566 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 567 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 568 } 569 570 /* Set ioconfig */ 571 if (i2c->use_push_pull) 572 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 573 else 574 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 575 576 if (i2c->dev_comp->dcm) 577 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 578 579 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 580 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 581 if (i2c->dev_comp->ltiming_adjust) 582 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 583 584 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 585 ext_conf_val = I2C_ST_START_CON; 586 else 587 ext_conf_val = I2C_FS_START_CON; 588 589 if (i2c->dev_comp->timing_adjust) { 590 ext_conf_val = i2c->ac_timing.ext; 591 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 592 OFFSET_CLOCK_DIV); 593 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 594 OFFSET_SCL_MIS_COMP_POINT); 595 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 596 OFFSET_SDA_TIMING); 597 598 if (i2c->dev_comp->ltiming_adjust) { 599 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 600 OFFSET_TIMING); 601 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 602 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 603 OFFSET_LTIMING); 604 } else { 605 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 606 OFFSET_SCL_HIGH_LOW_RATIO); 607 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 608 OFFSET_HS_SCL_HIGH_LOW_RATIO); 609 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 610 OFFSET_STA_STO_AC_TIMING); 611 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 612 OFFSET_HS_STA_STO_AC_TIMING); 613 } 614 } 615 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); 616 617 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 618 if (i2c->have_pmic) 619 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 620 621 control_reg = I2C_CONTROL_ACKERR_DET_EN | 622 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 623 if (i2c->dev_comp->dma_sync) 624 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 625 626 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 627 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 628 } 629 630 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 631 { 632 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 633 return &standard_mode_spec; 634 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 635 return &fast_mode_spec; 636 else 637 return &fast_mode_plus_spec; 638 } 639 640 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 641 { 642 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 643 return MAX_HS_STEP_CNT_DIV; 644 else 645 return MAX_STEP_CNT_DIV; 646 } 647 648 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, 649 unsigned int sample_cnt) 650 { 651 int clk_div_restri = 0; 652 653 if (i2c->dev_comp->ltiming_adjust == 0) 654 return 0; 655 656 if (sample_cnt == 1) { 657 if (i2c->ac_timing.inter_clk_div == 0) 658 clk_div_restri = 0; 659 else 660 clk_div_restri = 1; 661 } else { 662 if (i2c->ac_timing.inter_clk_div == 0) 663 clk_div_restri = -1; 664 else if (i2c->ac_timing.inter_clk_div == 1) 665 clk_div_restri = 0; 666 else 667 clk_div_restri = 1; 668 } 669 670 return clk_div_restri; 671 } 672 673 /* 674 * Check and Calculate i2c ac-timing 675 * 676 * Hardware design: 677 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 678 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 679 * 680 * Sample_ns is rounded down for xxx_cnt_div would be greater 681 * than the smallest spec. 682 * The sda_timing is chosen as the middle value between 683 * the largest and smallest. 684 */ 685 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 686 unsigned int clk_src, 687 unsigned int check_speed, 688 unsigned int step_cnt, 689 unsigned int sample_cnt) 690 { 691 const struct i2c_spec_values *spec; 692 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 693 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 694 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 695 clk_src); 696 697 if (!i2c->dev_comp->timing_adjust) 698 return 0; 699 700 if (i2c->dev_comp->ltiming_adjust) 701 max_sta_cnt = 0x100; 702 703 spec = mtk_i2c_get_spec(check_speed); 704 705 if (i2c->dev_comp->ltiming_adjust) 706 clk_ns = 1000000000 / clk_src; 707 else 708 clk_ns = sample_ns / 2; 709 710 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 711 i2c->timing_info.scl_int_delay_ns, clk_ns); 712 if (su_sta_cnt > max_sta_cnt) 713 return -1; 714 715 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 716 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 717 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 718 if (low_cnt > step_cnt) { 719 high_cnt = 2 * step_cnt - low_cnt; 720 } else { 721 high_cnt = step_cnt; 722 low_cnt = step_cnt; 723 } 724 } else { 725 return -2; 726 } 727 728 sda_max = spec->max_hd_dat_ns / sample_ns; 729 if (sda_max > low_cnt) 730 sda_max = 0; 731 732 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 733 if (sda_min < low_cnt) 734 sda_min = 0; 735 736 if (sda_min > sda_max) 737 return -3; 738 739 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 740 if (i2c->dev_comp->ltiming_adjust) { 741 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 742 (sample_cnt << 12) | (high_cnt << 8); 743 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 744 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 745 (low_cnt << 9); 746 i2c->ac_timing.ext &= ~GENMASK(7, 1); 747 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 748 } else { 749 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 750 (high_cnt << 6) | low_cnt; 751 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 752 su_sta_cnt; 753 } 754 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 755 i2c->ac_timing.sda_timing |= (1 << 12) | 756 ((sda_max + sda_min) / 2) << 6; 757 } else { 758 if (i2c->dev_comp->ltiming_adjust) { 759 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 760 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 761 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 762 } else { 763 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 764 (high_cnt << 6) | low_cnt; 765 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 766 su_sta_cnt; 767 } 768 769 i2c->ac_timing.sda_timing = (1 << 12) | 770 (sda_max + sda_min) / 2; 771 } 772 773 return 0; 774 } 775 776 /* 777 * Calculate i2c port speed 778 * 779 * Hardware design: 780 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 781 * clock_div: fixed in hardware, but may be various in different SoCs 782 * 783 * The calculation want to pick the highest bus frequency that is still 784 * less than or equal to i2c->speed_hz. The calculation try to get 785 * sample_cnt and step_cn 786 */ 787 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 788 unsigned int target_speed, 789 unsigned int *timing_step_cnt, 790 unsigned int *timing_sample_cnt) 791 { 792 unsigned int step_cnt; 793 unsigned int sample_cnt; 794 unsigned int max_step_cnt; 795 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 796 unsigned int base_step_cnt; 797 unsigned int opt_div; 798 unsigned int best_mul; 799 unsigned int cnt_mul; 800 int ret = -EINVAL; 801 int clk_div_restri = 0; 802 803 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 804 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 805 806 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 807 base_step_cnt = max_step_cnt; 808 /* Find the best combination */ 809 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 810 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 811 812 /* Search for the best pair (sample_cnt, step_cnt) with 813 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 814 * 0 < step_cnt < max_step_cnt 815 * sample_cnt * step_cnt >= opt_div 816 * optimizing for sample_cnt * step_cnt being minimal 817 */ 818 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 819 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); 820 step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); 821 cnt_mul = step_cnt * sample_cnt; 822 if (step_cnt > max_step_cnt) 823 continue; 824 825 if (cnt_mul < best_mul) { 826 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 827 target_speed, step_cnt - 1, sample_cnt - 1); 828 if (ret) 829 continue; 830 831 best_mul = cnt_mul; 832 base_sample_cnt = sample_cnt; 833 base_step_cnt = step_cnt; 834 if (best_mul == (opt_div + clk_div_restri)) 835 break; 836 } 837 } 838 839 if (ret) 840 return -EINVAL; 841 842 sample_cnt = base_sample_cnt; 843 step_cnt = base_step_cnt; 844 845 if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > 846 target_speed) { 847 /* In this case, hardware can't support such 848 * low i2c_bus_freq 849 */ 850 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 851 return -EINVAL; 852 } 853 854 *timing_step_cnt = step_cnt - 1; 855 *timing_sample_cnt = sample_cnt - 1; 856 857 return 0; 858 } 859 860 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 861 { 862 unsigned int clk_src; 863 unsigned int step_cnt; 864 unsigned int sample_cnt; 865 unsigned int l_step_cnt; 866 unsigned int l_sample_cnt; 867 unsigned int target_speed; 868 unsigned int clk_div; 869 unsigned int max_clk_div; 870 int ret; 871 872 target_speed = i2c->speed_hz; 873 parent_clk /= i2c->clk_src_div; 874 875 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) 876 max_clk_div = MAX_CLOCK_DIV_5BITS; 877 else if (i2c->dev_comp->timing_adjust) 878 max_clk_div = MAX_CLOCK_DIV_8BITS; 879 else 880 max_clk_div = 1; 881 882 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 883 clk_src = parent_clk / clk_div; 884 i2c->ac_timing.inter_clk_div = clk_div - 1; 885 886 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 887 /* Set master code speed register */ 888 ret = mtk_i2c_calculate_speed(i2c, clk_src, 889 I2C_MAX_FAST_MODE_FREQ, 890 &l_step_cnt, 891 &l_sample_cnt); 892 if (ret < 0) 893 continue; 894 895 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 896 897 /* Set the high speed mode register */ 898 ret = mtk_i2c_calculate_speed(i2c, clk_src, 899 target_speed, &step_cnt, 900 &sample_cnt); 901 if (ret < 0) 902 continue; 903 904 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 905 (sample_cnt << 12) | (step_cnt << 8); 906 907 if (i2c->dev_comp->ltiming_adjust) 908 i2c->ltiming_reg = 909 (l_sample_cnt << 6) | l_step_cnt | 910 (sample_cnt << 12) | (step_cnt << 9); 911 } else { 912 ret = mtk_i2c_calculate_speed(i2c, clk_src, 913 target_speed, &l_step_cnt, 914 &l_sample_cnt); 915 if (ret < 0) 916 continue; 917 918 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 919 920 /* Disable the high speed transaction */ 921 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 922 923 if (i2c->dev_comp->ltiming_adjust) 924 i2c->ltiming_reg = 925 (l_sample_cnt << 6) | l_step_cnt; 926 } 927 928 break; 929 } 930 931 932 return 0; 933 } 934 935 static void i2c_dump_register(struct mtk_i2c *i2c) 936 { 937 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", 938 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), 939 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); 940 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", 941 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), 942 mtk_i2c_readw(i2c, OFFSET_CONTROL)); 943 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", 944 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), 945 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); 946 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", 947 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), 948 mtk_i2c_readw(i2c, OFFSET_TIMING)); 949 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", 950 mtk_i2c_readw(i2c, OFFSET_START), 951 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); 952 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", 953 mtk_i2c_readw(i2c, OFFSET_HS), 954 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); 955 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", 956 mtk_i2c_readw(i2c, OFFSET_DCM_EN), 957 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); 958 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", 959 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), 960 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); 961 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", 962 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), 963 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); 964 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { 965 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", 966 mtk_i2c_readw(i2c, OFFSET_LTIMING), 967 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); 968 } 969 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", 970 readl(i2c->pdmabase + OFFSET_INT_FLAG), 971 readl(i2c->pdmabase + OFFSET_INT_EN)); 972 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", 973 readl(i2c->pdmabase + OFFSET_EN), 974 readl(i2c->pdmabase + OFFSET_CON)); 975 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", 976 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), 977 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); 978 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", 979 readl(i2c->pdmabase + OFFSET_TX_LEN), 980 readl(i2c->pdmabase + OFFSET_RX_LEN)); 981 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", 982 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), 983 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); 984 } 985 986 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 987 int num, int left_num) 988 { 989 u16 addr_reg; 990 u16 start_reg; 991 u16 control_reg; 992 u16 restart_flag = 0; 993 u16 dma_sync = 0; 994 u32 reg_4g_mode; 995 u32 reg_dma_reset; 996 u8 *dma_rd_buf = NULL; 997 u8 *dma_wr_buf = NULL; 998 dma_addr_t rpaddr = 0; 999 dma_addr_t wpaddr = 0; 1000 int ret; 1001 1002 i2c->irq_stat = 0; 1003 1004 if (i2c->auto_restart) 1005 restart_flag = I2C_RS_TRANSFER; 1006 1007 reinit_completion(&i2c->msg_complete); 1008 1009 if (i2c->dev_comp->apdma_sync && 1010 i2c->op != I2C_MASTER_WRRD && num > 1) { 1011 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); 1012 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, 1013 i2c->pdmabase + OFFSET_RST); 1014 1015 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, 1016 reg_dma_reset, 1017 !(reg_dma_reset & I2C_DMA_WARM_RST), 1018 0, 100); 1019 if (ret) { 1020 dev_err(i2c->dev, "DMA warm reset timeout\n"); 1021 return -ETIMEDOUT; 1022 } 1023 1024 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 1025 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); 1026 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 1027 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, 1028 OFFSET_DEBUGCTRL); 1029 } 1030 1031 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 1032 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 1033 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 1034 control_reg |= I2C_CONTROL_RS; 1035 1036 if (i2c->op == I2C_MASTER_WRRD) 1037 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 1038 1039 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 1040 1041 addr_reg = i2c_8bit_addr_from_msg(msgs); 1042 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 1043 1044 /* Clear interrupt status */ 1045 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1046 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 1047 1048 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 1049 1050 /* Enable interrupt */ 1051 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1052 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 1053 1054 /* Set transfer and transaction len */ 1055 if (i2c->op == I2C_MASTER_WRRD) { 1056 if (i2c->dev_comp->aux_len_reg) { 1057 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1058 mtk_i2c_writew(i2c, (msgs + 1)->len, 1059 OFFSET_TRANSFER_LEN_AUX); 1060 } else { 1061 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 1062 OFFSET_TRANSFER_LEN); 1063 } 1064 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 1065 } else { 1066 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1067 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 1068 } 1069 1070 if (i2c->dev_comp->apdma_sync) { 1071 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 1072 if (i2c->op == I2C_MASTER_WRRD) 1073 dma_sync |= I2C_DMA_DIR_CHANGE; 1074 } 1075 1076 /* Prepare buffer data to start transfer */ 1077 if (i2c->op == I2C_MASTER_RD) { 1078 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1079 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 1080 1081 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1082 if (!dma_rd_buf) 1083 return -ENOMEM; 1084 1085 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1086 msgs->len, DMA_FROM_DEVICE); 1087 if (dma_mapping_error(i2c->dev, rpaddr)) { 1088 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 1089 1090 return -ENOMEM; 1091 } 1092 1093 if (i2c->dev_comp->max_dma_support > 32) { 1094 reg_4g_mode = upper_32_bits(rpaddr); 1095 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1096 } 1097 1098 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1099 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 1100 } else if (i2c->op == I2C_MASTER_WR) { 1101 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1102 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 1103 1104 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1105 if (!dma_wr_buf) 1106 return -ENOMEM; 1107 1108 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1109 msgs->len, DMA_TO_DEVICE); 1110 if (dma_mapping_error(i2c->dev, wpaddr)) { 1111 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1112 1113 return -ENOMEM; 1114 } 1115 1116 if (i2c->dev_comp->max_dma_support > 32) { 1117 reg_4g_mode = upper_32_bits(wpaddr); 1118 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1119 } 1120 1121 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1122 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1123 } else { 1124 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 1125 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 1126 1127 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1128 if (!dma_wr_buf) 1129 return -ENOMEM; 1130 1131 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1132 msgs->len, DMA_TO_DEVICE); 1133 if (dma_mapping_error(i2c->dev, wpaddr)) { 1134 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1135 1136 return -ENOMEM; 1137 } 1138 1139 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 1140 if (!dma_rd_buf) { 1141 dma_unmap_single(i2c->dev, wpaddr, 1142 msgs->len, DMA_TO_DEVICE); 1143 1144 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1145 1146 return -ENOMEM; 1147 } 1148 1149 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1150 (msgs + 1)->len, 1151 DMA_FROM_DEVICE); 1152 if (dma_mapping_error(i2c->dev, rpaddr)) { 1153 dma_unmap_single(i2c->dev, wpaddr, 1154 msgs->len, DMA_TO_DEVICE); 1155 1156 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1157 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 1158 1159 return -ENOMEM; 1160 } 1161 1162 if (i2c->dev_comp->max_dma_support > 32) { 1163 reg_4g_mode = upper_32_bits(wpaddr); 1164 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1165 1166 reg_4g_mode = upper_32_bits(rpaddr); 1167 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1168 } 1169 1170 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1171 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1172 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1173 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 1174 } 1175 1176 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 1177 1178 if (!i2c->auto_restart) { 1179 start_reg = I2C_TRANSAC_START; 1180 } else { 1181 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1182 if (left_num >= 1) 1183 start_reg |= I2C_RS_MUL_CNFG; 1184 } 1185 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1186 1187 ret = wait_for_completion_timeout(&i2c->msg_complete, 1188 i2c->adap.timeout); 1189 1190 /* Clear interrupt mask */ 1191 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1192 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1193 1194 if (i2c->op == I2C_MASTER_WR) { 1195 dma_unmap_single(i2c->dev, wpaddr, 1196 msgs->len, DMA_TO_DEVICE); 1197 1198 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1199 } else if (i2c->op == I2C_MASTER_RD) { 1200 dma_unmap_single(i2c->dev, rpaddr, 1201 msgs->len, DMA_FROM_DEVICE); 1202 1203 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1204 } else { 1205 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1206 DMA_TO_DEVICE); 1207 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1208 DMA_FROM_DEVICE); 1209 1210 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1211 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1212 } 1213 1214 if (ret == 0) { 1215 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1216 i2c_dump_register(i2c); 1217 mtk_i2c_init_hw(i2c); 1218 return -ETIMEDOUT; 1219 } 1220 1221 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1222 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1223 mtk_i2c_init_hw(i2c); 1224 return -ENXIO; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1231 struct i2c_msg msgs[], int num) 1232 { 1233 int ret; 1234 int left_num = num; 1235 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1236 1237 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1238 if (ret) 1239 return ret; 1240 1241 i2c->auto_restart = i2c->dev_comp->auto_restart; 1242 1243 /* checking if we can skip restart and optimize using WRRD mode */ 1244 if (i2c->auto_restart && num == 2) { 1245 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1246 msgs[0].addr == msgs[1].addr) { 1247 i2c->auto_restart = 0; 1248 } 1249 } 1250 1251 if (i2c->auto_restart && num >= 2 && 1252 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1253 /* ignore the first restart irq after the master code, 1254 * otherwise the first transfer will be discarded. 1255 */ 1256 i2c->ignore_restart_irq = true; 1257 else 1258 i2c->ignore_restart_irq = false; 1259 1260 while (left_num--) { 1261 if (!msgs->buf) { 1262 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1263 ret = -EINVAL; 1264 goto err_exit; 1265 } 1266 1267 if (msgs->flags & I2C_M_RD) 1268 i2c->op = I2C_MASTER_RD; 1269 else 1270 i2c->op = I2C_MASTER_WR; 1271 1272 if (!i2c->auto_restart) { 1273 if (num > 1) { 1274 /* combined two messages into one transaction */ 1275 i2c->op = I2C_MASTER_WRRD; 1276 left_num--; 1277 } 1278 } 1279 1280 /* always use DMA mode. */ 1281 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1282 if (ret < 0) 1283 goto err_exit; 1284 1285 msgs++; 1286 } 1287 /* the return value is number of executed messages */ 1288 ret = num; 1289 1290 err_exit: 1291 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1292 return ret; 1293 } 1294 1295 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1296 { 1297 struct mtk_i2c *i2c = dev_id; 1298 u16 restart_flag = 0; 1299 u16 intr_stat; 1300 1301 if (i2c->auto_restart) 1302 restart_flag = I2C_RS_TRANSFER; 1303 1304 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1305 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1306 1307 /* 1308 * when occurs ack error, i2c controller generate two interrupts 1309 * first is the ack error interrupt, then the complete interrupt 1310 * i2c->irq_stat need keep the two interrupt value. 1311 */ 1312 i2c->irq_stat |= intr_stat; 1313 1314 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1315 i2c->ignore_restart_irq = false; 1316 i2c->irq_stat = 0; 1317 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1318 I2C_TRANSAC_START, OFFSET_START); 1319 } else { 1320 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1321 complete(&i2c->msg_complete); 1322 } 1323 1324 return IRQ_HANDLED; 1325 } 1326 1327 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1328 { 1329 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1330 return I2C_FUNC_I2C | 1331 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1332 else 1333 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1334 } 1335 1336 static const struct i2c_algorithm mtk_i2c_algorithm = { 1337 .master_xfer = mtk_i2c_transfer, 1338 .functionality = mtk_i2c_functionality, 1339 }; 1340 1341 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1342 { 1343 int ret; 1344 1345 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1346 if (ret < 0) 1347 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1348 1349 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1350 if (ret < 0) 1351 return ret; 1352 1353 if (i2c->clk_src_div == 0) 1354 return -EINVAL; 1355 1356 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1357 i2c->use_push_pull = 1358 of_property_read_bool(np, "mediatek,use-push-pull"); 1359 1360 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1361 1362 return 0; 1363 } 1364 1365 static int mtk_i2c_probe(struct platform_device *pdev) 1366 { 1367 int ret = 0; 1368 struct mtk_i2c *i2c; 1369 struct resource *res; 1370 int i, irq, speed_clk; 1371 1372 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1373 if (!i2c) 1374 return -ENOMEM; 1375 1376 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1377 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1378 if (IS_ERR(i2c->base)) 1379 return PTR_ERR(i2c->base); 1380 1381 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1382 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1383 if (IS_ERR(i2c->pdmabase)) 1384 return PTR_ERR(i2c->pdmabase); 1385 1386 irq = platform_get_irq(pdev, 0); 1387 if (irq < 0) 1388 return irq; 1389 1390 init_completion(&i2c->msg_complete); 1391 1392 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1393 i2c->adap.dev.of_node = pdev->dev.of_node; 1394 i2c->dev = &pdev->dev; 1395 i2c->adap.dev.parent = &pdev->dev; 1396 i2c->adap.owner = THIS_MODULE; 1397 i2c->adap.algo = &mtk_i2c_algorithm; 1398 i2c->adap.quirks = i2c->dev_comp->quirks; 1399 i2c->adap.timeout = 2 * HZ; 1400 i2c->adap.retries = 1; 1401 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1402 if (IS_ERR(i2c->adap.bus_regulator)) { 1403 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1404 i2c->adap.bus_regulator = NULL; 1405 else 1406 return PTR_ERR(i2c->adap.bus_regulator); 1407 } 1408 1409 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1410 if (ret) 1411 return -EINVAL; 1412 1413 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1414 return -EINVAL; 1415 1416 /* Fill in clk-bulk IDs */ 1417 for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) 1418 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; 1419 1420 /* Get clocks one by one, some may be optional */ 1421 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); 1422 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { 1423 dev_err(&pdev->dev, "cannot get main clock\n"); 1424 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); 1425 } 1426 1427 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); 1428 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { 1429 dev_err(&pdev->dev, "cannot get dma clock\n"); 1430 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); 1431 } 1432 1433 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); 1434 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) 1435 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); 1436 1437 if (i2c->have_pmic) { 1438 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); 1439 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { 1440 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1441 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); 1442 } 1443 speed_clk = I2C_MT65XX_CLK_PMIC; 1444 } else { 1445 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; 1446 speed_clk = I2C_MT65XX_CLK_MAIN; 1447 } 1448 1449 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1450 1451 ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); 1452 if (ret) { 1453 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1454 return -EINVAL; 1455 } 1456 1457 if (i2c->dev_comp->max_dma_support > 32) { 1458 ret = dma_set_mask(&pdev->dev, 1459 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1460 if (ret) { 1461 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1462 return ret; 1463 } 1464 } 1465 1466 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1467 if (ret) { 1468 dev_err(&pdev->dev, "clock enable failed!\n"); 1469 return ret; 1470 } 1471 mtk_i2c_init_hw(i2c); 1472 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1473 1474 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1475 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1476 dev_name(&pdev->dev), i2c); 1477 if (ret < 0) { 1478 dev_err(&pdev->dev, 1479 "Request I2C IRQ %d fail\n", irq); 1480 goto err_bulk_unprepare; 1481 } 1482 1483 i2c_set_adapdata(&i2c->adap, i2c); 1484 ret = i2c_add_adapter(&i2c->adap); 1485 if (ret) 1486 goto err_bulk_unprepare; 1487 1488 platform_set_drvdata(pdev, i2c); 1489 1490 return 0; 1491 1492 err_bulk_unprepare: 1493 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1494 1495 return ret; 1496 } 1497 1498 static int mtk_i2c_remove(struct platform_device *pdev) 1499 { 1500 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1501 1502 i2c_del_adapter(&i2c->adap); 1503 1504 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1505 1506 return 0; 1507 } 1508 1509 #ifdef CONFIG_PM_SLEEP 1510 static int mtk_i2c_suspend_noirq(struct device *dev) 1511 { 1512 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1513 1514 i2c_mark_adapter_suspended(&i2c->adap); 1515 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1516 1517 return 0; 1518 } 1519 1520 static int mtk_i2c_resume_noirq(struct device *dev) 1521 { 1522 int ret; 1523 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1524 1525 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1526 if (ret) { 1527 dev_err(dev, "clock enable failed!\n"); 1528 return ret; 1529 } 1530 1531 mtk_i2c_init_hw(i2c); 1532 1533 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1534 1535 i2c_mark_adapter_resumed(&i2c->adap); 1536 1537 return 0; 1538 } 1539 #endif 1540 1541 static const struct dev_pm_ops mtk_i2c_pm = { 1542 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1543 mtk_i2c_resume_noirq) 1544 }; 1545 1546 static struct platform_driver mtk_i2c_driver = { 1547 .probe = mtk_i2c_probe, 1548 .remove = mtk_i2c_remove, 1549 .driver = { 1550 .name = I2C_DRV_NAME, 1551 .pm = &mtk_i2c_pm, 1552 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1553 }, 1554 }; 1555 1556 module_platform_driver(mtk_i2c_driver); 1557 1558 MODULE_LICENSE("GPL v2"); 1559 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1560 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1561