1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_HANDSHAKE_RST 0x0020 42 #define I2C_FIFO_ADDR_CLR 0x0001 43 #define I2C_DELAY_LEN 0x0002 44 #define I2C_ST_START_CON 0x8001 45 #define I2C_FS_START_CON 0x1800 46 #define I2C_TIME_CLR_VALUE 0x0000 47 #define I2C_TIME_DEFAULT_VALUE 0x0003 48 #define I2C_WRRD_TRANAC_VALUE 0x0002 49 #define I2C_RD_TRANAC_VALUE 0x0001 50 #define I2C_SCL_MIS_COMP_VALUE 0x0000 51 #define I2C_CHN_CLR_FLAG 0x0000 52 53 #define I2C_DMA_CON_TX 0x0000 54 #define I2C_DMA_CON_RX 0x0001 55 #define I2C_DMA_ASYNC_MODE 0x0004 56 #define I2C_DMA_SKIP_CONFIG 0x0010 57 #define I2C_DMA_DIR_CHANGE 0x0200 58 #define I2C_DMA_START_EN 0x0001 59 #define I2C_DMA_INT_FLAG_NONE 0x0000 60 #define I2C_DMA_CLR_FLAG 0x0000 61 #define I2C_DMA_WARM_RST 0x0001 62 #define I2C_DMA_HARD_RST 0x0002 63 #define I2C_DMA_HANDSHAKE_RST 0x0004 64 65 #define MAX_SAMPLE_CNT_DIV 8 66 #define MAX_STEP_CNT_DIV 64 67 #define MAX_CLOCK_DIV 256 68 #define MAX_HS_STEP_CNT_DIV 8 69 #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 70 #define I2C_FAST_MODE_BUFFER (300 / 2) 71 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 72 73 #define I2C_CONTROL_RS (0x1 << 1) 74 #define I2C_CONTROL_DMA_EN (0x1 << 2) 75 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 76 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 77 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 78 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 79 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 80 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 81 #define I2C_CONTROL_WRAPPER (0x1 << 0) 82 83 #define I2C_DRV_NAME "i2c-mt65xx" 84 85 enum DMA_REGS_OFFSET { 86 OFFSET_INT_FLAG = 0x0, 87 OFFSET_INT_EN = 0x04, 88 OFFSET_EN = 0x08, 89 OFFSET_RST = 0x0c, 90 OFFSET_CON = 0x18, 91 OFFSET_TX_MEM_ADDR = 0x1c, 92 OFFSET_RX_MEM_ADDR = 0x20, 93 OFFSET_TX_LEN = 0x24, 94 OFFSET_RX_LEN = 0x28, 95 OFFSET_TX_4G_MODE = 0x54, 96 OFFSET_RX_4G_MODE = 0x58, 97 }; 98 99 enum i2c_trans_st_rs { 100 I2C_TRANS_STOP = 0, 101 I2C_TRANS_REPEATED_START, 102 }; 103 104 enum mtk_trans_op { 105 I2C_MASTER_WR = 1, 106 I2C_MASTER_RD, 107 I2C_MASTER_WRRD, 108 }; 109 110 enum I2C_REGS_OFFSET { 111 OFFSET_DATA_PORT, 112 OFFSET_SLAVE_ADDR, 113 OFFSET_INTR_MASK, 114 OFFSET_INTR_STAT, 115 OFFSET_CONTROL, 116 OFFSET_TRANSFER_LEN, 117 OFFSET_TRANSAC_LEN, 118 OFFSET_DELAY_LEN, 119 OFFSET_TIMING, 120 OFFSET_START, 121 OFFSET_EXT_CONF, 122 OFFSET_FIFO_STAT, 123 OFFSET_FIFO_THRESH, 124 OFFSET_FIFO_ADDR_CLR, 125 OFFSET_IO_CONFIG, 126 OFFSET_RSV_DEBUG, 127 OFFSET_HS, 128 OFFSET_SOFTRESET, 129 OFFSET_DCM_EN, 130 OFFSET_PATH_DIR, 131 OFFSET_DEBUGSTAT, 132 OFFSET_DEBUGCTRL, 133 OFFSET_TRANSFER_LEN_AUX, 134 OFFSET_CLOCK_DIV, 135 OFFSET_LTIMING, 136 OFFSET_SCL_HIGH_LOW_RATIO, 137 OFFSET_HS_SCL_HIGH_LOW_RATIO, 138 OFFSET_SCL_MIS_COMP_POINT, 139 OFFSET_STA_STO_AC_TIMING, 140 OFFSET_HS_STA_STO_AC_TIMING, 141 OFFSET_SDA_TIMING, 142 }; 143 144 static const u16 mt_i2c_regs_v1[] = { 145 [OFFSET_DATA_PORT] = 0x0, 146 [OFFSET_SLAVE_ADDR] = 0x4, 147 [OFFSET_INTR_MASK] = 0x8, 148 [OFFSET_INTR_STAT] = 0xc, 149 [OFFSET_CONTROL] = 0x10, 150 [OFFSET_TRANSFER_LEN] = 0x14, 151 [OFFSET_TRANSAC_LEN] = 0x18, 152 [OFFSET_DELAY_LEN] = 0x1c, 153 [OFFSET_TIMING] = 0x20, 154 [OFFSET_START] = 0x24, 155 [OFFSET_EXT_CONF] = 0x28, 156 [OFFSET_FIFO_STAT] = 0x30, 157 [OFFSET_FIFO_THRESH] = 0x34, 158 [OFFSET_FIFO_ADDR_CLR] = 0x38, 159 [OFFSET_IO_CONFIG] = 0x40, 160 [OFFSET_RSV_DEBUG] = 0x44, 161 [OFFSET_HS] = 0x48, 162 [OFFSET_SOFTRESET] = 0x50, 163 [OFFSET_DCM_EN] = 0x54, 164 [OFFSET_PATH_DIR] = 0x60, 165 [OFFSET_DEBUGSTAT] = 0x64, 166 [OFFSET_DEBUGCTRL] = 0x68, 167 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 168 [OFFSET_CLOCK_DIV] = 0x70, 169 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 170 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 171 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 172 [OFFSET_STA_STO_AC_TIMING] = 0x80, 173 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 174 [OFFSET_SDA_TIMING] = 0x88, 175 }; 176 177 static const u16 mt_i2c_regs_v2[] = { 178 [OFFSET_DATA_PORT] = 0x0, 179 [OFFSET_SLAVE_ADDR] = 0x4, 180 [OFFSET_INTR_MASK] = 0x8, 181 [OFFSET_INTR_STAT] = 0xc, 182 [OFFSET_CONTROL] = 0x10, 183 [OFFSET_TRANSFER_LEN] = 0x14, 184 [OFFSET_TRANSAC_LEN] = 0x18, 185 [OFFSET_DELAY_LEN] = 0x1c, 186 [OFFSET_TIMING] = 0x20, 187 [OFFSET_START] = 0x24, 188 [OFFSET_EXT_CONF] = 0x28, 189 [OFFSET_LTIMING] = 0x2c, 190 [OFFSET_HS] = 0x30, 191 [OFFSET_IO_CONFIG] = 0x34, 192 [OFFSET_FIFO_ADDR_CLR] = 0x38, 193 [OFFSET_SDA_TIMING] = 0x3c, 194 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 195 [OFFSET_CLOCK_DIV] = 0x48, 196 [OFFSET_SOFTRESET] = 0x50, 197 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 198 [OFFSET_DEBUGSTAT] = 0xe0, 199 [OFFSET_DEBUGCTRL] = 0xe8, 200 [OFFSET_FIFO_STAT] = 0xf4, 201 [OFFSET_FIFO_THRESH] = 0xf8, 202 [OFFSET_DCM_EN] = 0xf88, 203 }; 204 205 struct mtk_i2c_compatible { 206 const struct i2c_adapter_quirks *quirks; 207 const u16 *regs; 208 unsigned char pmic_i2c: 1; 209 unsigned char dcm: 1; 210 unsigned char auto_restart: 1; 211 unsigned char aux_len_reg: 1; 212 unsigned char timing_adjust: 1; 213 unsigned char dma_sync: 1; 214 unsigned char ltiming_adjust: 1; 215 unsigned char apdma_sync: 1; 216 unsigned char max_dma_support; 217 }; 218 219 struct mtk_i2c_ac_timing { 220 u16 htiming; 221 u16 ltiming; 222 u16 hs; 223 u16 ext; 224 u16 inter_clk_div; 225 u16 scl_hl_ratio; 226 u16 hs_scl_hl_ratio; 227 u16 sta_stop; 228 u16 hs_sta_stop; 229 u16 sda_timing; 230 }; 231 232 struct mtk_i2c { 233 struct i2c_adapter adap; /* i2c host adapter */ 234 struct device *dev; 235 struct completion msg_complete; 236 struct i2c_timings timing_info; 237 238 /* set in i2c probe */ 239 void __iomem *base; /* i2c base addr */ 240 void __iomem *pdmabase; /* dma base address*/ 241 struct clk *clk_main; /* main clock for i2c bus */ 242 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 243 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 244 struct clk *clk_arb; /* Arbitrator clock for i2c */ 245 bool have_pmic; /* can use i2c pins from PMIC */ 246 bool use_push_pull; /* IO config push-pull mode */ 247 248 u16 irq_stat; /* interrupt status */ 249 unsigned int clk_src_div; 250 unsigned int speed_hz; /* The speed in transfer */ 251 enum mtk_trans_op op; 252 u16 timing_reg; 253 u16 high_speed_reg; 254 u16 ltiming_reg; 255 unsigned char auto_restart; 256 bool ignore_restart_irq; 257 struct mtk_i2c_ac_timing ac_timing; 258 const struct mtk_i2c_compatible *dev_comp; 259 }; 260 261 /** 262 * struct i2c_spec_values: 263 * @min_low_ns: min LOW period of the SCL clock 264 * @min_su_sta_ns: min set-up time for a repeated START condition 265 * @max_hd_dat_ns: max data hold time 266 * @min_su_dat_ns: min data set-up time 267 */ 268 struct i2c_spec_values { 269 unsigned int min_low_ns; 270 unsigned int min_su_sta_ns; 271 unsigned int max_hd_dat_ns; 272 unsigned int min_su_dat_ns; 273 }; 274 275 static const struct i2c_spec_values standard_mode_spec = { 276 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 277 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 278 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 279 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 280 }; 281 282 static const struct i2c_spec_values fast_mode_spec = { 283 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 284 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 285 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 286 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 287 }; 288 289 static const struct i2c_spec_values fast_mode_plus_spec = { 290 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 291 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 292 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 293 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 294 }; 295 296 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 297 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 298 .max_num_msgs = 1, 299 .max_write_len = 255, 300 .max_read_len = 255, 301 .max_comb_1st_msg_len = 255, 302 .max_comb_2nd_msg_len = 31, 303 }; 304 305 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 306 .max_num_msgs = 255, 307 }; 308 309 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 310 .flags = I2C_AQ_NO_ZERO_LEN, 311 }; 312 313 static const struct mtk_i2c_compatible mt2712_compat = { 314 .regs = mt_i2c_regs_v1, 315 .pmic_i2c = 0, 316 .dcm = 1, 317 .auto_restart = 1, 318 .aux_len_reg = 1, 319 .timing_adjust = 1, 320 .dma_sync = 0, 321 .ltiming_adjust = 0, 322 .apdma_sync = 0, 323 .max_dma_support = 33, 324 }; 325 326 static const struct mtk_i2c_compatible mt6577_compat = { 327 .quirks = &mt6577_i2c_quirks, 328 .regs = mt_i2c_regs_v1, 329 .pmic_i2c = 0, 330 .dcm = 1, 331 .auto_restart = 0, 332 .aux_len_reg = 0, 333 .timing_adjust = 0, 334 .dma_sync = 0, 335 .ltiming_adjust = 0, 336 .apdma_sync = 0, 337 .max_dma_support = 32, 338 }; 339 340 static const struct mtk_i2c_compatible mt6589_compat = { 341 .quirks = &mt6577_i2c_quirks, 342 .regs = mt_i2c_regs_v1, 343 .pmic_i2c = 1, 344 .dcm = 0, 345 .auto_restart = 0, 346 .aux_len_reg = 0, 347 .timing_adjust = 0, 348 .dma_sync = 0, 349 .ltiming_adjust = 0, 350 .apdma_sync = 0, 351 .max_dma_support = 32, 352 }; 353 354 static const struct mtk_i2c_compatible mt7622_compat = { 355 .quirks = &mt7622_i2c_quirks, 356 .regs = mt_i2c_regs_v1, 357 .pmic_i2c = 0, 358 .dcm = 1, 359 .auto_restart = 1, 360 .aux_len_reg = 1, 361 .timing_adjust = 0, 362 .dma_sync = 0, 363 .ltiming_adjust = 0, 364 .apdma_sync = 0, 365 .max_dma_support = 32, 366 }; 367 368 static const struct mtk_i2c_compatible mt8173_compat = { 369 .regs = mt_i2c_regs_v1, 370 .pmic_i2c = 0, 371 .dcm = 1, 372 .auto_restart = 1, 373 .aux_len_reg = 1, 374 .timing_adjust = 0, 375 .dma_sync = 0, 376 .ltiming_adjust = 0, 377 .apdma_sync = 0, 378 .max_dma_support = 33, 379 }; 380 381 static const struct mtk_i2c_compatible mt8183_compat = { 382 .quirks = &mt8183_i2c_quirks, 383 .regs = mt_i2c_regs_v2, 384 .pmic_i2c = 0, 385 .dcm = 0, 386 .auto_restart = 1, 387 .aux_len_reg = 1, 388 .timing_adjust = 1, 389 .dma_sync = 1, 390 .ltiming_adjust = 1, 391 .apdma_sync = 0, 392 .max_dma_support = 33, 393 }; 394 395 static const struct mtk_i2c_compatible mt8192_compat = { 396 .quirks = &mt8183_i2c_quirks, 397 .regs = mt_i2c_regs_v2, 398 .pmic_i2c = 0, 399 .dcm = 0, 400 .auto_restart = 1, 401 .aux_len_reg = 1, 402 .timing_adjust = 1, 403 .dma_sync = 1, 404 .ltiming_adjust = 1, 405 .apdma_sync = 1, 406 .max_dma_support = 36, 407 }; 408 409 static const struct of_device_id mtk_i2c_of_match[] = { 410 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 411 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 412 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 413 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 414 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 415 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 416 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 417 {} 418 }; 419 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 420 421 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 422 { 423 return readw(i2c->base + i2c->dev_comp->regs[reg]); 424 } 425 426 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 427 enum I2C_REGS_OFFSET reg) 428 { 429 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 430 } 431 432 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 433 { 434 int ret; 435 436 ret = clk_prepare_enable(i2c->clk_dma); 437 if (ret) 438 return ret; 439 440 ret = clk_prepare_enable(i2c->clk_main); 441 if (ret) 442 goto err_main; 443 444 if (i2c->have_pmic) { 445 ret = clk_prepare_enable(i2c->clk_pmic); 446 if (ret) 447 goto err_pmic; 448 } 449 450 if (i2c->clk_arb) { 451 ret = clk_prepare_enable(i2c->clk_arb); 452 if (ret) 453 goto err_arb; 454 } 455 456 return 0; 457 458 err_arb: 459 if (i2c->have_pmic) 460 clk_disable_unprepare(i2c->clk_pmic); 461 err_pmic: 462 clk_disable_unprepare(i2c->clk_main); 463 err_main: 464 clk_disable_unprepare(i2c->clk_dma); 465 466 return ret; 467 } 468 469 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 470 { 471 if (i2c->clk_arb) 472 clk_disable_unprepare(i2c->clk_arb); 473 474 if (i2c->have_pmic) 475 clk_disable_unprepare(i2c->clk_pmic); 476 477 clk_disable_unprepare(i2c->clk_main); 478 clk_disable_unprepare(i2c->clk_dma); 479 } 480 481 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 482 { 483 u16 control_reg; 484 u16 intr_stat_reg; 485 u16 ext_conf_val; 486 487 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); 488 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 489 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); 490 491 if (i2c->dev_comp->apdma_sync) { 492 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 493 udelay(10); 494 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 495 udelay(10); 496 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 497 i2c->pdmabase + OFFSET_RST); 498 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 499 OFFSET_SOFTRESET); 500 udelay(10); 501 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 502 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 503 } else { 504 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 505 udelay(50); 506 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 507 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 508 } 509 510 /* Set ioconfig */ 511 if (i2c->use_push_pull) 512 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 513 else 514 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 515 516 if (i2c->dev_comp->dcm) 517 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 518 519 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 520 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 521 if (i2c->dev_comp->ltiming_adjust) 522 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 523 524 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 525 ext_conf_val = I2C_ST_START_CON; 526 else 527 ext_conf_val = I2C_FS_START_CON; 528 529 if (i2c->dev_comp->timing_adjust) { 530 ext_conf_val = i2c->ac_timing.ext; 531 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 532 OFFSET_CLOCK_DIV); 533 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 534 OFFSET_SCL_MIS_COMP_POINT); 535 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 536 OFFSET_SDA_TIMING); 537 538 if (i2c->dev_comp->ltiming_adjust) { 539 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 540 OFFSET_TIMING); 541 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 542 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 543 OFFSET_LTIMING); 544 } else { 545 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 546 OFFSET_SCL_HIGH_LOW_RATIO); 547 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 548 OFFSET_HS_SCL_HIGH_LOW_RATIO); 549 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 550 OFFSET_STA_STO_AC_TIMING); 551 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 552 OFFSET_HS_STA_STO_AC_TIMING); 553 } 554 } 555 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); 556 557 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 558 if (i2c->have_pmic) 559 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 560 561 control_reg = I2C_CONTROL_ACKERR_DET_EN | 562 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 563 if (i2c->dev_comp->dma_sync) 564 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 565 566 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 567 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 568 } 569 570 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 571 { 572 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 573 return &standard_mode_spec; 574 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 575 return &fast_mode_spec; 576 else 577 return &fast_mode_plus_spec; 578 } 579 580 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 581 { 582 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 583 return MAX_HS_STEP_CNT_DIV; 584 else 585 return MAX_STEP_CNT_DIV; 586 } 587 588 /* 589 * Check and Calculate i2c ac-timing 590 * 591 * Hardware design: 592 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 593 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 594 * 595 * Sample_ns is rounded down for xxx_cnt_div would be greater 596 * than the smallest spec. 597 * The sda_timing is chosen as the middle value between 598 * the largest and smallest. 599 */ 600 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 601 unsigned int clk_src, 602 unsigned int check_speed, 603 unsigned int step_cnt, 604 unsigned int sample_cnt) 605 { 606 const struct i2c_spec_values *spec; 607 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 608 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 609 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 610 clk_src); 611 612 if (!i2c->dev_comp->timing_adjust) 613 return 0; 614 615 if (i2c->dev_comp->ltiming_adjust) 616 max_sta_cnt = 0x100; 617 618 spec = mtk_i2c_get_spec(check_speed); 619 620 if (i2c->dev_comp->ltiming_adjust) 621 clk_ns = 1000000000 / clk_src; 622 else 623 clk_ns = sample_ns / 2; 624 625 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 626 i2c->timing_info.scl_int_delay_ns, clk_ns); 627 if (su_sta_cnt > max_sta_cnt) 628 return -1; 629 630 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 631 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 632 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 633 if (low_cnt > step_cnt) { 634 high_cnt = 2 * step_cnt - low_cnt; 635 } else { 636 high_cnt = step_cnt; 637 low_cnt = step_cnt; 638 } 639 } else { 640 return -2; 641 } 642 643 sda_max = spec->max_hd_dat_ns / sample_ns; 644 if (sda_max > low_cnt) 645 sda_max = 0; 646 647 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 648 if (sda_min < low_cnt) 649 sda_min = 0; 650 651 if (sda_min > sda_max) 652 return -3; 653 654 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 655 if (i2c->dev_comp->ltiming_adjust) { 656 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 657 (sample_cnt << 12) | (high_cnt << 8); 658 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 659 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 660 (low_cnt << 9); 661 i2c->ac_timing.ext &= ~GENMASK(7, 1); 662 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 663 } else { 664 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 665 (high_cnt << 6) | low_cnt; 666 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 667 su_sta_cnt; 668 } 669 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 670 i2c->ac_timing.sda_timing |= (1 << 12) | 671 ((sda_max + sda_min) / 2) << 6; 672 } else { 673 if (i2c->dev_comp->ltiming_adjust) { 674 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 675 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 676 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 677 } else { 678 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 679 (high_cnt << 6) | low_cnt; 680 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 681 su_sta_cnt; 682 } 683 684 i2c->ac_timing.sda_timing = (1 << 12) | 685 (sda_max + sda_min) / 2; 686 } 687 688 return 0; 689 } 690 691 /* 692 * Calculate i2c port speed 693 * 694 * Hardware design: 695 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 696 * clock_div: fixed in hardware, but may be various in different SoCs 697 * 698 * The calculation want to pick the highest bus frequency that is still 699 * less than or equal to i2c->speed_hz. The calculation try to get 700 * sample_cnt and step_cn 701 */ 702 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 703 unsigned int target_speed, 704 unsigned int *timing_step_cnt, 705 unsigned int *timing_sample_cnt) 706 { 707 unsigned int step_cnt; 708 unsigned int sample_cnt; 709 unsigned int max_step_cnt; 710 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 711 unsigned int base_step_cnt; 712 unsigned int opt_div; 713 unsigned int best_mul; 714 unsigned int cnt_mul; 715 int ret = -EINVAL; 716 717 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 718 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 719 720 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 721 base_step_cnt = max_step_cnt; 722 /* Find the best combination */ 723 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 724 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 725 726 /* Search for the best pair (sample_cnt, step_cnt) with 727 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 728 * 0 < step_cnt < max_step_cnt 729 * sample_cnt * step_cnt >= opt_div 730 * optimizing for sample_cnt * step_cnt being minimal 731 */ 732 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 733 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 734 cnt_mul = step_cnt * sample_cnt; 735 if (step_cnt > max_step_cnt) 736 continue; 737 738 if (cnt_mul < best_mul) { 739 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 740 target_speed, step_cnt - 1, sample_cnt - 1); 741 if (ret) 742 continue; 743 744 best_mul = cnt_mul; 745 base_sample_cnt = sample_cnt; 746 base_step_cnt = step_cnt; 747 if (best_mul == opt_div) 748 break; 749 } 750 } 751 752 if (ret) 753 return -EINVAL; 754 755 sample_cnt = base_sample_cnt; 756 step_cnt = base_step_cnt; 757 758 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 759 /* In this case, hardware can't support such 760 * low i2c_bus_freq 761 */ 762 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 763 return -EINVAL; 764 } 765 766 *timing_step_cnt = step_cnt - 1; 767 *timing_sample_cnt = sample_cnt - 1; 768 769 return 0; 770 } 771 772 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 773 { 774 unsigned int clk_src; 775 unsigned int step_cnt; 776 unsigned int sample_cnt; 777 unsigned int l_step_cnt; 778 unsigned int l_sample_cnt; 779 unsigned int target_speed; 780 unsigned int clk_div; 781 unsigned int max_clk_div; 782 int ret; 783 784 target_speed = i2c->speed_hz; 785 parent_clk /= i2c->clk_src_div; 786 787 if (i2c->dev_comp->timing_adjust) 788 max_clk_div = MAX_CLOCK_DIV; 789 else 790 max_clk_div = 1; 791 792 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 793 clk_src = parent_clk / clk_div; 794 795 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 796 /* Set master code speed register */ 797 ret = mtk_i2c_calculate_speed(i2c, clk_src, 798 I2C_MAX_FAST_MODE_FREQ, 799 &l_step_cnt, 800 &l_sample_cnt); 801 if (ret < 0) 802 continue; 803 804 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 805 806 /* Set the high speed mode register */ 807 ret = mtk_i2c_calculate_speed(i2c, clk_src, 808 target_speed, &step_cnt, 809 &sample_cnt); 810 if (ret < 0) 811 continue; 812 813 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 814 (sample_cnt << 12) | (step_cnt << 8); 815 816 if (i2c->dev_comp->ltiming_adjust) 817 i2c->ltiming_reg = 818 (l_sample_cnt << 6) | l_step_cnt | 819 (sample_cnt << 12) | (step_cnt << 9); 820 } else { 821 ret = mtk_i2c_calculate_speed(i2c, clk_src, 822 target_speed, &l_step_cnt, 823 &l_sample_cnt); 824 if (ret < 0) 825 continue; 826 827 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 828 829 /* Disable the high speed transaction */ 830 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 831 832 if (i2c->dev_comp->ltiming_adjust) 833 i2c->ltiming_reg = 834 (l_sample_cnt << 6) | l_step_cnt; 835 } 836 837 break; 838 } 839 840 i2c->ac_timing.inter_clk_div = clk_div - 1; 841 842 return 0; 843 } 844 845 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 846 int num, int left_num) 847 { 848 u16 addr_reg; 849 u16 start_reg; 850 u16 control_reg; 851 u16 restart_flag = 0; 852 u16 dma_sync = 0; 853 u32 reg_4g_mode; 854 u8 *dma_rd_buf = NULL; 855 u8 *dma_wr_buf = NULL; 856 dma_addr_t rpaddr = 0; 857 dma_addr_t wpaddr = 0; 858 int ret; 859 860 i2c->irq_stat = 0; 861 862 if (i2c->auto_restart) 863 restart_flag = I2C_RS_TRANSFER; 864 865 reinit_completion(&i2c->msg_complete); 866 867 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 868 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 869 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 870 control_reg |= I2C_CONTROL_RS; 871 872 if (i2c->op == I2C_MASTER_WRRD) 873 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 874 875 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 876 877 addr_reg = i2c_8bit_addr_from_msg(msgs); 878 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 879 880 /* Clear interrupt status */ 881 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 882 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 883 884 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 885 886 /* Enable interrupt */ 887 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 888 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 889 890 /* Set transfer and transaction len */ 891 if (i2c->op == I2C_MASTER_WRRD) { 892 if (i2c->dev_comp->aux_len_reg) { 893 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 894 mtk_i2c_writew(i2c, (msgs + 1)->len, 895 OFFSET_TRANSFER_LEN_AUX); 896 } else { 897 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 898 OFFSET_TRANSFER_LEN); 899 } 900 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 901 } else { 902 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 903 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 904 } 905 906 if (i2c->dev_comp->apdma_sync) { 907 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 908 if (i2c->op == I2C_MASTER_WRRD) 909 dma_sync |= I2C_DMA_DIR_CHANGE; 910 } 911 912 /* Prepare buffer data to start transfer */ 913 if (i2c->op == I2C_MASTER_RD) { 914 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 915 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 916 917 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 918 if (!dma_rd_buf) 919 return -ENOMEM; 920 921 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 922 msgs->len, DMA_FROM_DEVICE); 923 if (dma_mapping_error(i2c->dev, rpaddr)) { 924 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 925 926 return -ENOMEM; 927 } 928 929 if (i2c->dev_comp->max_dma_support > 32) { 930 reg_4g_mode = upper_32_bits(rpaddr); 931 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 932 } 933 934 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 935 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 936 } else if (i2c->op == I2C_MASTER_WR) { 937 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 938 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 939 940 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 941 if (!dma_wr_buf) 942 return -ENOMEM; 943 944 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 945 msgs->len, DMA_TO_DEVICE); 946 if (dma_mapping_error(i2c->dev, wpaddr)) { 947 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 948 949 return -ENOMEM; 950 } 951 952 if (i2c->dev_comp->max_dma_support > 32) { 953 reg_4g_mode = upper_32_bits(wpaddr); 954 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 955 } 956 957 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 958 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 959 } else { 960 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 961 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 962 963 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 964 if (!dma_wr_buf) 965 return -ENOMEM; 966 967 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 968 msgs->len, DMA_TO_DEVICE); 969 if (dma_mapping_error(i2c->dev, wpaddr)) { 970 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 971 972 return -ENOMEM; 973 } 974 975 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 976 if (!dma_rd_buf) { 977 dma_unmap_single(i2c->dev, wpaddr, 978 msgs->len, DMA_TO_DEVICE); 979 980 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 981 982 return -ENOMEM; 983 } 984 985 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 986 (msgs + 1)->len, 987 DMA_FROM_DEVICE); 988 if (dma_mapping_error(i2c->dev, rpaddr)) { 989 dma_unmap_single(i2c->dev, wpaddr, 990 msgs->len, DMA_TO_DEVICE); 991 992 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 993 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 994 995 return -ENOMEM; 996 } 997 998 if (i2c->dev_comp->max_dma_support > 32) { 999 reg_4g_mode = upper_32_bits(wpaddr); 1000 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1001 1002 reg_4g_mode = upper_32_bits(rpaddr); 1003 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1004 } 1005 1006 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1007 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1008 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1009 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 1010 } 1011 1012 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 1013 1014 if (!i2c->auto_restart) { 1015 start_reg = I2C_TRANSAC_START; 1016 } else { 1017 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1018 if (left_num >= 1) 1019 start_reg |= I2C_RS_MUL_CNFG; 1020 } 1021 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1022 1023 ret = wait_for_completion_timeout(&i2c->msg_complete, 1024 i2c->adap.timeout); 1025 1026 /* Clear interrupt mask */ 1027 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1028 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1029 1030 if (i2c->op == I2C_MASTER_WR) { 1031 dma_unmap_single(i2c->dev, wpaddr, 1032 msgs->len, DMA_TO_DEVICE); 1033 1034 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1035 } else if (i2c->op == I2C_MASTER_RD) { 1036 dma_unmap_single(i2c->dev, rpaddr, 1037 msgs->len, DMA_FROM_DEVICE); 1038 1039 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1040 } else { 1041 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1042 DMA_TO_DEVICE); 1043 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1044 DMA_FROM_DEVICE); 1045 1046 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1047 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1048 } 1049 1050 if (ret == 0) { 1051 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1052 mtk_i2c_init_hw(i2c); 1053 return -ETIMEDOUT; 1054 } 1055 1056 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1057 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1058 mtk_i2c_init_hw(i2c); 1059 return -ENXIO; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1066 struct i2c_msg msgs[], int num) 1067 { 1068 int ret; 1069 int left_num = num; 1070 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1071 1072 ret = mtk_i2c_clock_enable(i2c); 1073 if (ret) 1074 return ret; 1075 1076 i2c->auto_restart = i2c->dev_comp->auto_restart; 1077 1078 /* checking if we can skip restart and optimize using WRRD mode */ 1079 if (i2c->auto_restart && num == 2) { 1080 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1081 msgs[0].addr == msgs[1].addr) { 1082 i2c->auto_restart = 0; 1083 } 1084 } 1085 1086 if (i2c->auto_restart && num >= 2 && 1087 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1088 /* ignore the first restart irq after the master code, 1089 * otherwise the first transfer will be discarded. 1090 */ 1091 i2c->ignore_restart_irq = true; 1092 else 1093 i2c->ignore_restart_irq = false; 1094 1095 while (left_num--) { 1096 if (!msgs->buf) { 1097 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1098 ret = -EINVAL; 1099 goto err_exit; 1100 } 1101 1102 if (msgs->flags & I2C_M_RD) 1103 i2c->op = I2C_MASTER_RD; 1104 else 1105 i2c->op = I2C_MASTER_WR; 1106 1107 if (!i2c->auto_restart) { 1108 if (num > 1) { 1109 /* combined two messages into one transaction */ 1110 i2c->op = I2C_MASTER_WRRD; 1111 left_num--; 1112 } 1113 } 1114 1115 /* always use DMA mode. */ 1116 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1117 if (ret < 0) 1118 goto err_exit; 1119 1120 msgs++; 1121 } 1122 /* the return value is number of executed messages */ 1123 ret = num; 1124 1125 err_exit: 1126 mtk_i2c_clock_disable(i2c); 1127 return ret; 1128 } 1129 1130 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1131 { 1132 struct mtk_i2c *i2c = dev_id; 1133 u16 restart_flag = 0; 1134 u16 intr_stat; 1135 1136 if (i2c->auto_restart) 1137 restart_flag = I2C_RS_TRANSFER; 1138 1139 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1140 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1141 1142 /* 1143 * when occurs ack error, i2c controller generate two interrupts 1144 * first is the ack error interrupt, then the complete interrupt 1145 * i2c->irq_stat need keep the two interrupt value. 1146 */ 1147 i2c->irq_stat |= intr_stat; 1148 1149 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1150 i2c->ignore_restart_irq = false; 1151 i2c->irq_stat = 0; 1152 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1153 I2C_TRANSAC_START, OFFSET_START); 1154 } else { 1155 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1156 complete(&i2c->msg_complete); 1157 } 1158 1159 return IRQ_HANDLED; 1160 } 1161 1162 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1163 { 1164 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1165 return I2C_FUNC_I2C | 1166 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1167 else 1168 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1169 } 1170 1171 static const struct i2c_algorithm mtk_i2c_algorithm = { 1172 .master_xfer = mtk_i2c_transfer, 1173 .functionality = mtk_i2c_functionality, 1174 }; 1175 1176 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1177 { 1178 int ret; 1179 1180 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1181 if (ret < 0) 1182 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1183 1184 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1185 if (ret < 0) 1186 return ret; 1187 1188 if (i2c->clk_src_div == 0) 1189 return -EINVAL; 1190 1191 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1192 i2c->use_push_pull = 1193 of_property_read_bool(np, "mediatek,use-push-pull"); 1194 1195 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1196 1197 return 0; 1198 } 1199 1200 static int mtk_i2c_probe(struct platform_device *pdev) 1201 { 1202 int ret = 0; 1203 struct mtk_i2c *i2c; 1204 struct clk *clk; 1205 struct resource *res; 1206 int irq; 1207 1208 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1209 if (!i2c) 1210 return -ENOMEM; 1211 1212 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1213 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1214 if (IS_ERR(i2c->base)) 1215 return PTR_ERR(i2c->base); 1216 1217 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1218 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1219 if (IS_ERR(i2c->pdmabase)) 1220 return PTR_ERR(i2c->pdmabase); 1221 1222 irq = platform_get_irq(pdev, 0); 1223 if (irq < 0) 1224 return irq; 1225 1226 init_completion(&i2c->msg_complete); 1227 1228 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1229 i2c->adap.dev.of_node = pdev->dev.of_node; 1230 i2c->dev = &pdev->dev; 1231 i2c->adap.dev.parent = &pdev->dev; 1232 i2c->adap.owner = THIS_MODULE; 1233 i2c->adap.algo = &mtk_i2c_algorithm; 1234 i2c->adap.quirks = i2c->dev_comp->quirks; 1235 i2c->adap.timeout = 2 * HZ; 1236 i2c->adap.retries = 1; 1237 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1238 if (IS_ERR(i2c->adap.bus_regulator)) { 1239 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1240 i2c->adap.bus_regulator = NULL; 1241 else 1242 return PTR_ERR(i2c->adap.bus_regulator); 1243 } 1244 1245 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1246 if (ret) 1247 return -EINVAL; 1248 1249 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1250 return -EINVAL; 1251 1252 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1253 if (IS_ERR(i2c->clk_main)) { 1254 dev_err(&pdev->dev, "cannot get main clock\n"); 1255 return PTR_ERR(i2c->clk_main); 1256 } 1257 1258 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1259 if (IS_ERR(i2c->clk_dma)) { 1260 dev_err(&pdev->dev, "cannot get dma clock\n"); 1261 return PTR_ERR(i2c->clk_dma); 1262 } 1263 1264 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1265 if (IS_ERR(i2c->clk_arb)) 1266 i2c->clk_arb = NULL; 1267 1268 clk = i2c->clk_main; 1269 if (i2c->have_pmic) { 1270 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1271 if (IS_ERR(i2c->clk_pmic)) { 1272 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1273 return PTR_ERR(i2c->clk_pmic); 1274 } 1275 clk = i2c->clk_pmic; 1276 } 1277 1278 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1279 1280 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1281 if (ret) { 1282 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1283 return -EINVAL; 1284 } 1285 1286 if (i2c->dev_comp->max_dma_support > 32) { 1287 ret = dma_set_mask(&pdev->dev, 1288 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1289 if (ret) { 1290 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1291 return ret; 1292 } 1293 } 1294 1295 ret = mtk_i2c_clock_enable(i2c); 1296 if (ret) { 1297 dev_err(&pdev->dev, "clock enable failed!\n"); 1298 return ret; 1299 } 1300 mtk_i2c_init_hw(i2c); 1301 mtk_i2c_clock_disable(i2c); 1302 1303 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1304 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1305 dev_name(&pdev->dev), i2c); 1306 if (ret < 0) { 1307 dev_err(&pdev->dev, 1308 "Request I2C IRQ %d fail\n", irq); 1309 return ret; 1310 } 1311 1312 i2c_set_adapdata(&i2c->adap, i2c); 1313 ret = i2c_add_adapter(&i2c->adap); 1314 if (ret) 1315 return ret; 1316 1317 platform_set_drvdata(pdev, i2c); 1318 1319 return 0; 1320 } 1321 1322 static int mtk_i2c_remove(struct platform_device *pdev) 1323 { 1324 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1325 1326 i2c_del_adapter(&i2c->adap); 1327 1328 return 0; 1329 } 1330 1331 #ifdef CONFIG_PM_SLEEP 1332 static int mtk_i2c_suspend_noirq(struct device *dev) 1333 { 1334 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1335 1336 i2c_mark_adapter_suspended(&i2c->adap); 1337 1338 return 0; 1339 } 1340 1341 static int mtk_i2c_resume_noirq(struct device *dev) 1342 { 1343 int ret; 1344 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1345 1346 ret = mtk_i2c_clock_enable(i2c); 1347 if (ret) { 1348 dev_err(dev, "clock enable failed!\n"); 1349 return ret; 1350 } 1351 1352 mtk_i2c_init_hw(i2c); 1353 1354 mtk_i2c_clock_disable(i2c); 1355 1356 i2c_mark_adapter_resumed(&i2c->adap); 1357 1358 return 0; 1359 } 1360 #endif 1361 1362 static const struct dev_pm_ops mtk_i2c_pm = { 1363 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1364 mtk_i2c_resume_noirq) 1365 }; 1366 1367 static struct platform_driver mtk_i2c_driver = { 1368 .probe = mtk_i2c_probe, 1369 .remove = mtk_i2c_remove, 1370 .driver = { 1371 .name = I2C_DRV_NAME, 1372 .pm = &mtk_i2c_pm, 1373 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1374 }, 1375 }; 1376 1377 module_platform_driver(mtk_i2c_driver); 1378 1379 MODULE_LICENSE("GPL v2"); 1380 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1381 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1382