1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 30 #define I2C_RS_TRANSFER (1 << 4) 31 #define I2C_ARB_LOST (1 << 3) 32 #define I2C_HS_NACKERR (1 << 2) 33 #define I2C_ACKERR (1 << 1) 34 #define I2C_TRANSAC_COMP (1 << 0) 35 #define I2C_TRANSAC_START (1 << 0) 36 #define I2C_RS_MUL_CNFG (1 << 15) 37 #define I2C_RS_MUL_TRIG (1 << 14) 38 #define I2C_DCM_DISABLE 0x0000 39 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 40 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 41 #define I2C_SOFT_RST 0x0001 42 #define I2C_HANDSHAKE_RST 0x0020 43 #define I2C_FIFO_ADDR_CLR 0x0001 44 #define I2C_DELAY_LEN 0x0002 45 #define I2C_ST_START_CON 0x8001 46 #define I2C_FS_START_CON 0x1800 47 #define I2C_TIME_CLR_VALUE 0x0000 48 #define I2C_TIME_DEFAULT_VALUE 0x0003 49 #define I2C_WRRD_TRANAC_VALUE 0x0002 50 #define I2C_RD_TRANAC_VALUE 0x0001 51 #define I2C_SCL_MIS_COMP_VALUE 0x0000 52 #define I2C_CHN_CLR_FLAG 0x0000 53 #define I2C_RELIABILITY 0x0010 54 #define I2C_DMAACK_ENABLE 0x0008 55 56 #define I2C_DMA_CON_TX 0x0000 57 #define I2C_DMA_CON_RX 0x0001 58 #define I2C_DMA_ASYNC_MODE 0x0004 59 #define I2C_DMA_SKIP_CONFIG 0x0010 60 #define I2C_DMA_DIR_CHANGE 0x0200 61 #define I2C_DMA_START_EN 0x0001 62 #define I2C_DMA_INT_FLAG_NONE 0x0000 63 #define I2C_DMA_CLR_FLAG 0x0000 64 #define I2C_DMA_WARM_RST 0x0001 65 #define I2C_DMA_HARD_RST 0x0002 66 #define I2C_DMA_HANDSHAKE_RST 0x0004 67 68 #define MAX_SAMPLE_CNT_DIV 8 69 #define MAX_STEP_CNT_DIV 64 70 #define MAX_CLOCK_DIV 256 71 #define MAX_HS_STEP_CNT_DIV 8 72 #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 73 #define I2C_FAST_MODE_BUFFER (300 / 2) 74 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 75 76 #define I2C_CONTROL_RS (0x1 << 1) 77 #define I2C_CONTROL_DMA_EN (0x1 << 2) 78 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 79 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 80 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 81 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 82 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 83 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 84 #define I2C_CONTROL_WRAPPER (0x1 << 0) 85 86 #define I2C_DRV_NAME "i2c-mt65xx" 87 88 enum DMA_REGS_OFFSET { 89 OFFSET_INT_FLAG = 0x0, 90 OFFSET_INT_EN = 0x04, 91 OFFSET_EN = 0x08, 92 OFFSET_RST = 0x0c, 93 OFFSET_CON = 0x18, 94 OFFSET_TX_MEM_ADDR = 0x1c, 95 OFFSET_RX_MEM_ADDR = 0x20, 96 OFFSET_TX_LEN = 0x24, 97 OFFSET_RX_LEN = 0x28, 98 OFFSET_TX_4G_MODE = 0x54, 99 OFFSET_RX_4G_MODE = 0x58, 100 }; 101 102 enum i2c_trans_st_rs { 103 I2C_TRANS_STOP = 0, 104 I2C_TRANS_REPEATED_START, 105 }; 106 107 enum mtk_trans_op { 108 I2C_MASTER_WR = 1, 109 I2C_MASTER_RD, 110 I2C_MASTER_WRRD, 111 }; 112 113 enum I2C_REGS_OFFSET { 114 OFFSET_DATA_PORT, 115 OFFSET_SLAVE_ADDR, 116 OFFSET_INTR_MASK, 117 OFFSET_INTR_STAT, 118 OFFSET_CONTROL, 119 OFFSET_TRANSFER_LEN, 120 OFFSET_TRANSAC_LEN, 121 OFFSET_DELAY_LEN, 122 OFFSET_TIMING, 123 OFFSET_START, 124 OFFSET_EXT_CONF, 125 OFFSET_FIFO_STAT, 126 OFFSET_FIFO_THRESH, 127 OFFSET_FIFO_ADDR_CLR, 128 OFFSET_IO_CONFIG, 129 OFFSET_RSV_DEBUG, 130 OFFSET_HS, 131 OFFSET_SOFTRESET, 132 OFFSET_DCM_EN, 133 OFFSET_MULTI_DMA, 134 OFFSET_PATH_DIR, 135 OFFSET_DEBUGSTAT, 136 OFFSET_DEBUGCTRL, 137 OFFSET_TRANSFER_LEN_AUX, 138 OFFSET_CLOCK_DIV, 139 OFFSET_LTIMING, 140 OFFSET_SCL_HIGH_LOW_RATIO, 141 OFFSET_HS_SCL_HIGH_LOW_RATIO, 142 OFFSET_SCL_MIS_COMP_POINT, 143 OFFSET_STA_STO_AC_TIMING, 144 OFFSET_HS_STA_STO_AC_TIMING, 145 OFFSET_SDA_TIMING, 146 }; 147 148 static const u16 mt_i2c_regs_v1[] = { 149 [OFFSET_DATA_PORT] = 0x0, 150 [OFFSET_SLAVE_ADDR] = 0x4, 151 [OFFSET_INTR_MASK] = 0x8, 152 [OFFSET_INTR_STAT] = 0xc, 153 [OFFSET_CONTROL] = 0x10, 154 [OFFSET_TRANSFER_LEN] = 0x14, 155 [OFFSET_TRANSAC_LEN] = 0x18, 156 [OFFSET_DELAY_LEN] = 0x1c, 157 [OFFSET_TIMING] = 0x20, 158 [OFFSET_START] = 0x24, 159 [OFFSET_EXT_CONF] = 0x28, 160 [OFFSET_FIFO_STAT] = 0x30, 161 [OFFSET_FIFO_THRESH] = 0x34, 162 [OFFSET_FIFO_ADDR_CLR] = 0x38, 163 [OFFSET_IO_CONFIG] = 0x40, 164 [OFFSET_RSV_DEBUG] = 0x44, 165 [OFFSET_HS] = 0x48, 166 [OFFSET_SOFTRESET] = 0x50, 167 [OFFSET_DCM_EN] = 0x54, 168 [OFFSET_PATH_DIR] = 0x60, 169 [OFFSET_DEBUGSTAT] = 0x64, 170 [OFFSET_DEBUGCTRL] = 0x68, 171 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 172 [OFFSET_CLOCK_DIV] = 0x70, 173 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 174 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 175 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 176 [OFFSET_STA_STO_AC_TIMING] = 0x80, 177 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 178 [OFFSET_SDA_TIMING] = 0x88, 179 }; 180 181 static const u16 mt_i2c_regs_v2[] = { 182 [OFFSET_DATA_PORT] = 0x0, 183 [OFFSET_SLAVE_ADDR] = 0x4, 184 [OFFSET_INTR_MASK] = 0x8, 185 [OFFSET_INTR_STAT] = 0xc, 186 [OFFSET_CONTROL] = 0x10, 187 [OFFSET_TRANSFER_LEN] = 0x14, 188 [OFFSET_TRANSAC_LEN] = 0x18, 189 [OFFSET_DELAY_LEN] = 0x1c, 190 [OFFSET_TIMING] = 0x20, 191 [OFFSET_START] = 0x24, 192 [OFFSET_EXT_CONF] = 0x28, 193 [OFFSET_LTIMING] = 0x2c, 194 [OFFSET_HS] = 0x30, 195 [OFFSET_IO_CONFIG] = 0x34, 196 [OFFSET_FIFO_ADDR_CLR] = 0x38, 197 [OFFSET_SDA_TIMING] = 0x3c, 198 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 199 [OFFSET_CLOCK_DIV] = 0x48, 200 [OFFSET_SOFTRESET] = 0x50, 201 [OFFSET_MULTI_DMA] = 0x8c, 202 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 203 [OFFSET_DEBUGSTAT] = 0xe4, 204 [OFFSET_DEBUGCTRL] = 0xe8, 205 [OFFSET_FIFO_STAT] = 0xf4, 206 [OFFSET_FIFO_THRESH] = 0xf8, 207 [OFFSET_DCM_EN] = 0xf88, 208 }; 209 210 struct mtk_i2c_compatible { 211 const struct i2c_adapter_quirks *quirks; 212 const u16 *regs; 213 unsigned char pmic_i2c: 1; 214 unsigned char dcm: 1; 215 unsigned char auto_restart: 1; 216 unsigned char aux_len_reg: 1; 217 unsigned char timing_adjust: 1; 218 unsigned char dma_sync: 1; 219 unsigned char ltiming_adjust: 1; 220 unsigned char apdma_sync: 1; 221 unsigned char max_dma_support; 222 }; 223 224 struct mtk_i2c_ac_timing { 225 u16 htiming; 226 u16 ltiming; 227 u16 hs; 228 u16 ext; 229 u16 inter_clk_div; 230 u16 scl_hl_ratio; 231 u16 hs_scl_hl_ratio; 232 u16 sta_stop; 233 u16 hs_sta_stop; 234 u16 sda_timing; 235 }; 236 237 struct mtk_i2c { 238 struct i2c_adapter adap; /* i2c host adapter */ 239 struct device *dev; 240 struct completion msg_complete; 241 struct i2c_timings timing_info; 242 243 /* set in i2c probe */ 244 void __iomem *base; /* i2c base addr */ 245 void __iomem *pdmabase; /* dma base address*/ 246 struct clk *clk_main; /* main clock for i2c bus */ 247 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 248 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 249 struct clk *clk_arb; /* Arbitrator clock for i2c */ 250 bool have_pmic; /* can use i2c pins from PMIC */ 251 bool use_push_pull; /* IO config push-pull mode */ 252 253 u16 irq_stat; /* interrupt status */ 254 unsigned int clk_src_div; 255 unsigned int speed_hz; /* The speed in transfer */ 256 enum mtk_trans_op op; 257 u16 timing_reg; 258 u16 high_speed_reg; 259 u16 ltiming_reg; 260 unsigned char auto_restart; 261 bool ignore_restart_irq; 262 struct mtk_i2c_ac_timing ac_timing; 263 const struct mtk_i2c_compatible *dev_comp; 264 }; 265 266 /** 267 * struct i2c_spec_values: 268 * @min_low_ns: min LOW period of the SCL clock 269 * @min_su_sta_ns: min set-up time for a repeated START condition 270 * @max_hd_dat_ns: max data hold time 271 * @min_su_dat_ns: min data set-up time 272 */ 273 struct i2c_spec_values { 274 unsigned int min_low_ns; 275 unsigned int min_su_sta_ns; 276 unsigned int max_hd_dat_ns; 277 unsigned int min_su_dat_ns; 278 }; 279 280 static const struct i2c_spec_values standard_mode_spec = { 281 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 282 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 283 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 284 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 285 }; 286 287 static const struct i2c_spec_values fast_mode_spec = { 288 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 289 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 290 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 291 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 292 }; 293 294 static const struct i2c_spec_values fast_mode_plus_spec = { 295 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 296 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 297 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 298 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 299 }; 300 301 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 302 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 303 .max_num_msgs = 1, 304 .max_write_len = 255, 305 .max_read_len = 255, 306 .max_comb_1st_msg_len = 255, 307 .max_comb_2nd_msg_len = 31, 308 }; 309 310 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 311 .max_num_msgs = 255, 312 }; 313 314 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 315 .flags = I2C_AQ_NO_ZERO_LEN, 316 }; 317 318 static const struct mtk_i2c_compatible mt2712_compat = { 319 .regs = mt_i2c_regs_v1, 320 .pmic_i2c = 0, 321 .dcm = 1, 322 .auto_restart = 1, 323 .aux_len_reg = 1, 324 .timing_adjust = 1, 325 .dma_sync = 0, 326 .ltiming_adjust = 0, 327 .apdma_sync = 0, 328 .max_dma_support = 33, 329 }; 330 331 static const struct mtk_i2c_compatible mt6577_compat = { 332 .quirks = &mt6577_i2c_quirks, 333 .regs = mt_i2c_regs_v1, 334 .pmic_i2c = 0, 335 .dcm = 1, 336 .auto_restart = 0, 337 .aux_len_reg = 0, 338 .timing_adjust = 0, 339 .dma_sync = 0, 340 .ltiming_adjust = 0, 341 .apdma_sync = 0, 342 .max_dma_support = 32, 343 }; 344 345 static const struct mtk_i2c_compatible mt6589_compat = { 346 .quirks = &mt6577_i2c_quirks, 347 .regs = mt_i2c_regs_v1, 348 .pmic_i2c = 1, 349 .dcm = 0, 350 .auto_restart = 0, 351 .aux_len_reg = 0, 352 .timing_adjust = 0, 353 .dma_sync = 0, 354 .ltiming_adjust = 0, 355 .apdma_sync = 0, 356 .max_dma_support = 32, 357 }; 358 359 static const struct mtk_i2c_compatible mt7622_compat = { 360 .quirks = &mt7622_i2c_quirks, 361 .regs = mt_i2c_regs_v1, 362 .pmic_i2c = 0, 363 .dcm = 1, 364 .auto_restart = 1, 365 .aux_len_reg = 1, 366 .timing_adjust = 0, 367 .dma_sync = 0, 368 .ltiming_adjust = 0, 369 .apdma_sync = 0, 370 .max_dma_support = 32, 371 }; 372 373 static const struct mtk_i2c_compatible mt8173_compat = { 374 .regs = mt_i2c_regs_v1, 375 .pmic_i2c = 0, 376 .dcm = 1, 377 .auto_restart = 1, 378 .aux_len_reg = 1, 379 .timing_adjust = 0, 380 .dma_sync = 0, 381 .ltiming_adjust = 0, 382 .apdma_sync = 0, 383 .max_dma_support = 33, 384 }; 385 386 static const struct mtk_i2c_compatible mt8183_compat = { 387 .quirks = &mt8183_i2c_quirks, 388 .regs = mt_i2c_regs_v2, 389 .pmic_i2c = 0, 390 .dcm = 0, 391 .auto_restart = 1, 392 .aux_len_reg = 1, 393 .timing_adjust = 1, 394 .dma_sync = 1, 395 .ltiming_adjust = 1, 396 .apdma_sync = 0, 397 .max_dma_support = 33, 398 }; 399 400 static const struct mtk_i2c_compatible mt8192_compat = { 401 .quirks = &mt8183_i2c_quirks, 402 .regs = mt_i2c_regs_v2, 403 .pmic_i2c = 0, 404 .dcm = 0, 405 .auto_restart = 1, 406 .aux_len_reg = 1, 407 .timing_adjust = 1, 408 .dma_sync = 1, 409 .ltiming_adjust = 1, 410 .apdma_sync = 1, 411 .max_dma_support = 36, 412 }; 413 414 static const struct of_device_id mtk_i2c_of_match[] = { 415 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 416 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 417 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 418 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 419 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 420 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 421 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 422 {} 423 }; 424 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 425 426 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 427 { 428 return readw(i2c->base + i2c->dev_comp->regs[reg]); 429 } 430 431 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 432 enum I2C_REGS_OFFSET reg) 433 { 434 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 435 } 436 437 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 438 { 439 int ret; 440 441 ret = clk_prepare_enable(i2c->clk_dma); 442 if (ret) 443 return ret; 444 445 ret = clk_prepare_enable(i2c->clk_main); 446 if (ret) 447 goto err_main; 448 449 if (i2c->have_pmic) { 450 ret = clk_prepare_enable(i2c->clk_pmic); 451 if (ret) 452 goto err_pmic; 453 } 454 455 if (i2c->clk_arb) { 456 ret = clk_prepare_enable(i2c->clk_arb); 457 if (ret) 458 goto err_arb; 459 } 460 461 return 0; 462 463 err_arb: 464 if (i2c->have_pmic) 465 clk_disable_unprepare(i2c->clk_pmic); 466 err_pmic: 467 clk_disable_unprepare(i2c->clk_main); 468 err_main: 469 clk_disable_unprepare(i2c->clk_dma); 470 471 return ret; 472 } 473 474 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 475 { 476 if (i2c->clk_arb) 477 clk_disable_unprepare(i2c->clk_arb); 478 479 if (i2c->have_pmic) 480 clk_disable_unprepare(i2c->clk_pmic); 481 482 clk_disable_unprepare(i2c->clk_main); 483 clk_disable_unprepare(i2c->clk_dma); 484 } 485 486 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 487 { 488 u16 control_reg; 489 u16 intr_stat_reg; 490 u16 ext_conf_val; 491 492 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); 493 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 494 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); 495 496 if (i2c->dev_comp->apdma_sync) { 497 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 498 udelay(10); 499 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 500 udelay(10); 501 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 502 i2c->pdmabase + OFFSET_RST); 503 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 504 OFFSET_SOFTRESET); 505 udelay(10); 506 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 507 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 508 } else { 509 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 510 udelay(50); 511 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 512 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 513 } 514 515 /* Set ioconfig */ 516 if (i2c->use_push_pull) 517 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 518 else 519 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 520 521 if (i2c->dev_comp->dcm) 522 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 523 524 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 525 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 526 if (i2c->dev_comp->ltiming_adjust) 527 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 528 529 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 530 ext_conf_val = I2C_ST_START_CON; 531 else 532 ext_conf_val = I2C_FS_START_CON; 533 534 if (i2c->dev_comp->timing_adjust) { 535 ext_conf_val = i2c->ac_timing.ext; 536 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 537 OFFSET_CLOCK_DIV); 538 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 539 OFFSET_SCL_MIS_COMP_POINT); 540 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 541 OFFSET_SDA_TIMING); 542 543 if (i2c->dev_comp->ltiming_adjust) { 544 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 545 OFFSET_TIMING); 546 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 547 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 548 OFFSET_LTIMING); 549 } else { 550 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 551 OFFSET_SCL_HIGH_LOW_RATIO); 552 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 553 OFFSET_HS_SCL_HIGH_LOW_RATIO); 554 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 555 OFFSET_STA_STO_AC_TIMING); 556 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 557 OFFSET_HS_STA_STO_AC_TIMING); 558 } 559 } 560 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); 561 562 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 563 if (i2c->have_pmic) 564 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 565 566 control_reg = I2C_CONTROL_ACKERR_DET_EN | 567 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 568 if (i2c->dev_comp->dma_sync) 569 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 570 571 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 572 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 573 } 574 575 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 576 { 577 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 578 return &standard_mode_spec; 579 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 580 return &fast_mode_spec; 581 else 582 return &fast_mode_plus_spec; 583 } 584 585 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 586 { 587 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 588 return MAX_HS_STEP_CNT_DIV; 589 else 590 return MAX_STEP_CNT_DIV; 591 } 592 593 /* 594 * Check and Calculate i2c ac-timing 595 * 596 * Hardware design: 597 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 598 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 599 * 600 * Sample_ns is rounded down for xxx_cnt_div would be greater 601 * than the smallest spec. 602 * The sda_timing is chosen as the middle value between 603 * the largest and smallest. 604 */ 605 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 606 unsigned int clk_src, 607 unsigned int check_speed, 608 unsigned int step_cnt, 609 unsigned int sample_cnt) 610 { 611 const struct i2c_spec_values *spec; 612 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 613 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 614 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 615 clk_src); 616 617 if (!i2c->dev_comp->timing_adjust) 618 return 0; 619 620 if (i2c->dev_comp->ltiming_adjust) 621 max_sta_cnt = 0x100; 622 623 spec = mtk_i2c_get_spec(check_speed); 624 625 if (i2c->dev_comp->ltiming_adjust) 626 clk_ns = 1000000000 / clk_src; 627 else 628 clk_ns = sample_ns / 2; 629 630 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 631 i2c->timing_info.scl_int_delay_ns, clk_ns); 632 if (su_sta_cnt > max_sta_cnt) 633 return -1; 634 635 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 636 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 637 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 638 if (low_cnt > step_cnt) { 639 high_cnt = 2 * step_cnt - low_cnt; 640 } else { 641 high_cnt = step_cnt; 642 low_cnt = step_cnt; 643 } 644 } else { 645 return -2; 646 } 647 648 sda_max = spec->max_hd_dat_ns / sample_ns; 649 if (sda_max > low_cnt) 650 sda_max = 0; 651 652 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 653 if (sda_min < low_cnt) 654 sda_min = 0; 655 656 if (sda_min > sda_max) 657 return -3; 658 659 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 660 if (i2c->dev_comp->ltiming_adjust) { 661 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 662 (sample_cnt << 12) | (high_cnt << 8); 663 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 664 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 665 (low_cnt << 9); 666 i2c->ac_timing.ext &= ~GENMASK(7, 1); 667 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 668 } else { 669 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 670 (high_cnt << 6) | low_cnt; 671 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 672 su_sta_cnt; 673 } 674 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 675 i2c->ac_timing.sda_timing |= (1 << 12) | 676 ((sda_max + sda_min) / 2) << 6; 677 } else { 678 if (i2c->dev_comp->ltiming_adjust) { 679 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 680 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 681 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 682 } else { 683 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 684 (high_cnt << 6) | low_cnt; 685 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 686 su_sta_cnt; 687 } 688 689 i2c->ac_timing.sda_timing = (1 << 12) | 690 (sda_max + sda_min) / 2; 691 } 692 693 return 0; 694 } 695 696 /* 697 * Calculate i2c port speed 698 * 699 * Hardware design: 700 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 701 * clock_div: fixed in hardware, but may be various in different SoCs 702 * 703 * The calculation want to pick the highest bus frequency that is still 704 * less than or equal to i2c->speed_hz. The calculation try to get 705 * sample_cnt and step_cn 706 */ 707 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 708 unsigned int target_speed, 709 unsigned int *timing_step_cnt, 710 unsigned int *timing_sample_cnt) 711 { 712 unsigned int step_cnt; 713 unsigned int sample_cnt; 714 unsigned int max_step_cnt; 715 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 716 unsigned int base_step_cnt; 717 unsigned int opt_div; 718 unsigned int best_mul; 719 unsigned int cnt_mul; 720 int ret = -EINVAL; 721 722 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 723 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 724 725 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 726 base_step_cnt = max_step_cnt; 727 /* Find the best combination */ 728 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 729 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 730 731 /* Search for the best pair (sample_cnt, step_cnt) with 732 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 733 * 0 < step_cnt < max_step_cnt 734 * sample_cnt * step_cnt >= opt_div 735 * optimizing for sample_cnt * step_cnt being minimal 736 */ 737 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 738 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 739 cnt_mul = step_cnt * sample_cnt; 740 if (step_cnt > max_step_cnt) 741 continue; 742 743 if (cnt_mul < best_mul) { 744 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 745 target_speed, step_cnt - 1, sample_cnt - 1); 746 if (ret) 747 continue; 748 749 best_mul = cnt_mul; 750 base_sample_cnt = sample_cnt; 751 base_step_cnt = step_cnt; 752 if (best_mul == opt_div) 753 break; 754 } 755 } 756 757 if (ret) 758 return -EINVAL; 759 760 sample_cnt = base_sample_cnt; 761 step_cnt = base_step_cnt; 762 763 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 764 /* In this case, hardware can't support such 765 * low i2c_bus_freq 766 */ 767 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 768 return -EINVAL; 769 } 770 771 *timing_step_cnt = step_cnt - 1; 772 *timing_sample_cnt = sample_cnt - 1; 773 774 return 0; 775 } 776 777 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 778 { 779 unsigned int clk_src; 780 unsigned int step_cnt; 781 unsigned int sample_cnt; 782 unsigned int l_step_cnt; 783 unsigned int l_sample_cnt; 784 unsigned int target_speed; 785 unsigned int clk_div; 786 unsigned int max_clk_div; 787 int ret; 788 789 target_speed = i2c->speed_hz; 790 parent_clk /= i2c->clk_src_div; 791 792 if (i2c->dev_comp->timing_adjust) 793 max_clk_div = MAX_CLOCK_DIV; 794 else 795 max_clk_div = 1; 796 797 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 798 clk_src = parent_clk / clk_div; 799 800 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 801 /* Set master code speed register */ 802 ret = mtk_i2c_calculate_speed(i2c, clk_src, 803 I2C_MAX_FAST_MODE_FREQ, 804 &l_step_cnt, 805 &l_sample_cnt); 806 if (ret < 0) 807 continue; 808 809 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 810 811 /* Set the high speed mode register */ 812 ret = mtk_i2c_calculate_speed(i2c, clk_src, 813 target_speed, &step_cnt, 814 &sample_cnt); 815 if (ret < 0) 816 continue; 817 818 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 819 (sample_cnt << 12) | (step_cnt << 8); 820 821 if (i2c->dev_comp->ltiming_adjust) 822 i2c->ltiming_reg = 823 (l_sample_cnt << 6) | l_step_cnt | 824 (sample_cnt << 12) | (step_cnt << 9); 825 } else { 826 ret = mtk_i2c_calculate_speed(i2c, clk_src, 827 target_speed, &l_step_cnt, 828 &l_sample_cnt); 829 if (ret < 0) 830 continue; 831 832 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 833 834 /* Disable the high speed transaction */ 835 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 836 837 if (i2c->dev_comp->ltiming_adjust) 838 i2c->ltiming_reg = 839 (l_sample_cnt << 6) | l_step_cnt; 840 } 841 842 break; 843 } 844 845 i2c->ac_timing.inter_clk_div = clk_div - 1; 846 847 return 0; 848 } 849 850 static void i2c_dump_register(struct mtk_i2c *i2c) 851 { 852 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", 853 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), 854 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); 855 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", 856 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), 857 mtk_i2c_readw(i2c, OFFSET_CONTROL)); 858 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", 859 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), 860 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); 861 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", 862 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), 863 mtk_i2c_readw(i2c, OFFSET_TIMING)); 864 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", 865 mtk_i2c_readw(i2c, OFFSET_START), 866 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); 867 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", 868 mtk_i2c_readw(i2c, OFFSET_HS), 869 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); 870 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", 871 mtk_i2c_readw(i2c, OFFSET_DCM_EN), 872 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); 873 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", 874 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), 875 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); 876 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", 877 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), 878 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); 879 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { 880 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", 881 mtk_i2c_readw(i2c, OFFSET_LTIMING), 882 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); 883 } 884 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", 885 readl(i2c->pdmabase + OFFSET_INT_FLAG), 886 readl(i2c->pdmabase + OFFSET_INT_EN)); 887 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", 888 readl(i2c->pdmabase + OFFSET_EN), 889 readl(i2c->pdmabase + OFFSET_CON)); 890 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", 891 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), 892 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); 893 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", 894 readl(i2c->pdmabase + OFFSET_TX_LEN), 895 readl(i2c->pdmabase + OFFSET_RX_LEN)); 896 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", 897 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), 898 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); 899 } 900 901 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 902 int num, int left_num) 903 { 904 u16 addr_reg; 905 u16 start_reg; 906 u16 control_reg; 907 u16 restart_flag = 0; 908 u16 dma_sync = 0; 909 u32 reg_4g_mode; 910 u32 reg_dma_reset; 911 u8 *dma_rd_buf = NULL; 912 u8 *dma_wr_buf = NULL; 913 dma_addr_t rpaddr = 0; 914 dma_addr_t wpaddr = 0; 915 int ret; 916 917 i2c->irq_stat = 0; 918 919 if (i2c->auto_restart) 920 restart_flag = I2C_RS_TRANSFER; 921 922 reinit_completion(&i2c->msg_complete); 923 924 if (i2c->dev_comp->apdma_sync && 925 i2c->op != I2C_MASTER_WRRD && num > 1) { 926 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); 927 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, 928 i2c->pdmabase + OFFSET_RST); 929 930 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, 931 reg_dma_reset, 932 !(reg_dma_reset & I2C_DMA_WARM_RST), 933 0, 100); 934 if (ret) { 935 dev_err(i2c->dev, "DMA warm reset timeout\n"); 936 return -ETIMEDOUT; 937 } 938 939 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 940 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); 941 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 942 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, 943 OFFSET_DEBUGCTRL); 944 } 945 946 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 947 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 948 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 949 control_reg |= I2C_CONTROL_RS; 950 951 if (i2c->op == I2C_MASTER_WRRD) 952 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 953 954 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 955 956 addr_reg = i2c_8bit_addr_from_msg(msgs); 957 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 958 959 /* Clear interrupt status */ 960 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 961 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 962 963 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 964 965 /* Enable interrupt */ 966 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 967 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 968 969 /* Set transfer and transaction len */ 970 if (i2c->op == I2C_MASTER_WRRD) { 971 if (i2c->dev_comp->aux_len_reg) { 972 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 973 mtk_i2c_writew(i2c, (msgs + 1)->len, 974 OFFSET_TRANSFER_LEN_AUX); 975 } else { 976 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 977 OFFSET_TRANSFER_LEN); 978 } 979 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 980 } else { 981 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 982 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 983 } 984 985 if (i2c->dev_comp->apdma_sync) { 986 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 987 if (i2c->op == I2C_MASTER_WRRD) 988 dma_sync |= I2C_DMA_DIR_CHANGE; 989 } 990 991 /* Prepare buffer data to start transfer */ 992 if (i2c->op == I2C_MASTER_RD) { 993 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 994 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 995 996 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 997 if (!dma_rd_buf) 998 return -ENOMEM; 999 1000 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1001 msgs->len, DMA_FROM_DEVICE); 1002 if (dma_mapping_error(i2c->dev, rpaddr)) { 1003 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 1004 1005 return -ENOMEM; 1006 } 1007 1008 if (i2c->dev_comp->max_dma_support > 32) { 1009 reg_4g_mode = upper_32_bits(rpaddr); 1010 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1011 } 1012 1013 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1014 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 1015 } else if (i2c->op == I2C_MASTER_WR) { 1016 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1017 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 1018 1019 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1020 if (!dma_wr_buf) 1021 return -ENOMEM; 1022 1023 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1024 msgs->len, DMA_TO_DEVICE); 1025 if (dma_mapping_error(i2c->dev, wpaddr)) { 1026 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1027 1028 return -ENOMEM; 1029 } 1030 1031 if (i2c->dev_comp->max_dma_support > 32) { 1032 reg_4g_mode = upper_32_bits(wpaddr); 1033 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1034 } 1035 1036 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1037 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1038 } else { 1039 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 1040 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 1041 1042 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1043 if (!dma_wr_buf) 1044 return -ENOMEM; 1045 1046 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1047 msgs->len, DMA_TO_DEVICE); 1048 if (dma_mapping_error(i2c->dev, wpaddr)) { 1049 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1050 1051 return -ENOMEM; 1052 } 1053 1054 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 1055 if (!dma_rd_buf) { 1056 dma_unmap_single(i2c->dev, wpaddr, 1057 msgs->len, DMA_TO_DEVICE); 1058 1059 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1060 1061 return -ENOMEM; 1062 } 1063 1064 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1065 (msgs + 1)->len, 1066 DMA_FROM_DEVICE); 1067 if (dma_mapping_error(i2c->dev, rpaddr)) { 1068 dma_unmap_single(i2c->dev, wpaddr, 1069 msgs->len, DMA_TO_DEVICE); 1070 1071 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1072 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 1073 1074 return -ENOMEM; 1075 } 1076 1077 if (i2c->dev_comp->max_dma_support > 32) { 1078 reg_4g_mode = upper_32_bits(wpaddr); 1079 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1080 1081 reg_4g_mode = upper_32_bits(rpaddr); 1082 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1083 } 1084 1085 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1086 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1087 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1088 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 1089 } 1090 1091 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 1092 1093 if (!i2c->auto_restart) { 1094 start_reg = I2C_TRANSAC_START; 1095 } else { 1096 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1097 if (left_num >= 1) 1098 start_reg |= I2C_RS_MUL_CNFG; 1099 } 1100 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1101 1102 ret = wait_for_completion_timeout(&i2c->msg_complete, 1103 i2c->adap.timeout); 1104 1105 /* Clear interrupt mask */ 1106 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1107 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1108 1109 if (i2c->op == I2C_MASTER_WR) { 1110 dma_unmap_single(i2c->dev, wpaddr, 1111 msgs->len, DMA_TO_DEVICE); 1112 1113 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1114 } else if (i2c->op == I2C_MASTER_RD) { 1115 dma_unmap_single(i2c->dev, rpaddr, 1116 msgs->len, DMA_FROM_DEVICE); 1117 1118 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1119 } else { 1120 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1121 DMA_TO_DEVICE); 1122 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1123 DMA_FROM_DEVICE); 1124 1125 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1126 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1127 } 1128 1129 if (ret == 0) { 1130 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1131 i2c_dump_register(i2c); 1132 mtk_i2c_init_hw(i2c); 1133 return -ETIMEDOUT; 1134 } 1135 1136 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1137 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1138 mtk_i2c_init_hw(i2c); 1139 return -ENXIO; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1146 struct i2c_msg msgs[], int num) 1147 { 1148 int ret; 1149 int left_num = num; 1150 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1151 1152 ret = mtk_i2c_clock_enable(i2c); 1153 if (ret) 1154 return ret; 1155 1156 i2c->auto_restart = i2c->dev_comp->auto_restart; 1157 1158 /* checking if we can skip restart and optimize using WRRD mode */ 1159 if (i2c->auto_restart && num == 2) { 1160 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1161 msgs[0].addr == msgs[1].addr) { 1162 i2c->auto_restart = 0; 1163 } 1164 } 1165 1166 if (i2c->auto_restart && num >= 2 && 1167 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1168 /* ignore the first restart irq after the master code, 1169 * otherwise the first transfer will be discarded. 1170 */ 1171 i2c->ignore_restart_irq = true; 1172 else 1173 i2c->ignore_restart_irq = false; 1174 1175 while (left_num--) { 1176 if (!msgs->buf) { 1177 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1178 ret = -EINVAL; 1179 goto err_exit; 1180 } 1181 1182 if (msgs->flags & I2C_M_RD) 1183 i2c->op = I2C_MASTER_RD; 1184 else 1185 i2c->op = I2C_MASTER_WR; 1186 1187 if (!i2c->auto_restart) { 1188 if (num > 1) { 1189 /* combined two messages into one transaction */ 1190 i2c->op = I2C_MASTER_WRRD; 1191 left_num--; 1192 } 1193 } 1194 1195 /* always use DMA mode. */ 1196 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1197 if (ret < 0) 1198 goto err_exit; 1199 1200 msgs++; 1201 } 1202 /* the return value is number of executed messages */ 1203 ret = num; 1204 1205 err_exit: 1206 mtk_i2c_clock_disable(i2c); 1207 return ret; 1208 } 1209 1210 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1211 { 1212 struct mtk_i2c *i2c = dev_id; 1213 u16 restart_flag = 0; 1214 u16 intr_stat; 1215 1216 if (i2c->auto_restart) 1217 restart_flag = I2C_RS_TRANSFER; 1218 1219 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1220 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1221 1222 /* 1223 * when occurs ack error, i2c controller generate two interrupts 1224 * first is the ack error interrupt, then the complete interrupt 1225 * i2c->irq_stat need keep the two interrupt value. 1226 */ 1227 i2c->irq_stat |= intr_stat; 1228 1229 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1230 i2c->ignore_restart_irq = false; 1231 i2c->irq_stat = 0; 1232 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1233 I2C_TRANSAC_START, OFFSET_START); 1234 } else { 1235 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1236 complete(&i2c->msg_complete); 1237 } 1238 1239 return IRQ_HANDLED; 1240 } 1241 1242 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1243 { 1244 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1245 return I2C_FUNC_I2C | 1246 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1247 else 1248 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1249 } 1250 1251 static const struct i2c_algorithm mtk_i2c_algorithm = { 1252 .master_xfer = mtk_i2c_transfer, 1253 .functionality = mtk_i2c_functionality, 1254 }; 1255 1256 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1257 { 1258 int ret; 1259 1260 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1261 if (ret < 0) 1262 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1263 1264 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1265 if (ret < 0) 1266 return ret; 1267 1268 if (i2c->clk_src_div == 0) 1269 return -EINVAL; 1270 1271 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1272 i2c->use_push_pull = 1273 of_property_read_bool(np, "mediatek,use-push-pull"); 1274 1275 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1276 1277 return 0; 1278 } 1279 1280 static int mtk_i2c_probe(struct platform_device *pdev) 1281 { 1282 int ret = 0; 1283 struct mtk_i2c *i2c; 1284 struct clk *clk; 1285 struct resource *res; 1286 int irq; 1287 1288 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1289 if (!i2c) 1290 return -ENOMEM; 1291 1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1293 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1294 if (IS_ERR(i2c->base)) 1295 return PTR_ERR(i2c->base); 1296 1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1298 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1299 if (IS_ERR(i2c->pdmabase)) 1300 return PTR_ERR(i2c->pdmabase); 1301 1302 irq = platform_get_irq(pdev, 0); 1303 if (irq < 0) 1304 return irq; 1305 1306 init_completion(&i2c->msg_complete); 1307 1308 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1309 i2c->adap.dev.of_node = pdev->dev.of_node; 1310 i2c->dev = &pdev->dev; 1311 i2c->adap.dev.parent = &pdev->dev; 1312 i2c->adap.owner = THIS_MODULE; 1313 i2c->adap.algo = &mtk_i2c_algorithm; 1314 i2c->adap.quirks = i2c->dev_comp->quirks; 1315 i2c->adap.timeout = 2 * HZ; 1316 i2c->adap.retries = 1; 1317 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1318 if (IS_ERR(i2c->adap.bus_regulator)) { 1319 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1320 i2c->adap.bus_regulator = NULL; 1321 else 1322 return PTR_ERR(i2c->adap.bus_regulator); 1323 } 1324 1325 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1326 if (ret) 1327 return -EINVAL; 1328 1329 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1330 return -EINVAL; 1331 1332 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1333 if (IS_ERR(i2c->clk_main)) { 1334 dev_err(&pdev->dev, "cannot get main clock\n"); 1335 return PTR_ERR(i2c->clk_main); 1336 } 1337 1338 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1339 if (IS_ERR(i2c->clk_dma)) { 1340 dev_err(&pdev->dev, "cannot get dma clock\n"); 1341 return PTR_ERR(i2c->clk_dma); 1342 } 1343 1344 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1345 if (IS_ERR(i2c->clk_arb)) 1346 i2c->clk_arb = NULL; 1347 1348 clk = i2c->clk_main; 1349 if (i2c->have_pmic) { 1350 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1351 if (IS_ERR(i2c->clk_pmic)) { 1352 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1353 return PTR_ERR(i2c->clk_pmic); 1354 } 1355 clk = i2c->clk_pmic; 1356 } 1357 1358 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1359 1360 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1361 if (ret) { 1362 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1363 return -EINVAL; 1364 } 1365 1366 if (i2c->dev_comp->max_dma_support > 32) { 1367 ret = dma_set_mask(&pdev->dev, 1368 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1369 if (ret) { 1370 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1371 return ret; 1372 } 1373 } 1374 1375 ret = mtk_i2c_clock_enable(i2c); 1376 if (ret) { 1377 dev_err(&pdev->dev, "clock enable failed!\n"); 1378 return ret; 1379 } 1380 mtk_i2c_init_hw(i2c); 1381 mtk_i2c_clock_disable(i2c); 1382 1383 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1384 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1385 dev_name(&pdev->dev), i2c); 1386 if (ret < 0) { 1387 dev_err(&pdev->dev, 1388 "Request I2C IRQ %d fail\n", irq); 1389 return ret; 1390 } 1391 1392 i2c_set_adapdata(&i2c->adap, i2c); 1393 ret = i2c_add_adapter(&i2c->adap); 1394 if (ret) 1395 return ret; 1396 1397 platform_set_drvdata(pdev, i2c); 1398 1399 return 0; 1400 } 1401 1402 static int mtk_i2c_remove(struct platform_device *pdev) 1403 { 1404 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1405 1406 i2c_del_adapter(&i2c->adap); 1407 1408 return 0; 1409 } 1410 1411 #ifdef CONFIG_PM_SLEEP 1412 static int mtk_i2c_suspend_noirq(struct device *dev) 1413 { 1414 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1415 1416 i2c_mark_adapter_suspended(&i2c->adap); 1417 1418 return 0; 1419 } 1420 1421 static int mtk_i2c_resume_noirq(struct device *dev) 1422 { 1423 int ret; 1424 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1425 1426 ret = mtk_i2c_clock_enable(i2c); 1427 if (ret) { 1428 dev_err(dev, "clock enable failed!\n"); 1429 return ret; 1430 } 1431 1432 mtk_i2c_init_hw(i2c); 1433 1434 mtk_i2c_clock_disable(i2c); 1435 1436 i2c_mark_adapter_resumed(&i2c->adap); 1437 1438 return 0; 1439 } 1440 #endif 1441 1442 static const struct dev_pm_ops mtk_i2c_pm = { 1443 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1444 mtk_i2c_resume_noirq) 1445 }; 1446 1447 static struct platform_driver mtk_i2c_driver = { 1448 .probe = mtk_i2c_probe, 1449 .remove = mtk_i2c_remove, 1450 .driver = { 1451 .name = I2C_DRV_NAME, 1452 .pm = &mtk_i2c_pm, 1453 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1454 }, 1455 }; 1456 1457 module_platform_driver(mtk_i2c_driver); 1458 1459 MODULE_LICENSE("GPL v2"); 1460 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1461 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1462