11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2ce38815dSXudong Chen /* 3ce38815dSXudong Chen * Copyright (c) 2014 MediaTek Inc. 4ce38815dSXudong Chen * Author: Xudong Chen <xudong.chen@mediatek.com> 5ce38815dSXudong Chen */ 6ce38815dSXudong Chen 7ce38815dSXudong Chen #include <linux/clk.h> 8ce38815dSXudong Chen #include <linux/completion.h> 9ce38815dSXudong Chen #include <linux/delay.h> 10ce38815dSXudong Chen #include <linux/device.h> 11ce38815dSXudong Chen #include <linux/dma-mapping.h> 12ce38815dSXudong Chen #include <linux/err.h> 13ce38815dSXudong Chen #include <linux/errno.h> 14ce38815dSXudong Chen #include <linux/i2c.h> 15ce38815dSXudong Chen #include <linux/init.h> 16ce38815dSXudong Chen #include <linux/interrupt.h> 17ce38815dSXudong Chen #include <linux/io.h> 18ce38815dSXudong Chen #include <linux/kernel.h> 19ce38815dSXudong Chen #include <linux/mm.h> 20ce38815dSXudong Chen #include <linux/module.h> 21ce38815dSXudong Chen #include <linux/of_address.h> 226e29577fSRyder Lee #include <linux/of_device.h> 23ce38815dSXudong Chen #include <linux/of_irq.h> 24ce38815dSXudong Chen #include <linux/platform_device.h> 25ce38815dSXudong Chen #include <linux/scatterlist.h> 26ce38815dSXudong Chen #include <linux/sched.h> 27ce38815dSXudong Chen #include <linux/slab.h> 28ce38815dSXudong Chen 29b2ed11e2SEddie Huang #define I2C_RS_TRANSFER (1 << 4) 30cad6dc5dSQii Wang #define I2C_ARB_LOST (1 << 3) 31ce38815dSXudong Chen #define I2C_HS_NACKERR (1 << 2) 32ce38815dSXudong Chen #define I2C_ACKERR (1 << 1) 33ce38815dSXudong Chen #define I2C_TRANSAC_COMP (1 << 0) 34ce38815dSXudong Chen #define I2C_TRANSAC_START (1 << 0) 35b2ed11e2SEddie Huang #define I2C_RS_MUL_CNFG (1 << 15) 36b2ed11e2SEddie Huang #define I2C_RS_MUL_TRIG (1 << 14) 37ce38815dSXudong Chen #define I2C_DCM_DISABLE 0x0000 38ce38815dSXudong Chen #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39ce38815dSXudong Chen #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40ce38815dSXudong Chen #define I2C_SOFT_RST 0x0001 41ce38815dSXudong Chen #define I2C_FIFO_ADDR_CLR 0x0001 42ce38815dSXudong Chen #define I2C_DELAY_LEN 0x0002 43ce38815dSXudong Chen #define I2C_TIME_CLR_VALUE 0x0000 44ce38815dSXudong Chen #define I2C_TIME_DEFAULT_VALUE 0x0003 45ce38815dSXudong Chen #define I2C_WRRD_TRANAC_VALUE 0x0002 46ce38815dSXudong Chen #define I2C_RD_TRANAC_VALUE 0x0001 47be5ce0e9SQii Wang #define I2C_SCL_MIS_COMP_VALUE 0x0000 48ce38815dSXudong Chen 49ce38815dSXudong Chen #define I2C_DMA_CON_TX 0x0000 50ce38815dSXudong Chen #define I2C_DMA_CON_RX 0x0001 518426fe70SQii Wang #define I2C_DMA_ASYNC_MODE 0x0004 528426fe70SQii Wang #define I2C_DMA_SKIP_CONFIG 0x0010 538426fe70SQii Wang #define I2C_DMA_DIR_CHANGE 0x0200 54ce38815dSXudong Chen #define I2C_DMA_START_EN 0x0001 55ce38815dSXudong Chen #define I2C_DMA_INT_FLAG_NONE 0x0000 56ce38815dSXudong Chen #define I2C_DMA_CLR_FLAG 0x0000 57ea89ef1fSEddie Huang #define I2C_DMA_HARD_RST 0x0002 58f4f4fed6SLiguo Zhang #define I2C_DMA_4G_MODE 0x0001 59ce38815dSXudong Chen 60ce38815dSXudong Chen #define MAX_SAMPLE_CNT_DIV 8 61ce38815dSXudong Chen #define MAX_STEP_CNT_DIV 64 62be5ce0e9SQii Wang #define MAX_CLOCK_DIV 256 63ce38815dSXudong Chen #define MAX_HS_STEP_CNT_DIV 8 64be5ce0e9SQii Wang #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 65be5ce0e9SQii Wang #define I2C_FAST_MODE_BUFFER (300 / 2) 66be5ce0e9SQii Wang #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 67ce38815dSXudong Chen 68ce38815dSXudong Chen #define I2C_CONTROL_RS (0x1 << 1) 69ce38815dSXudong Chen #define I2C_CONTROL_DMA_EN (0x1 << 2) 70ce38815dSXudong Chen #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 71ce38815dSXudong Chen #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 72ce38815dSXudong Chen #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 73ce38815dSXudong Chen #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 74a15c91baSQii Wang #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 75a15c91baSQii Wang #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 76ce38815dSXudong Chen #define I2C_CONTROL_WRAPPER (0x1 << 0) 77ce38815dSXudong Chen 78ce38815dSXudong Chen #define I2C_DRV_NAME "i2c-mt65xx" 79ce38815dSXudong Chen 80ce38815dSXudong Chen enum DMA_REGS_OFFSET { 81ce38815dSXudong Chen OFFSET_INT_FLAG = 0x0, 82ce38815dSXudong Chen OFFSET_INT_EN = 0x04, 83ce38815dSXudong Chen OFFSET_EN = 0x08, 84ea89ef1fSEddie Huang OFFSET_RST = 0x0c, 85ce38815dSXudong Chen OFFSET_CON = 0x18, 86ce38815dSXudong Chen OFFSET_TX_MEM_ADDR = 0x1c, 87ce38815dSXudong Chen OFFSET_RX_MEM_ADDR = 0x20, 88ce38815dSXudong Chen OFFSET_TX_LEN = 0x24, 89ce38815dSXudong Chen OFFSET_RX_LEN = 0x28, 90f4f4fed6SLiguo Zhang OFFSET_TX_4G_MODE = 0x54, 91f4f4fed6SLiguo Zhang OFFSET_RX_4G_MODE = 0x58, 92ce38815dSXudong Chen }; 93ce38815dSXudong Chen 94ce38815dSXudong Chen enum i2c_trans_st_rs { 95ce38815dSXudong Chen I2C_TRANS_STOP = 0, 96ce38815dSXudong Chen I2C_TRANS_REPEATED_START, 97ce38815dSXudong Chen }; 98ce38815dSXudong Chen 99ce38815dSXudong Chen enum mtk_trans_op { 100ce38815dSXudong Chen I2C_MASTER_WR = 1, 101ce38815dSXudong Chen I2C_MASTER_RD, 102ce38815dSXudong Chen I2C_MASTER_WRRD, 103ce38815dSXudong Chen }; 104ce38815dSXudong Chen 105ce38815dSXudong Chen enum I2C_REGS_OFFSET { 106bc6eaf17SQii Wang OFFSET_DATA_PORT, 107bc6eaf17SQii Wang OFFSET_SLAVE_ADDR, 108bc6eaf17SQii Wang OFFSET_INTR_MASK, 109bc6eaf17SQii Wang OFFSET_INTR_STAT, 110bc6eaf17SQii Wang OFFSET_CONTROL, 111bc6eaf17SQii Wang OFFSET_TRANSFER_LEN, 112bc6eaf17SQii Wang OFFSET_TRANSAC_LEN, 113bc6eaf17SQii Wang OFFSET_DELAY_LEN, 114bc6eaf17SQii Wang OFFSET_TIMING, 115bc6eaf17SQii Wang OFFSET_START, 116bc6eaf17SQii Wang OFFSET_EXT_CONF, 117bc6eaf17SQii Wang OFFSET_FIFO_STAT, 118bc6eaf17SQii Wang OFFSET_FIFO_THRESH, 119bc6eaf17SQii Wang OFFSET_FIFO_ADDR_CLR, 120bc6eaf17SQii Wang OFFSET_IO_CONFIG, 121bc6eaf17SQii Wang OFFSET_RSV_DEBUG, 122bc6eaf17SQii Wang OFFSET_HS, 123bc6eaf17SQii Wang OFFSET_SOFTRESET, 124bc6eaf17SQii Wang OFFSET_DCM_EN, 125bc6eaf17SQii Wang OFFSET_PATH_DIR, 126bc6eaf17SQii Wang OFFSET_DEBUGSTAT, 127bc6eaf17SQii Wang OFFSET_DEBUGCTRL, 128bc6eaf17SQii Wang OFFSET_TRANSFER_LEN_AUX, 129bc6eaf17SQii Wang OFFSET_CLOCK_DIV, 13025708278SQii Wang OFFSET_LTIMING, 131be5ce0e9SQii Wang OFFSET_SCL_HIGH_LOW_RATIO, 132be5ce0e9SQii Wang OFFSET_HS_SCL_HIGH_LOW_RATIO, 133be5ce0e9SQii Wang OFFSET_SCL_MIS_COMP_POINT, 134be5ce0e9SQii Wang OFFSET_STA_STO_AC_TIMING, 135be5ce0e9SQii Wang OFFSET_HS_STA_STO_AC_TIMING, 136be5ce0e9SQii Wang OFFSET_SDA_TIMING, 137bc6eaf17SQii Wang }; 138bc6eaf17SQii Wang 139bc6eaf17SQii Wang static const u16 mt_i2c_regs_v1[] = { 140bc6eaf17SQii Wang [OFFSET_DATA_PORT] = 0x0, 141bc6eaf17SQii Wang [OFFSET_SLAVE_ADDR] = 0x4, 142bc6eaf17SQii Wang [OFFSET_INTR_MASK] = 0x8, 143bc6eaf17SQii Wang [OFFSET_INTR_STAT] = 0xc, 144bc6eaf17SQii Wang [OFFSET_CONTROL] = 0x10, 145bc6eaf17SQii Wang [OFFSET_TRANSFER_LEN] = 0x14, 146bc6eaf17SQii Wang [OFFSET_TRANSAC_LEN] = 0x18, 147bc6eaf17SQii Wang [OFFSET_DELAY_LEN] = 0x1c, 148bc6eaf17SQii Wang [OFFSET_TIMING] = 0x20, 149bc6eaf17SQii Wang [OFFSET_START] = 0x24, 150bc6eaf17SQii Wang [OFFSET_EXT_CONF] = 0x28, 151bc6eaf17SQii Wang [OFFSET_FIFO_STAT] = 0x30, 152bc6eaf17SQii Wang [OFFSET_FIFO_THRESH] = 0x34, 153bc6eaf17SQii Wang [OFFSET_FIFO_ADDR_CLR] = 0x38, 154bc6eaf17SQii Wang [OFFSET_IO_CONFIG] = 0x40, 155bc6eaf17SQii Wang [OFFSET_RSV_DEBUG] = 0x44, 156bc6eaf17SQii Wang [OFFSET_HS] = 0x48, 157bc6eaf17SQii Wang [OFFSET_SOFTRESET] = 0x50, 158bc6eaf17SQii Wang [OFFSET_DCM_EN] = 0x54, 159bc6eaf17SQii Wang [OFFSET_PATH_DIR] = 0x60, 160bc6eaf17SQii Wang [OFFSET_DEBUGSTAT] = 0x64, 161bc6eaf17SQii Wang [OFFSET_DEBUGCTRL] = 0x68, 162bc6eaf17SQii Wang [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 163bc6eaf17SQii Wang [OFFSET_CLOCK_DIV] = 0x70, 164be5ce0e9SQii Wang [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 165be5ce0e9SQii Wang [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 166be5ce0e9SQii Wang [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 167be5ce0e9SQii Wang [OFFSET_STA_STO_AC_TIMING] = 0x80, 168be5ce0e9SQii Wang [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 169be5ce0e9SQii Wang [OFFSET_SDA_TIMING] = 0x88, 170ce38815dSXudong Chen }; 171ce38815dSXudong Chen 17225708278SQii Wang static const u16 mt_i2c_regs_v2[] = { 17325708278SQii Wang [OFFSET_DATA_PORT] = 0x0, 17425708278SQii Wang [OFFSET_SLAVE_ADDR] = 0x4, 17525708278SQii Wang [OFFSET_INTR_MASK] = 0x8, 17625708278SQii Wang [OFFSET_INTR_STAT] = 0xc, 17725708278SQii Wang [OFFSET_CONTROL] = 0x10, 17825708278SQii Wang [OFFSET_TRANSFER_LEN] = 0x14, 17925708278SQii Wang [OFFSET_TRANSAC_LEN] = 0x18, 18025708278SQii Wang [OFFSET_DELAY_LEN] = 0x1c, 18125708278SQii Wang [OFFSET_TIMING] = 0x20, 18225708278SQii Wang [OFFSET_START] = 0x24, 18325708278SQii Wang [OFFSET_EXT_CONF] = 0x28, 18425708278SQii Wang [OFFSET_LTIMING] = 0x2c, 18525708278SQii Wang [OFFSET_HS] = 0x30, 18625708278SQii Wang [OFFSET_IO_CONFIG] = 0x34, 18725708278SQii Wang [OFFSET_FIFO_ADDR_CLR] = 0x38, 188be5ce0e9SQii Wang [OFFSET_SDA_TIMING] = 0x3c, 18925708278SQii Wang [OFFSET_TRANSFER_LEN_AUX] = 0x44, 19025708278SQii Wang [OFFSET_CLOCK_DIV] = 0x48, 19125708278SQii Wang [OFFSET_SOFTRESET] = 0x50, 192be5ce0e9SQii Wang [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 19325708278SQii Wang [OFFSET_DEBUGSTAT] = 0xe0, 19425708278SQii Wang [OFFSET_DEBUGCTRL] = 0xe8, 19525708278SQii Wang [OFFSET_FIFO_STAT] = 0xf4, 19625708278SQii Wang [OFFSET_FIFO_THRESH] = 0xf8, 19725708278SQii Wang [OFFSET_DCM_EN] = 0xf88, 19825708278SQii Wang }; 19925708278SQii Wang 200ce38815dSXudong Chen struct mtk_i2c_compatible { 201ce38815dSXudong Chen const struct i2c_adapter_quirks *quirks; 202bc6eaf17SQii Wang const u16 *regs; 203ce38815dSXudong Chen unsigned char pmic_i2c: 1; 204ce38815dSXudong Chen unsigned char dcm: 1; 205b2ed11e2SEddie Huang unsigned char auto_restart: 1; 206173b77e8SLiguo Zhang unsigned char aux_len_reg: 1; 207f4f4fed6SLiguo Zhang unsigned char support_33bits: 1; 2085a10e7d7SJun Gao unsigned char timing_adjust: 1; 209a15c91baSQii Wang unsigned char dma_sync: 1; 21025708278SQii Wang unsigned char ltiming_adjust: 1; 2118426fe70SQii Wang unsigned char apdma_sync: 1; 212ce38815dSXudong Chen }; 213ce38815dSXudong Chen 214be5ce0e9SQii Wang struct mtk_i2c_ac_timing { 215be5ce0e9SQii Wang u16 htiming; 216be5ce0e9SQii Wang u16 ltiming; 217be5ce0e9SQii Wang u16 hs; 218be5ce0e9SQii Wang u16 ext; 219be5ce0e9SQii Wang u16 inter_clk_div; 220be5ce0e9SQii Wang u16 scl_hl_ratio; 221be5ce0e9SQii Wang u16 hs_scl_hl_ratio; 222be5ce0e9SQii Wang u16 sta_stop; 223be5ce0e9SQii Wang u16 hs_sta_stop; 224be5ce0e9SQii Wang u16 sda_timing; 225be5ce0e9SQii Wang }; 226be5ce0e9SQii Wang 227ce38815dSXudong Chen struct mtk_i2c { 228ce38815dSXudong Chen struct i2c_adapter adap; /* i2c host adapter */ 229ce38815dSXudong Chen struct device *dev; 230ce38815dSXudong Chen struct completion msg_complete; 231ce38815dSXudong Chen 232ce38815dSXudong Chen /* set in i2c probe */ 233ce38815dSXudong Chen void __iomem *base; /* i2c base addr */ 234ce38815dSXudong Chen void __iomem *pdmabase; /* dma base address*/ 235ce38815dSXudong Chen struct clk *clk_main; /* main clock for i2c bus */ 236ce38815dSXudong Chen struct clk *clk_dma; /* DMA clock for i2c via DMA */ 237ce38815dSXudong Chen struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 238cad6dc5dSQii Wang struct clk *clk_arb; /* Arbitrator clock for i2c */ 239ce38815dSXudong Chen bool have_pmic; /* can use i2c pins from PMIC */ 240ce38815dSXudong Chen bool use_push_pull; /* IO config push-pull mode */ 241ce38815dSXudong Chen 242ce38815dSXudong Chen u16 irq_stat; /* interrupt status */ 243f2326401SJun Gao unsigned int clk_src_div; 244ce38815dSXudong Chen unsigned int speed_hz; /* The speed in transfer */ 245ce38815dSXudong Chen enum mtk_trans_op op; 246ce38815dSXudong Chen u16 timing_reg; 247ce38815dSXudong Chen u16 high_speed_reg; 24825708278SQii Wang u16 ltiming_reg; 249173b77e8SLiguo Zhang unsigned char auto_restart; 2508378d01fSLiguo Zhang bool ignore_restart_irq; 251be5ce0e9SQii Wang struct mtk_i2c_ac_timing ac_timing; 252ce38815dSXudong Chen const struct mtk_i2c_compatible *dev_comp; 253ce38815dSXudong Chen }; 254ce38815dSXudong Chen 255be5ce0e9SQii Wang /** 256be5ce0e9SQii Wang * struct i2c_spec_values: 257be5ce0e9SQii Wang * min_low_ns: min LOW period of the SCL clock 258be5ce0e9SQii Wang * min_su_sta_ns: min set-up time for a repeated START condition 259be5ce0e9SQii Wang * max_hd_dat_ns: max data hold time 260be5ce0e9SQii Wang * min_su_dat_ns: min data set-up time 261be5ce0e9SQii Wang */ 262be5ce0e9SQii Wang struct i2c_spec_values { 263be5ce0e9SQii Wang unsigned int min_low_ns; 264be5ce0e9SQii Wang unsigned int min_high_ns; 265be5ce0e9SQii Wang unsigned int min_su_sta_ns; 266be5ce0e9SQii Wang unsigned int max_hd_dat_ns; 267be5ce0e9SQii Wang unsigned int min_su_dat_ns; 268be5ce0e9SQii Wang }; 269be5ce0e9SQii Wang 270be5ce0e9SQii Wang static const struct i2c_spec_values standard_mode_spec = { 271be5ce0e9SQii Wang .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 272be5ce0e9SQii Wang .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 273be5ce0e9SQii Wang .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 274be5ce0e9SQii Wang .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 275be5ce0e9SQii Wang }; 276be5ce0e9SQii Wang 277be5ce0e9SQii Wang static const struct i2c_spec_values fast_mode_spec = { 278be5ce0e9SQii Wang .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 279be5ce0e9SQii Wang .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 280be5ce0e9SQii Wang .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 281be5ce0e9SQii Wang .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 282be5ce0e9SQii Wang }; 283be5ce0e9SQii Wang 284be5ce0e9SQii Wang static const struct i2c_spec_values fast_mode_plus_spec = { 285be5ce0e9SQii Wang .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 286be5ce0e9SQii Wang .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 287be5ce0e9SQii Wang .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 288be5ce0e9SQii Wang .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 289be5ce0e9SQii Wang }; 290be5ce0e9SQii Wang 291ce38815dSXudong Chen static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 292ce38815dSXudong Chen .flags = I2C_AQ_COMB_WRITE_THEN_READ, 293ce38815dSXudong Chen .max_num_msgs = 1, 294ce38815dSXudong Chen .max_write_len = 255, 295ce38815dSXudong Chen .max_read_len = 255, 296ce38815dSXudong Chen .max_comb_1st_msg_len = 255, 297ce38815dSXudong Chen .max_comb_2nd_msg_len = 31, 298ce38815dSXudong Chen }; 299ce38815dSXudong Chen 3001304fe09SJun Gao static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 3011304fe09SJun Gao .max_num_msgs = 255, 3021304fe09SJun Gao }; 3031304fe09SJun Gao 304abf4923eSHsin-Yi Wang static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 305abf4923eSHsin-Yi Wang .flags = I2C_AQ_NO_ZERO_LEN, 306abf4923eSHsin-Yi Wang }; 307abf4923eSHsin-Yi Wang 3085a10e7d7SJun Gao static const struct mtk_i2c_compatible mt2712_compat = { 309bc6eaf17SQii Wang .regs = mt_i2c_regs_v1, 3105a10e7d7SJun Gao .pmic_i2c = 0, 3115a10e7d7SJun Gao .dcm = 1, 3125a10e7d7SJun Gao .auto_restart = 1, 3135a10e7d7SJun Gao .aux_len_reg = 1, 3145a10e7d7SJun Gao .support_33bits = 1, 3155a10e7d7SJun Gao .timing_adjust = 1, 316a15c91baSQii Wang .dma_sync = 0, 31725708278SQii Wang .ltiming_adjust = 0, 3188426fe70SQii Wang .apdma_sync = 0, 3195a10e7d7SJun Gao }; 3205a10e7d7SJun Gao 321ce38815dSXudong Chen static const struct mtk_i2c_compatible mt6577_compat = { 322ce38815dSXudong Chen .quirks = &mt6577_i2c_quirks, 323bc6eaf17SQii Wang .regs = mt_i2c_regs_v1, 324ce38815dSXudong Chen .pmic_i2c = 0, 325ce38815dSXudong Chen .dcm = 1, 326b2ed11e2SEddie Huang .auto_restart = 0, 327173b77e8SLiguo Zhang .aux_len_reg = 0, 328f4f4fed6SLiguo Zhang .support_33bits = 0, 3295a10e7d7SJun Gao .timing_adjust = 0, 330a15c91baSQii Wang .dma_sync = 0, 33125708278SQii Wang .ltiming_adjust = 0, 3328426fe70SQii Wang .apdma_sync = 0, 333ce38815dSXudong Chen }; 334ce38815dSXudong Chen 335ce38815dSXudong Chen static const struct mtk_i2c_compatible mt6589_compat = { 336ce38815dSXudong Chen .quirks = &mt6577_i2c_quirks, 337bc6eaf17SQii Wang .regs = mt_i2c_regs_v1, 338ce38815dSXudong Chen .pmic_i2c = 1, 339ce38815dSXudong Chen .dcm = 0, 340b2ed11e2SEddie Huang .auto_restart = 0, 341173b77e8SLiguo Zhang .aux_len_reg = 0, 342f4f4fed6SLiguo Zhang .support_33bits = 0, 3435a10e7d7SJun Gao .timing_adjust = 0, 344a15c91baSQii Wang .dma_sync = 0, 34525708278SQii Wang .ltiming_adjust = 0, 3468426fe70SQii Wang .apdma_sync = 0, 347b2ed11e2SEddie Huang }; 348b2ed11e2SEddie Huang 3491304fe09SJun Gao static const struct mtk_i2c_compatible mt7622_compat = { 3501304fe09SJun Gao .quirks = &mt7622_i2c_quirks, 351bc6eaf17SQii Wang .regs = mt_i2c_regs_v1, 3521304fe09SJun Gao .pmic_i2c = 0, 3531304fe09SJun Gao .dcm = 1, 3541304fe09SJun Gao .auto_restart = 1, 3551304fe09SJun Gao .aux_len_reg = 1, 3561304fe09SJun Gao .support_33bits = 0, 3575a10e7d7SJun Gao .timing_adjust = 0, 358a15c91baSQii Wang .dma_sync = 0, 35925708278SQii Wang .ltiming_adjust = 0, 3608426fe70SQii Wang .apdma_sync = 0, 3611304fe09SJun Gao }; 3621304fe09SJun Gao 363b2ed11e2SEddie Huang static const struct mtk_i2c_compatible mt8173_compat = { 364bc6eaf17SQii Wang .regs = mt_i2c_regs_v1, 365b2ed11e2SEddie Huang .pmic_i2c = 0, 366b2ed11e2SEddie Huang .dcm = 1, 367b2ed11e2SEddie Huang .auto_restart = 1, 368173b77e8SLiguo Zhang .aux_len_reg = 1, 369f4f4fed6SLiguo Zhang .support_33bits = 1, 3705a10e7d7SJun Gao .timing_adjust = 0, 371a15c91baSQii Wang .dma_sync = 0, 37225708278SQii Wang .ltiming_adjust = 0, 3738426fe70SQii Wang .apdma_sync = 0, 37425708278SQii Wang }; 37525708278SQii Wang 37625708278SQii Wang static const struct mtk_i2c_compatible mt8183_compat = { 377abf4923eSHsin-Yi Wang .quirks = &mt8183_i2c_quirks, 37825708278SQii Wang .regs = mt_i2c_regs_v2, 37925708278SQii Wang .pmic_i2c = 0, 38025708278SQii Wang .dcm = 0, 38125708278SQii Wang .auto_restart = 1, 38225708278SQii Wang .aux_len_reg = 1, 38325708278SQii Wang .support_33bits = 1, 38425708278SQii Wang .timing_adjust = 1, 38525708278SQii Wang .dma_sync = 1, 38625708278SQii Wang .ltiming_adjust = 1, 3878426fe70SQii Wang .apdma_sync = 0, 388ce38815dSXudong Chen }; 389ce38815dSXudong Chen 390ce38815dSXudong Chen static const struct of_device_id mtk_i2c_of_match[] = { 3915a10e7d7SJun Gao { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 392ce38815dSXudong Chen { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 393ce38815dSXudong Chen { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 3941304fe09SJun Gao { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 395b2ed11e2SEddie Huang { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 39625708278SQii Wang { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 397ce38815dSXudong Chen {} 398ce38815dSXudong Chen }; 399ce38815dSXudong Chen MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 400ce38815dSXudong Chen 401bc6eaf17SQii Wang static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 402bc6eaf17SQii Wang { 403bc6eaf17SQii Wang return readw(i2c->base + i2c->dev_comp->regs[reg]); 404bc6eaf17SQii Wang } 405bc6eaf17SQii Wang 406bc6eaf17SQii Wang static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 407bc6eaf17SQii Wang enum I2C_REGS_OFFSET reg) 408bc6eaf17SQii Wang { 409bc6eaf17SQii Wang writew(val, i2c->base + i2c->dev_comp->regs[reg]); 410bc6eaf17SQii Wang } 411bc6eaf17SQii Wang 412ce38815dSXudong Chen static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 413ce38815dSXudong Chen { 414ce38815dSXudong Chen int ret; 415ce38815dSXudong Chen 416ce38815dSXudong Chen ret = clk_prepare_enable(i2c->clk_dma); 417ce38815dSXudong Chen if (ret) 418ce38815dSXudong Chen return ret; 419ce38815dSXudong Chen 420ce38815dSXudong Chen ret = clk_prepare_enable(i2c->clk_main); 421ce38815dSXudong Chen if (ret) 422ce38815dSXudong Chen goto err_main; 423ce38815dSXudong Chen 424ce38815dSXudong Chen if (i2c->have_pmic) { 425ce38815dSXudong Chen ret = clk_prepare_enable(i2c->clk_pmic); 426ce38815dSXudong Chen if (ret) 427ce38815dSXudong Chen goto err_pmic; 428ce38815dSXudong Chen } 429cad6dc5dSQii Wang 430cad6dc5dSQii Wang if (i2c->clk_arb) { 431cad6dc5dSQii Wang ret = clk_prepare_enable(i2c->clk_arb); 432cad6dc5dSQii Wang if (ret) 433cad6dc5dSQii Wang goto err_arb; 434cad6dc5dSQii Wang } 435cad6dc5dSQii Wang 436ce38815dSXudong Chen return 0; 437ce38815dSXudong Chen 438cad6dc5dSQii Wang err_arb: 439cad6dc5dSQii Wang if (i2c->have_pmic) 440cad6dc5dSQii Wang clk_disable_unprepare(i2c->clk_pmic); 441ce38815dSXudong Chen err_pmic: 442ce38815dSXudong Chen clk_disable_unprepare(i2c->clk_main); 443ce38815dSXudong Chen err_main: 444ce38815dSXudong Chen clk_disable_unprepare(i2c->clk_dma); 445ce38815dSXudong Chen 446ce38815dSXudong Chen return ret; 447ce38815dSXudong Chen } 448ce38815dSXudong Chen 449ce38815dSXudong Chen static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 450ce38815dSXudong Chen { 451cad6dc5dSQii Wang if (i2c->clk_arb) 452cad6dc5dSQii Wang clk_disable_unprepare(i2c->clk_arb); 453cad6dc5dSQii Wang 454ce38815dSXudong Chen if (i2c->have_pmic) 455ce38815dSXudong Chen clk_disable_unprepare(i2c->clk_pmic); 456ce38815dSXudong Chen 457ce38815dSXudong Chen clk_disable_unprepare(i2c->clk_main); 458ce38815dSXudong Chen clk_disable_unprepare(i2c->clk_dma); 459ce38815dSXudong Chen } 460ce38815dSXudong Chen 461ce38815dSXudong Chen static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 462ce38815dSXudong Chen { 463ce38815dSXudong Chen u16 control_reg; 464ce38815dSXudong Chen 465bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 466ce38815dSXudong Chen 467ce38815dSXudong Chen /* Set ioconfig */ 468ce38815dSXudong Chen if (i2c->use_push_pull) 469bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 470ce38815dSXudong Chen else 471bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 472ce38815dSXudong Chen 473ce38815dSXudong Chen if (i2c->dev_comp->dcm) 474bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 475ce38815dSXudong Chen 476bc6eaf17SQii Wang mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 477bc6eaf17SQii Wang mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 47825708278SQii Wang if (i2c->dev_comp->ltiming_adjust) 47925708278SQii Wang mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 480ce38815dSXudong Chen 481be5ce0e9SQii Wang if (i2c->dev_comp->timing_adjust) { 482be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF); 483be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 484be5ce0e9SQii Wang OFFSET_CLOCK_DIV); 485be5ce0e9SQii Wang mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 486be5ce0e9SQii Wang OFFSET_SCL_MIS_COMP_POINT); 487be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 488be5ce0e9SQii Wang OFFSET_SDA_TIMING); 489be5ce0e9SQii Wang 490be5ce0e9SQii Wang if (i2c->dev_comp->ltiming_adjust) { 491be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 492be5ce0e9SQii Wang OFFSET_TIMING); 493be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 494be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 495be5ce0e9SQii Wang OFFSET_LTIMING); 496be5ce0e9SQii Wang } else { 497be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 498be5ce0e9SQii Wang OFFSET_SCL_HIGH_LOW_RATIO); 499be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 500be5ce0e9SQii Wang OFFSET_HS_SCL_HIGH_LOW_RATIO); 501be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 502be5ce0e9SQii Wang OFFSET_STA_STO_AC_TIMING); 503be5ce0e9SQii Wang mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 504be5ce0e9SQii Wang OFFSET_HS_STA_STO_AC_TIMING); 505be5ce0e9SQii Wang } 506be5ce0e9SQii Wang } 507be5ce0e9SQii Wang 508ce38815dSXudong Chen /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 509ce38815dSXudong Chen if (i2c->have_pmic) 510bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 511ce38815dSXudong Chen 512ce38815dSXudong Chen control_reg = I2C_CONTROL_ACKERR_DET_EN | 513ce38815dSXudong Chen I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 514a15c91baSQii Wang if (i2c->dev_comp->dma_sync) 515a15c91baSQii Wang control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 516a15c91baSQii Wang 517bc6eaf17SQii Wang mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 518bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 519ea89ef1fSEddie Huang 520ea89ef1fSEddie Huang writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 521ea89ef1fSEddie Huang udelay(50); 522ea89ef1fSEddie Huang writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 523ce38815dSXudong Chen } 524ce38815dSXudong Chen 525be5ce0e9SQii Wang static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 526be5ce0e9SQii Wang { 527be5ce0e9SQii Wang if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 528be5ce0e9SQii Wang return &standard_mode_spec; 529be5ce0e9SQii Wang else if (speed <= I2C_MAX_FAST_MODE_FREQ) 530be5ce0e9SQii Wang return &fast_mode_spec; 531be5ce0e9SQii Wang else 532be5ce0e9SQii Wang return &fast_mode_plus_spec; 533be5ce0e9SQii Wang } 534be5ce0e9SQii Wang 535be5ce0e9SQii Wang static int mtk_i2c_max_step_cnt(unsigned int target_speed) 536be5ce0e9SQii Wang { 537be5ce0e9SQii Wang if (target_speed > I2C_MAX_FAST_MODE_FREQ) 538be5ce0e9SQii Wang return MAX_HS_STEP_CNT_DIV; 539be5ce0e9SQii Wang else 540be5ce0e9SQii Wang return MAX_STEP_CNT_DIV; 541be5ce0e9SQii Wang } 542be5ce0e9SQii Wang 543be5ce0e9SQii Wang /* 544be5ce0e9SQii Wang * Check and Calculate i2c ac-timing 545be5ce0e9SQii Wang * 546be5ce0e9SQii Wang * Hardware design: 547be5ce0e9SQii Wang * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 548be5ce0e9SQii Wang * xxx_cnt_div = spec->min_xxx_ns / sample_ns 549be5ce0e9SQii Wang * 550be5ce0e9SQii Wang * Sample_ns is rounded down for xxx_cnt_div would be greater 551be5ce0e9SQii Wang * than the smallest spec. 552be5ce0e9SQii Wang * The sda_timing is chosen as the middle value between 553be5ce0e9SQii Wang * the largest and smallest. 554be5ce0e9SQii Wang */ 555be5ce0e9SQii Wang static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 556be5ce0e9SQii Wang unsigned int clk_src, 557be5ce0e9SQii Wang unsigned int check_speed, 558be5ce0e9SQii Wang unsigned int step_cnt, 559be5ce0e9SQii Wang unsigned int sample_cnt) 560be5ce0e9SQii Wang { 561be5ce0e9SQii Wang const struct i2c_spec_values *spec; 562be5ce0e9SQii Wang unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 563be5ce0e9SQii Wang unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 564be5ce0e9SQii Wang unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 565be5ce0e9SQii Wang clk_src); 566be5ce0e9SQii Wang 567be5ce0e9SQii Wang if (!i2c->dev_comp->timing_adjust) 568be5ce0e9SQii Wang return 0; 569be5ce0e9SQii Wang 570be5ce0e9SQii Wang if (i2c->dev_comp->ltiming_adjust) 571be5ce0e9SQii Wang max_sta_cnt = 0x100; 572be5ce0e9SQii Wang 573be5ce0e9SQii Wang spec = mtk_i2c_get_spec(check_speed); 574be5ce0e9SQii Wang 575be5ce0e9SQii Wang if (i2c->dev_comp->ltiming_adjust) 576be5ce0e9SQii Wang clk_ns = 1000000000 / clk_src; 577be5ce0e9SQii Wang else 578be5ce0e9SQii Wang clk_ns = sample_ns / 2; 579be5ce0e9SQii Wang 580be5ce0e9SQii Wang su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); 581be5ce0e9SQii Wang if (su_sta_cnt > max_sta_cnt) 582be5ce0e9SQii Wang return -1; 583be5ce0e9SQii Wang 584be5ce0e9SQii Wang low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 585be5ce0e9SQii Wang max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 586be5ce0e9SQii Wang if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 587be5ce0e9SQii Wang if (low_cnt > step_cnt) { 588be5ce0e9SQii Wang high_cnt = 2 * step_cnt - low_cnt; 589be5ce0e9SQii Wang } else { 590be5ce0e9SQii Wang high_cnt = step_cnt; 591be5ce0e9SQii Wang low_cnt = step_cnt; 592be5ce0e9SQii Wang } 593be5ce0e9SQii Wang } else { 594be5ce0e9SQii Wang return -2; 595be5ce0e9SQii Wang } 596be5ce0e9SQii Wang 597be5ce0e9SQii Wang sda_max = spec->max_hd_dat_ns / sample_ns; 598be5ce0e9SQii Wang if (sda_max > low_cnt) 599be5ce0e9SQii Wang sda_max = 0; 600be5ce0e9SQii Wang 601be5ce0e9SQii Wang sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 602be5ce0e9SQii Wang if (sda_min < low_cnt) 603be5ce0e9SQii Wang sda_min = 0; 604be5ce0e9SQii Wang 605be5ce0e9SQii Wang if (sda_min > sda_max) 606be5ce0e9SQii Wang return -3; 607be5ce0e9SQii Wang 608be5ce0e9SQii Wang if (check_speed > I2C_MAX_FAST_MODE_FREQ) { 609be5ce0e9SQii Wang if (i2c->dev_comp->ltiming_adjust) { 610be5ce0e9SQii Wang i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 611be5ce0e9SQii Wang (sample_cnt << 12) | (high_cnt << 8); 612be5ce0e9SQii Wang i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 613be5ce0e9SQii Wang i2c->ac_timing.ltiming |= (sample_cnt << 12) | 614be5ce0e9SQii Wang (low_cnt << 9); 615be5ce0e9SQii Wang i2c->ac_timing.ext &= ~GENMASK(7, 1); 616be5ce0e9SQii Wang i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 617be5ce0e9SQii Wang } else { 618be5ce0e9SQii Wang i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 619be5ce0e9SQii Wang (high_cnt << 6) | low_cnt; 620be5ce0e9SQii Wang i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 621be5ce0e9SQii Wang su_sta_cnt; 622be5ce0e9SQii Wang } 623be5ce0e9SQii Wang i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 624be5ce0e9SQii Wang i2c->ac_timing.sda_timing |= (1 << 12) | 625be5ce0e9SQii Wang ((sda_max + sda_min) / 2) << 6; 626be5ce0e9SQii Wang } else { 627be5ce0e9SQii Wang if (i2c->dev_comp->ltiming_adjust) { 628be5ce0e9SQii Wang i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 629be5ce0e9SQii Wang i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 630be5ce0e9SQii Wang i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 631be5ce0e9SQii Wang } else { 632be5ce0e9SQii Wang i2c->ac_timing.scl_hl_ratio = (1 << 12) | 633be5ce0e9SQii Wang (high_cnt << 6) | low_cnt; 634be5ce0e9SQii Wang i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 635be5ce0e9SQii Wang su_sta_cnt; 636be5ce0e9SQii Wang } 637be5ce0e9SQii Wang 638be5ce0e9SQii Wang i2c->ac_timing.sda_timing = (1 << 12) | 639be5ce0e9SQii Wang (sda_max + sda_min) / 2; 640be5ce0e9SQii Wang } 641be5ce0e9SQii Wang 642be5ce0e9SQii Wang return 0; 643be5ce0e9SQii Wang } 644be5ce0e9SQii Wang 645ce38815dSXudong Chen /* 646ce38815dSXudong Chen * Calculate i2c port speed 647ce38815dSXudong Chen * 648ce38815dSXudong Chen * Hardware design: 649ce38815dSXudong Chen * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 650ce38815dSXudong Chen * clock_div: fixed in hardware, but may be various in different SoCs 651ce38815dSXudong Chen * 652ce38815dSXudong Chen * The calculation want to pick the highest bus frequency that is still 653ce38815dSXudong Chen * less than or equal to i2c->speed_hz. The calculation try to get 654ce38815dSXudong Chen * sample_cnt and step_cn 655ce38815dSXudong Chen */ 656f2326401SJun Gao static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 657f2326401SJun Gao unsigned int target_speed, 658f2326401SJun Gao unsigned int *timing_step_cnt, 659f2326401SJun Gao unsigned int *timing_sample_cnt) 660ce38815dSXudong Chen { 661ce38815dSXudong Chen unsigned int step_cnt; 662ce38815dSXudong Chen unsigned int sample_cnt; 663ce38815dSXudong Chen unsigned int max_step_cnt; 664ce38815dSXudong Chen unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 665ce38815dSXudong Chen unsigned int base_step_cnt; 666ce38815dSXudong Chen unsigned int opt_div; 667ce38815dSXudong Chen unsigned int best_mul; 668ce38815dSXudong Chen unsigned int cnt_mul; 669be5ce0e9SQii Wang int ret = -EINVAL; 670ce38815dSXudong Chen 67190224e64SAndy Shevchenko if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 67290224e64SAndy Shevchenko target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ; 673ce38815dSXudong Chen 674be5ce0e9SQii Wang max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 675ce38815dSXudong Chen base_step_cnt = max_step_cnt; 676ce38815dSXudong Chen /* Find the best combination */ 677ce38815dSXudong Chen opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 678ce38815dSXudong Chen best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 679ce38815dSXudong Chen 680ce38815dSXudong Chen /* Search for the best pair (sample_cnt, step_cnt) with 681ce38815dSXudong Chen * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 682ce38815dSXudong Chen * 0 < step_cnt < max_step_cnt 683ce38815dSXudong Chen * sample_cnt * step_cnt >= opt_div 684ce38815dSXudong Chen * optimizing for sample_cnt * step_cnt being minimal 685ce38815dSXudong Chen */ 686ce38815dSXudong Chen for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 687ce38815dSXudong Chen step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 688ce38815dSXudong Chen cnt_mul = step_cnt * sample_cnt; 689ce38815dSXudong Chen if (step_cnt > max_step_cnt) 690ce38815dSXudong Chen continue; 691ce38815dSXudong Chen 692ce38815dSXudong Chen if (cnt_mul < best_mul) { 693be5ce0e9SQii Wang ret = mtk_i2c_check_ac_timing(i2c, clk_src, 694be5ce0e9SQii Wang target_speed, step_cnt - 1, sample_cnt - 1); 695be5ce0e9SQii Wang if (ret) 696be5ce0e9SQii Wang continue; 697be5ce0e9SQii Wang 698ce38815dSXudong Chen best_mul = cnt_mul; 699ce38815dSXudong Chen base_sample_cnt = sample_cnt; 700ce38815dSXudong Chen base_step_cnt = step_cnt; 701ce38815dSXudong Chen if (best_mul == opt_div) 702ce38815dSXudong Chen break; 703ce38815dSXudong Chen } 704ce38815dSXudong Chen } 705ce38815dSXudong Chen 706be5ce0e9SQii Wang if (ret) 707be5ce0e9SQii Wang return -EINVAL; 708be5ce0e9SQii Wang 709ce38815dSXudong Chen sample_cnt = base_sample_cnt; 710ce38815dSXudong Chen step_cnt = base_step_cnt; 711ce38815dSXudong Chen 712ce38815dSXudong Chen if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 713ce38815dSXudong Chen /* In this case, hardware can't support such 714ce38815dSXudong Chen * low i2c_bus_freq 715ce38815dSXudong Chen */ 716ce38815dSXudong Chen dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 717ce38815dSXudong Chen return -EINVAL; 718ce38815dSXudong Chen } 719ce38815dSXudong Chen 720f2326401SJun Gao *timing_step_cnt = step_cnt - 1; 721f2326401SJun Gao *timing_sample_cnt = sample_cnt - 1; 722f2326401SJun Gao 723f2326401SJun Gao return 0; 724f2326401SJun Gao } 725f2326401SJun Gao 726f2326401SJun Gao static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 727f2326401SJun Gao { 728f2326401SJun Gao unsigned int clk_src; 729f2326401SJun Gao unsigned int step_cnt; 730f2326401SJun Gao unsigned int sample_cnt; 73125708278SQii Wang unsigned int l_step_cnt; 73225708278SQii Wang unsigned int l_sample_cnt; 733f2326401SJun Gao unsigned int target_speed; 734be5ce0e9SQii Wang unsigned int clk_div; 735be5ce0e9SQii Wang unsigned int max_clk_div; 736f2326401SJun Gao int ret; 737f2326401SJun Gao 738f2326401SJun Gao target_speed = i2c->speed_hz; 739be5ce0e9SQii Wang parent_clk /= i2c->clk_src_div; 740be5ce0e9SQii Wang 741be5ce0e9SQii Wang if (i2c->dev_comp->timing_adjust) 742be5ce0e9SQii Wang max_clk_div = MAX_CLOCK_DIV; 743be5ce0e9SQii Wang else 744be5ce0e9SQii Wang max_clk_div = 1; 745be5ce0e9SQii Wang 746be5ce0e9SQii Wang for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 747be5ce0e9SQii Wang clk_src = parent_clk / clk_div; 748ce38815dSXudong Chen 74990224e64SAndy Shevchenko if (target_speed > I2C_MAX_FAST_MODE_FREQ) { 750f2326401SJun Gao /* Set master code speed register */ 751be5ce0e9SQii Wang ret = mtk_i2c_calculate_speed(i2c, clk_src, 752be5ce0e9SQii Wang I2C_MAX_FAST_MODE_FREQ, 753be5ce0e9SQii Wang &l_step_cnt, 754be5ce0e9SQii Wang &l_sample_cnt); 755f2326401SJun Gao if (ret < 0) 756be5ce0e9SQii Wang continue; 757f2326401SJun Gao 75825708278SQii Wang i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 759f2326401SJun Gao 760ce38815dSXudong Chen /* Set the high speed mode register */ 761be5ce0e9SQii Wang ret = mtk_i2c_calculate_speed(i2c, clk_src, 762be5ce0e9SQii Wang target_speed, &step_cnt, 763be5ce0e9SQii Wang &sample_cnt); 764f2326401SJun Gao if (ret < 0) 765be5ce0e9SQii Wang continue; 766f2326401SJun Gao 767ce38815dSXudong Chen i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 768ce38815dSXudong Chen (sample_cnt << 12) | (step_cnt << 8); 76925708278SQii Wang 77025708278SQii Wang if (i2c->dev_comp->ltiming_adjust) 771be5ce0e9SQii Wang i2c->ltiming_reg = 772be5ce0e9SQii Wang (l_sample_cnt << 6) | l_step_cnt | 77325708278SQii Wang (sample_cnt << 12) | (step_cnt << 9); 774ce38815dSXudong Chen } else { 775be5ce0e9SQii Wang ret = mtk_i2c_calculate_speed(i2c, clk_src, 776be5ce0e9SQii Wang target_speed, &l_step_cnt, 777be5ce0e9SQii Wang &l_sample_cnt); 778f2326401SJun Gao if (ret < 0) 779be5ce0e9SQii Wang continue; 780f2326401SJun Gao 781be5ce0e9SQii Wang i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 782f2326401SJun Gao 783ce38815dSXudong Chen /* Disable the high speed transaction */ 784ce38815dSXudong Chen i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 78525708278SQii Wang 78625708278SQii Wang if (i2c->dev_comp->ltiming_adjust) 787be5ce0e9SQii Wang i2c->ltiming_reg = 788be5ce0e9SQii Wang (l_sample_cnt << 6) | l_step_cnt; 789ce38815dSXudong Chen } 790ce38815dSXudong Chen 791be5ce0e9SQii Wang break; 792be5ce0e9SQii Wang } 793be5ce0e9SQii Wang 794be5ce0e9SQii Wang i2c->ac_timing.inter_clk_div = clk_div - 1; 795be5ce0e9SQii Wang 796ce38815dSXudong Chen return 0; 797ce38815dSXudong Chen } 798ce38815dSXudong Chen 799f4f4fed6SLiguo Zhang static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr) 800f4f4fed6SLiguo Zhang { 801f4f4fed6SLiguo Zhang return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG; 802f4f4fed6SLiguo Zhang } 803f4f4fed6SLiguo Zhang 804b2ed11e2SEddie Huang static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 805b2ed11e2SEddie Huang int num, int left_num) 806ce38815dSXudong Chen { 807ce38815dSXudong Chen u16 addr_reg; 808b2ed11e2SEddie Huang u16 start_reg; 809ce38815dSXudong Chen u16 control_reg; 810b2ed11e2SEddie Huang u16 restart_flag = 0; 8118426fe70SQii Wang u16 dma_sync = 0; 812f4f4fed6SLiguo Zhang u32 reg_4g_mode; 813fc66b39fSJun Gao u8 *dma_rd_buf = NULL; 814fc66b39fSJun Gao u8 *dma_wr_buf = NULL; 815ce38815dSXudong Chen dma_addr_t rpaddr = 0; 816ce38815dSXudong Chen dma_addr_t wpaddr = 0; 817ce38815dSXudong Chen int ret; 818ce38815dSXudong Chen 819ce38815dSXudong Chen i2c->irq_stat = 0; 820ce38815dSXudong Chen 821173b77e8SLiguo Zhang if (i2c->auto_restart) 822b2ed11e2SEddie Huang restart_flag = I2C_RS_TRANSFER; 823b2ed11e2SEddie Huang 824ce38815dSXudong Chen reinit_completion(&i2c->msg_complete); 825ce38815dSXudong Chen 826bc6eaf17SQii Wang control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 827ce38815dSXudong Chen ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 82890224e64SAndy Shevchenko if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 829ce38815dSXudong Chen control_reg |= I2C_CONTROL_RS; 830ce38815dSXudong Chen 831ce38815dSXudong Chen if (i2c->op == I2C_MASTER_WRRD) 832ce38815dSXudong Chen control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 833ce38815dSXudong Chen 834bc6eaf17SQii Wang mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 835ce38815dSXudong Chen 8360d47ce21SWolfram Sang addr_reg = i2c_8bit_addr_from_msg(msgs); 837bc6eaf17SQii Wang mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 838ce38815dSXudong Chen 839ce38815dSXudong Chen /* Clear interrupt status */ 840bc6eaf17SQii Wang mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 841cad6dc5dSQii Wang I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 842bc6eaf17SQii Wang 843bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 844ce38815dSXudong Chen 845ce38815dSXudong Chen /* Enable interrupt */ 846bc6eaf17SQii Wang mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 847cad6dc5dSQii Wang I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 848ce38815dSXudong Chen 849ce38815dSXudong Chen /* Set transfer and transaction len */ 850ce38815dSXudong Chen if (i2c->op == I2C_MASTER_WRRD) { 851173b77e8SLiguo Zhang if (i2c->dev_comp->aux_len_reg) { 852bc6eaf17SQii Wang mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 853bc6eaf17SQii Wang mtk_i2c_writew(i2c, (msgs + 1)->len, 854173b77e8SLiguo Zhang OFFSET_TRANSFER_LEN_AUX); 855173b77e8SLiguo Zhang } else { 856bc6eaf17SQii Wang mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 857bc6eaf17SQii Wang OFFSET_TRANSFER_LEN); 858173b77e8SLiguo Zhang } 859bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 860ce38815dSXudong Chen } else { 861bc6eaf17SQii Wang mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 862bc6eaf17SQii Wang mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 863ce38815dSXudong Chen } 864ce38815dSXudong Chen 8658426fe70SQii Wang if (i2c->dev_comp->apdma_sync) { 8668426fe70SQii Wang dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 8678426fe70SQii Wang if (i2c->op == I2C_MASTER_WRRD) 8688426fe70SQii Wang dma_sync |= I2C_DMA_DIR_CHANGE; 8698426fe70SQii Wang } 8708426fe70SQii Wang 871ce38815dSXudong Chen /* Prepare buffer data to start transfer */ 872ce38815dSXudong Chen if (i2c->op == I2C_MASTER_RD) { 873ce38815dSXudong Chen writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 8748426fe70SQii Wang writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 875fc66b39fSJun Gao 876bc1a7f75SHsin-Yi Wang dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 877fc66b39fSJun Gao if (!dma_rd_buf) 878ce38815dSXudong Chen return -ENOMEM; 879f4f4fed6SLiguo Zhang 880fc66b39fSJun Gao rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 881fc66b39fSJun Gao msgs->len, DMA_FROM_DEVICE); 882fc66b39fSJun Gao if (dma_mapping_error(i2c->dev, rpaddr)) { 883fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 884fc66b39fSJun Gao 885fc66b39fSJun Gao return -ENOMEM; 886fc66b39fSJun Gao } 887fc66b39fSJun Gao 888f4f4fed6SLiguo Zhang if (i2c->dev_comp->support_33bits) { 889f4f4fed6SLiguo Zhang reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 890f4f4fed6SLiguo Zhang writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 891f4f4fed6SLiguo Zhang } 892f4f4fed6SLiguo Zhang 893ce38815dSXudong Chen writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 894ce38815dSXudong Chen writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 895ce38815dSXudong Chen } else if (i2c->op == I2C_MASTER_WR) { 896ce38815dSXudong Chen writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 8978426fe70SQii Wang writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 898fc66b39fSJun Gao 899bc1a7f75SHsin-Yi Wang dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 900fc66b39fSJun Gao if (!dma_wr_buf) 901ce38815dSXudong Chen return -ENOMEM; 902f4f4fed6SLiguo Zhang 903fc66b39fSJun Gao wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 904fc66b39fSJun Gao msgs->len, DMA_TO_DEVICE); 905fc66b39fSJun Gao if (dma_mapping_error(i2c->dev, wpaddr)) { 906fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 907fc66b39fSJun Gao 908fc66b39fSJun Gao return -ENOMEM; 909fc66b39fSJun Gao } 910fc66b39fSJun Gao 911f4f4fed6SLiguo Zhang if (i2c->dev_comp->support_33bits) { 912f4f4fed6SLiguo Zhang reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 913f4f4fed6SLiguo Zhang writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 914f4f4fed6SLiguo Zhang } 915f4f4fed6SLiguo Zhang 916ce38815dSXudong Chen writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 917ce38815dSXudong Chen writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 918ce38815dSXudong Chen } else { 919ce38815dSXudong Chen writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 9208426fe70SQii Wang writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 921fc66b39fSJun Gao 922bc1a7f75SHsin-Yi Wang dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 923fc66b39fSJun Gao if (!dma_wr_buf) 924ce38815dSXudong Chen return -ENOMEM; 925fc66b39fSJun Gao 926fc66b39fSJun Gao wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 927fc66b39fSJun Gao msgs->len, DMA_TO_DEVICE); 928fc66b39fSJun Gao if (dma_mapping_error(i2c->dev, wpaddr)) { 929fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 930fc66b39fSJun Gao 931fc66b39fSJun Gao return -ENOMEM; 932fc66b39fSJun Gao } 933fc66b39fSJun Gao 934bc1a7f75SHsin-Yi Wang dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 935fc66b39fSJun Gao if (!dma_rd_buf) { 936fc66b39fSJun Gao dma_unmap_single(i2c->dev, wpaddr, 937fc66b39fSJun Gao msgs->len, DMA_TO_DEVICE); 938fc66b39fSJun Gao 939fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 940fc66b39fSJun Gao 941fc66b39fSJun Gao return -ENOMEM; 942fc66b39fSJun Gao } 943fc66b39fSJun Gao 944fc66b39fSJun Gao rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 945ce38815dSXudong Chen (msgs + 1)->len, 946ce38815dSXudong Chen DMA_FROM_DEVICE); 947ce38815dSXudong Chen if (dma_mapping_error(i2c->dev, rpaddr)) { 948ce38815dSXudong Chen dma_unmap_single(i2c->dev, wpaddr, 949ce38815dSXudong Chen msgs->len, DMA_TO_DEVICE); 950fc66b39fSJun Gao 951fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 952fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 953fc66b39fSJun Gao 954ce38815dSXudong Chen return -ENOMEM; 955ce38815dSXudong Chen } 956f4f4fed6SLiguo Zhang 957f4f4fed6SLiguo Zhang if (i2c->dev_comp->support_33bits) { 958f4f4fed6SLiguo Zhang reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); 959f4f4fed6SLiguo Zhang writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 960f4f4fed6SLiguo Zhang 961f4f4fed6SLiguo Zhang reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr); 962f4f4fed6SLiguo Zhang writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 963f4f4fed6SLiguo Zhang } 964f4f4fed6SLiguo Zhang 965ce38815dSXudong Chen writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 966ce38815dSXudong Chen writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 967ce38815dSXudong Chen writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 968ce38815dSXudong Chen writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 969ce38815dSXudong Chen } 970ce38815dSXudong Chen 971ce38815dSXudong Chen writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 972b2ed11e2SEddie Huang 973173b77e8SLiguo Zhang if (!i2c->auto_restart) { 974b2ed11e2SEddie Huang start_reg = I2C_TRANSAC_START; 975b2ed11e2SEddie Huang } else { 976b2ed11e2SEddie Huang start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 977b2ed11e2SEddie Huang if (left_num >= 1) 978b2ed11e2SEddie Huang start_reg |= I2C_RS_MUL_CNFG; 979b2ed11e2SEddie Huang } 980bc6eaf17SQii Wang mtk_i2c_writew(i2c, start_reg, OFFSET_START); 981ce38815dSXudong Chen 982ce38815dSXudong Chen ret = wait_for_completion_timeout(&i2c->msg_complete, 983ce38815dSXudong Chen i2c->adap.timeout); 984ce38815dSXudong Chen 985ce38815dSXudong Chen /* Clear interrupt mask */ 986bc6eaf17SQii Wang mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 987cad6dc5dSQii Wang I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 988ce38815dSXudong Chen 989ce38815dSXudong Chen if (i2c->op == I2C_MASTER_WR) { 990ce38815dSXudong Chen dma_unmap_single(i2c->dev, wpaddr, 991ce38815dSXudong Chen msgs->len, DMA_TO_DEVICE); 992fc66b39fSJun Gao 993fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 994ce38815dSXudong Chen } else if (i2c->op == I2C_MASTER_RD) { 995ce38815dSXudong Chen dma_unmap_single(i2c->dev, rpaddr, 996ce38815dSXudong Chen msgs->len, DMA_FROM_DEVICE); 997fc66b39fSJun Gao 998fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 999ce38815dSXudong Chen } else { 1000ce38815dSXudong Chen dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1001ce38815dSXudong Chen DMA_TO_DEVICE); 1002ce38815dSXudong Chen dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1003ce38815dSXudong Chen DMA_FROM_DEVICE); 1004fc66b39fSJun Gao 1005fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1006fc66b39fSJun Gao i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1007ce38815dSXudong Chen } 1008ce38815dSXudong Chen 1009ce38815dSXudong Chen if (ret == 0) { 1010ce38815dSXudong Chen dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1011ce38815dSXudong Chen mtk_i2c_init_hw(i2c); 1012ce38815dSXudong Chen return -ETIMEDOUT; 1013ce38815dSXudong Chen } 1014ce38815dSXudong Chen 1015ce38815dSXudong Chen if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1016ce38815dSXudong Chen dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1017ce38815dSXudong Chen mtk_i2c_init_hw(i2c); 1018ce38815dSXudong Chen return -ENXIO; 1019ce38815dSXudong Chen } 1020ce38815dSXudong Chen 1021ce38815dSXudong Chen return 0; 1022ce38815dSXudong Chen } 1023ce38815dSXudong Chen 1024ce38815dSXudong Chen static int mtk_i2c_transfer(struct i2c_adapter *adap, 1025ce38815dSXudong Chen struct i2c_msg msgs[], int num) 1026ce38815dSXudong Chen { 1027ce38815dSXudong Chen int ret; 1028ce38815dSXudong Chen int left_num = num; 1029ce38815dSXudong Chen struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1030ce38815dSXudong Chen 1031ce38815dSXudong Chen ret = mtk_i2c_clock_enable(i2c); 1032ce38815dSXudong Chen if (ret) 1033ce38815dSXudong Chen return ret; 1034ce38815dSXudong Chen 1035173b77e8SLiguo Zhang i2c->auto_restart = i2c->dev_comp->auto_restart; 1036173b77e8SLiguo Zhang 1037173b77e8SLiguo Zhang /* checking if we can skip restart and optimize using WRRD mode */ 1038173b77e8SLiguo Zhang if (i2c->auto_restart && num == 2) { 1039173b77e8SLiguo Zhang if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1040173b77e8SLiguo Zhang msgs[0].addr == msgs[1].addr) { 1041173b77e8SLiguo Zhang i2c->auto_restart = 0; 1042173b77e8SLiguo Zhang } 1043173b77e8SLiguo Zhang } 1044173b77e8SLiguo Zhang 104590224e64SAndy Shevchenko if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 10468378d01fSLiguo Zhang /* ignore the first restart irq after the master code, 10478378d01fSLiguo Zhang * otherwise the first transfer will be discarded. 10488378d01fSLiguo Zhang */ 10498378d01fSLiguo Zhang i2c->ignore_restart_irq = true; 10508378d01fSLiguo Zhang else 10518378d01fSLiguo Zhang i2c->ignore_restart_irq = false; 10528378d01fSLiguo Zhang 1053b2ed11e2SEddie Huang while (left_num--) { 1054ce38815dSXudong Chen if (!msgs->buf) { 1055ce38815dSXudong Chen dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1056ce38815dSXudong Chen ret = -EINVAL; 1057ce38815dSXudong Chen goto err_exit; 1058ce38815dSXudong Chen } 1059ce38815dSXudong Chen 1060ce38815dSXudong Chen if (msgs->flags & I2C_M_RD) 1061ce38815dSXudong Chen i2c->op = I2C_MASTER_RD; 1062ce38815dSXudong Chen else 1063ce38815dSXudong Chen i2c->op = I2C_MASTER_WR; 1064ce38815dSXudong Chen 1065173b77e8SLiguo Zhang if (!i2c->auto_restart) { 1066ce38815dSXudong Chen if (num > 1) { 1067ce38815dSXudong Chen /* combined two messages into one transaction */ 1068ce38815dSXudong Chen i2c->op = I2C_MASTER_WRRD; 1069ce38815dSXudong Chen left_num--; 1070ce38815dSXudong Chen } 1071b2ed11e2SEddie Huang } 1072ce38815dSXudong Chen 1073ce38815dSXudong Chen /* always use DMA mode. */ 1074b2ed11e2SEddie Huang ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1075ce38815dSXudong Chen if (ret < 0) 1076ce38815dSXudong Chen goto err_exit; 1077ce38815dSXudong Chen 1078b2ed11e2SEddie Huang msgs++; 1079b2ed11e2SEddie Huang } 1080ce38815dSXudong Chen /* the return value is number of executed messages */ 1081ce38815dSXudong Chen ret = num; 1082ce38815dSXudong Chen 1083ce38815dSXudong Chen err_exit: 1084ce38815dSXudong Chen mtk_i2c_clock_disable(i2c); 1085ce38815dSXudong Chen return ret; 1086ce38815dSXudong Chen } 1087ce38815dSXudong Chen 1088ce38815dSXudong Chen static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1089ce38815dSXudong Chen { 1090ce38815dSXudong Chen struct mtk_i2c *i2c = dev_id; 1091b2ed11e2SEddie Huang u16 restart_flag = 0; 109228c0a843SEddie Huang u16 intr_stat; 1093b2ed11e2SEddie Huang 1094173b77e8SLiguo Zhang if (i2c->auto_restart) 1095b2ed11e2SEddie Huang restart_flag = I2C_RS_TRANSFER; 1096ce38815dSXudong Chen 1097bc6eaf17SQii Wang intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1098bc6eaf17SQii Wang mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1099ce38815dSXudong Chen 110028c0a843SEddie Huang /* 110128c0a843SEddie Huang * when occurs ack error, i2c controller generate two interrupts 110228c0a843SEddie Huang * first is the ack error interrupt, then the complete interrupt 110328c0a843SEddie Huang * i2c->irq_stat need keep the two interrupt value. 110428c0a843SEddie Huang */ 110528c0a843SEddie Huang i2c->irq_stat |= intr_stat; 11068378d01fSLiguo Zhang 11078378d01fSLiguo Zhang if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 11088378d01fSLiguo Zhang i2c->ignore_restart_irq = false; 11098378d01fSLiguo Zhang i2c->irq_stat = 0; 1110bc6eaf17SQii Wang mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1111bc6eaf17SQii Wang I2C_TRANSAC_START, OFFSET_START); 11128378d01fSLiguo Zhang } else { 111328c0a843SEddie Huang if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1114ce38815dSXudong Chen complete(&i2c->msg_complete); 11158378d01fSLiguo Zhang } 1116ce38815dSXudong Chen 1117ce38815dSXudong Chen return IRQ_HANDLED; 1118ce38815dSXudong Chen } 1119ce38815dSXudong Chen 1120ce38815dSXudong Chen static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1121ce38815dSXudong Chen { 112262931ac2SFabien Parent if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1123abf4923eSHsin-Yi Wang return I2C_FUNC_I2C | 1124abf4923eSHsin-Yi Wang (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1125abf4923eSHsin-Yi Wang else 1126ce38815dSXudong Chen return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1127ce38815dSXudong Chen } 1128ce38815dSXudong Chen 1129ce38815dSXudong Chen static const struct i2c_algorithm mtk_i2c_algorithm = { 1130ce38815dSXudong Chen .master_xfer = mtk_i2c_transfer, 1131ce38815dSXudong Chen .functionality = mtk_i2c_functionality, 1132ce38815dSXudong Chen }; 1133ce38815dSXudong Chen 1134f2326401SJun Gao static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1135ce38815dSXudong Chen { 1136ce38815dSXudong Chen int ret; 1137ce38815dSXudong Chen 1138ce38815dSXudong Chen ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1139ce38815dSXudong Chen if (ret < 0) 114090224e64SAndy Shevchenko i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1141ce38815dSXudong Chen 1142f2326401SJun Gao ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1143ce38815dSXudong Chen if (ret < 0) 1144ce38815dSXudong Chen return ret; 1145ce38815dSXudong Chen 1146f2326401SJun Gao if (i2c->clk_src_div == 0) 1147ce38815dSXudong Chen return -EINVAL; 1148ce38815dSXudong Chen 1149ce38815dSXudong Chen i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1150ce38815dSXudong Chen i2c->use_push_pull = 1151ce38815dSXudong Chen of_property_read_bool(np, "mediatek,use-push-pull"); 1152ce38815dSXudong Chen 1153ce38815dSXudong Chen return 0; 1154ce38815dSXudong Chen } 1155ce38815dSXudong Chen 1156ce38815dSXudong Chen static int mtk_i2c_probe(struct platform_device *pdev) 1157ce38815dSXudong Chen { 1158ce38815dSXudong Chen int ret = 0; 1159ce38815dSXudong Chen struct mtk_i2c *i2c; 1160ce38815dSXudong Chen struct clk *clk; 1161ce38815dSXudong Chen struct resource *res; 1162ce38815dSXudong Chen int irq; 1163ce38815dSXudong Chen 1164ce38815dSXudong Chen i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1165ce38815dSXudong Chen if (!i2c) 1166ce38815dSXudong Chen return -ENOMEM; 1167ce38815dSXudong Chen 1168ce38815dSXudong Chen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1169ce38815dSXudong Chen i2c->base = devm_ioremap_resource(&pdev->dev, res); 1170ce38815dSXudong Chen if (IS_ERR(i2c->base)) 1171ce38815dSXudong Chen return PTR_ERR(i2c->base); 1172ce38815dSXudong Chen 1173ce38815dSXudong Chen res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1174ce38815dSXudong Chen i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1175ce38815dSXudong Chen if (IS_ERR(i2c->pdmabase)) 1176ce38815dSXudong Chen return PTR_ERR(i2c->pdmabase); 1177ce38815dSXudong Chen 1178ce38815dSXudong Chen irq = platform_get_irq(pdev, 0); 1179ce38815dSXudong Chen if (irq <= 0) 1180ce38815dSXudong Chen return irq; 1181ce38815dSXudong Chen 1182ce38815dSXudong Chen init_completion(&i2c->msg_complete); 1183ce38815dSXudong Chen 11846e29577fSRyder Lee i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1185ce38815dSXudong Chen i2c->adap.dev.of_node = pdev->dev.of_node; 1186ce38815dSXudong Chen i2c->dev = &pdev->dev; 1187ce38815dSXudong Chen i2c->adap.dev.parent = &pdev->dev; 1188ce38815dSXudong Chen i2c->adap.owner = THIS_MODULE; 1189ce38815dSXudong Chen i2c->adap.algo = &mtk_i2c_algorithm; 1190ce38815dSXudong Chen i2c->adap.quirks = i2c->dev_comp->quirks; 1191ce38815dSXudong Chen i2c->adap.timeout = 2 * HZ; 1192ce38815dSXudong Chen i2c->adap.retries = 1; 1193ce38815dSXudong Chen 11945a10e7d7SJun Gao ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 11955a10e7d7SJun Gao if (ret) 11965a10e7d7SJun Gao return -EINVAL; 11975a10e7d7SJun Gao 1198ce38815dSXudong Chen if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1199ce38815dSXudong Chen return -EINVAL; 1200ce38815dSXudong Chen 1201ce38815dSXudong Chen i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1202ce38815dSXudong Chen if (IS_ERR(i2c->clk_main)) { 1203ce38815dSXudong Chen dev_err(&pdev->dev, "cannot get main clock\n"); 1204ce38815dSXudong Chen return PTR_ERR(i2c->clk_main); 1205ce38815dSXudong Chen } 1206ce38815dSXudong Chen 1207ce38815dSXudong Chen i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1208ce38815dSXudong Chen if (IS_ERR(i2c->clk_dma)) { 1209ce38815dSXudong Chen dev_err(&pdev->dev, "cannot get dma clock\n"); 1210ce38815dSXudong Chen return PTR_ERR(i2c->clk_dma); 1211ce38815dSXudong Chen } 1212ce38815dSXudong Chen 1213cad6dc5dSQii Wang i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1214cad6dc5dSQii Wang if (IS_ERR(i2c->clk_arb)) 1215cad6dc5dSQii Wang i2c->clk_arb = NULL; 1216cad6dc5dSQii Wang 1217ce38815dSXudong Chen clk = i2c->clk_main; 1218ce38815dSXudong Chen if (i2c->have_pmic) { 1219ce38815dSXudong Chen i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1220ce38815dSXudong Chen if (IS_ERR(i2c->clk_pmic)) { 1221ce38815dSXudong Chen dev_err(&pdev->dev, "cannot get pmic clock\n"); 1222ce38815dSXudong Chen return PTR_ERR(i2c->clk_pmic); 1223ce38815dSXudong Chen } 1224ce38815dSXudong Chen clk = i2c->clk_pmic; 1225ce38815dSXudong Chen } 1226ce38815dSXudong Chen 1227ce38815dSXudong Chen strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1228ce38815dSXudong Chen 1229f2326401SJun Gao ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1230ce38815dSXudong Chen if (ret) { 1231ce38815dSXudong Chen dev_err(&pdev->dev, "Failed to set the speed.\n"); 1232ce38815dSXudong Chen return -EINVAL; 1233ce38815dSXudong Chen } 1234ce38815dSXudong Chen 1235f4f4fed6SLiguo Zhang if (i2c->dev_comp->support_33bits) { 1236f4f4fed6SLiguo Zhang ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33)); 1237f4f4fed6SLiguo Zhang if (ret) { 1238f4f4fed6SLiguo Zhang dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1239f4f4fed6SLiguo Zhang return ret; 1240f4f4fed6SLiguo Zhang } 1241f4f4fed6SLiguo Zhang } 1242f4f4fed6SLiguo Zhang 1243ce38815dSXudong Chen ret = mtk_i2c_clock_enable(i2c); 1244ce38815dSXudong Chen if (ret) { 1245ce38815dSXudong Chen dev_err(&pdev->dev, "clock enable failed!\n"); 1246ce38815dSXudong Chen return ret; 1247ce38815dSXudong Chen } 1248ce38815dSXudong Chen mtk_i2c_init_hw(i2c); 1249ce38815dSXudong Chen mtk_i2c_clock_disable(i2c); 1250ce38815dSXudong Chen 1251ce38815dSXudong Chen ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1252ce38815dSXudong Chen IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 1253ce38815dSXudong Chen if (ret < 0) { 1254ce38815dSXudong Chen dev_err(&pdev->dev, 1255ce38815dSXudong Chen "Request I2C IRQ %d fail\n", irq); 1256ce38815dSXudong Chen return ret; 1257ce38815dSXudong Chen } 1258ce38815dSXudong Chen 1259ce38815dSXudong Chen i2c_set_adapdata(&i2c->adap, i2c); 1260ce38815dSXudong Chen ret = i2c_add_adapter(&i2c->adap); 1261ea734404SWolfram Sang if (ret) 1262ce38815dSXudong Chen return ret; 1263ce38815dSXudong Chen 1264ce38815dSXudong Chen platform_set_drvdata(pdev, i2c); 1265ce38815dSXudong Chen 1266ce38815dSXudong Chen return 0; 1267ce38815dSXudong Chen } 1268ce38815dSXudong Chen 1269ce38815dSXudong Chen static int mtk_i2c_remove(struct platform_device *pdev) 1270ce38815dSXudong Chen { 1271ce38815dSXudong Chen struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1272ce38815dSXudong Chen 1273ce38815dSXudong Chen i2c_del_adapter(&i2c->adap); 1274ce38815dSXudong Chen 1275ce38815dSXudong Chen return 0; 1276ce38815dSXudong Chen } 1277ce38815dSXudong Chen 127809027e08SLiguo Zhang #ifdef CONFIG_PM_SLEEP 127909027e08SLiguo Zhang static int mtk_i2c_resume(struct device *dev) 128009027e08SLiguo Zhang { 1281f6762cedSJun Gao int ret; 128209027e08SLiguo Zhang struct mtk_i2c *i2c = dev_get_drvdata(dev); 128309027e08SLiguo Zhang 1284f6762cedSJun Gao ret = mtk_i2c_clock_enable(i2c); 1285f6762cedSJun Gao if (ret) { 1286f6762cedSJun Gao dev_err(dev, "clock enable failed!\n"); 1287f6762cedSJun Gao return ret; 1288f6762cedSJun Gao } 1289f6762cedSJun Gao 129009027e08SLiguo Zhang mtk_i2c_init_hw(i2c); 129109027e08SLiguo Zhang 1292f6762cedSJun Gao mtk_i2c_clock_disable(i2c); 1293f6762cedSJun Gao 129409027e08SLiguo Zhang return 0; 129509027e08SLiguo Zhang } 129609027e08SLiguo Zhang #endif 129709027e08SLiguo Zhang 129809027e08SLiguo Zhang static const struct dev_pm_ops mtk_i2c_pm = { 129909027e08SLiguo Zhang SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume) 130009027e08SLiguo Zhang }; 130109027e08SLiguo Zhang 1302ce38815dSXudong Chen static struct platform_driver mtk_i2c_driver = { 1303ce38815dSXudong Chen .probe = mtk_i2c_probe, 1304ce38815dSXudong Chen .remove = mtk_i2c_remove, 1305ce38815dSXudong Chen .driver = { 1306ce38815dSXudong Chen .name = I2C_DRV_NAME, 130709027e08SLiguo Zhang .pm = &mtk_i2c_pm, 1308ce38815dSXudong Chen .of_match_table = of_match_ptr(mtk_i2c_of_match), 1309ce38815dSXudong Chen }, 1310ce38815dSXudong Chen }; 1311ce38815dSXudong Chen 1312ce38815dSXudong Chen module_platform_driver(mtk_i2c_driver); 1313ce38815dSXudong Chen 1314ce38815dSXudong Chen MODULE_LICENSE("GPL v2"); 1315ce38815dSXudong Chen MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1316ce38815dSXudong Chen MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1317