1 /* 2 * (C) Copyright 2003-2004 3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk. 4 5 * This is a combined i2c adapter and algorithm driver for the 6 * MPC107/Tsi107 PowerPC northbridge and processors that include 7 * the same I2C unit (8240, 8245, 85xx). 8 * 9 * Release 0.8 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/sched.h> 19 #include <linux/init.h> 20 #include <linux/of_platform.h> 21 #include <linux/slab.h> 22 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/fsl_devices.h> 26 #include <linux/i2c.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 30 #include <asm/mpc52xx.h> 31 #include <sysdev/fsl_soc.h> 32 33 #define DRV_NAME "mpc-i2c" 34 35 #define MPC_I2C_CLOCK_LEGACY 0 36 #define MPC_I2C_CLOCK_PRESERVE (~0U) 37 38 #define MPC_I2C_FDR 0x04 39 #define MPC_I2C_CR 0x08 40 #define MPC_I2C_SR 0x0c 41 #define MPC_I2C_DR 0x10 42 #define MPC_I2C_DFSRR 0x14 43 44 #define CCR_MEN 0x80 45 #define CCR_MIEN 0x40 46 #define CCR_MSTA 0x20 47 #define CCR_MTX 0x10 48 #define CCR_TXAK 0x08 49 #define CCR_RSTA 0x04 50 51 #define CSR_MCF 0x80 52 #define CSR_MAAS 0x40 53 #define CSR_MBB 0x20 54 #define CSR_MAL 0x10 55 #define CSR_SRW 0x04 56 #define CSR_MIF 0x02 57 #define CSR_RXAK 0x01 58 59 struct mpc_i2c { 60 struct device *dev; 61 void __iomem *base; 62 u32 interrupt; 63 wait_queue_head_t queue; 64 struct i2c_adapter adap; 65 int irq; 66 u32 real_clk; 67 #ifdef CONFIG_PM_SLEEP 68 u8 fdr, dfsrr; 69 #endif 70 struct clk *clk_per; 71 }; 72 73 struct mpc_i2c_divider { 74 u16 divider; 75 u16 fdr; /* including dfsrr */ 76 }; 77 78 struct mpc_i2c_data { 79 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, 80 u32 clock, u32 prescaler); 81 u32 prescaler; 82 }; 83 84 static inline void writeccr(struct mpc_i2c *i2c, u32 x) 85 { 86 writeb(x, i2c->base + MPC_I2C_CR); 87 } 88 89 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 90 { 91 struct mpc_i2c *i2c = dev_id; 92 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { 93 /* Read again to allow register to stabilise */ 94 i2c->interrupt = readb(i2c->base + MPC_I2C_SR); 95 writeb(0, i2c->base + MPC_I2C_SR); 96 wake_up(&i2c->queue); 97 } 98 return IRQ_HANDLED; 99 } 100 101 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release 102 * the bus, because it wants to send ACK. 103 * Following sequence of enabling/disabling and sending start/stop generates 104 * the 9 pulses, so it's all OK. 105 */ 106 static void mpc_i2c_fixup(struct mpc_i2c *i2c) 107 { 108 int k; 109 u32 delay_val = 1000000 / i2c->real_clk + 1; 110 111 if (delay_val < 2) 112 delay_val = 2; 113 114 for (k = 9; k; k--) { 115 writeccr(i2c, 0); 116 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); 117 udelay(delay_val); 118 writeccr(i2c, CCR_MEN); 119 udelay(delay_val << 1); 120 } 121 } 122 123 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 124 { 125 unsigned long orig_jiffies = jiffies; 126 u32 x; 127 int result = 0; 128 129 if (!i2c->irq) { 130 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { 131 schedule(); 132 if (time_after(jiffies, orig_jiffies + timeout)) { 133 dev_dbg(i2c->dev, "timeout\n"); 134 writeccr(i2c, 0); 135 result = -EIO; 136 break; 137 } 138 } 139 x = readb(i2c->base + MPC_I2C_SR); 140 writeb(0, i2c->base + MPC_I2C_SR); 141 } else { 142 /* Interrupt mode */ 143 result = wait_event_timeout(i2c->queue, 144 (i2c->interrupt & CSR_MIF), timeout); 145 146 if (unlikely(!(i2c->interrupt & CSR_MIF))) { 147 dev_dbg(i2c->dev, "wait timeout\n"); 148 writeccr(i2c, 0); 149 result = -ETIMEDOUT; 150 } 151 152 x = i2c->interrupt; 153 i2c->interrupt = 0; 154 } 155 156 if (result < 0) 157 return result; 158 159 if (!(x & CSR_MCF)) { 160 dev_dbg(i2c->dev, "unfinished\n"); 161 return -EIO; 162 } 163 164 if (x & CSR_MAL) { 165 dev_dbg(i2c->dev, "MAL\n"); 166 return -EIO; 167 } 168 169 if (writing && (x & CSR_RXAK)) { 170 dev_dbg(i2c->dev, "No RXAK\n"); 171 /* generate stop */ 172 writeccr(i2c, CCR_MEN); 173 return -EIO; 174 } 175 return 0; 176 } 177 178 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) 179 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 180 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 181 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 182 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 183 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, 184 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, 185 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, 186 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, 187 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, 188 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, 189 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, 190 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, 191 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, 192 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, 193 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, 194 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, 195 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, 196 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, 197 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 198 }; 199 200 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, 201 int prescaler, u32 *real_clk) 202 { 203 const struct mpc_i2c_divider *div = NULL; 204 unsigned int pvr = mfspr(SPRN_PVR); 205 u32 divider; 206 int i; 207 208 if (clock == MPC_I2C_CLOCK_LEGACY) { 209 /* see below - default fdr = 0x3f -> div = 2048 */ 210 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048; 211 return -EINVAL; 212 } 213 214 /* Determine divider value */ 215 divider = mpc5xxx_get_bus_frequency(node) / clock; 216 217 /* 218 * We want to choose an FDR/DFSR that generates an I2C bus speed that 219 * is equal to or lower than the requested speed. 220 */ 221 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { 222 div = &mpc_i2c_dividers_52xx[i]; 223 /* Old MPC5200 rev A CPUs do not support the high bits */ 224 if (div->fdr & 0xc0 && pvr == 0x80822011) 225 continue; 226 if (div->divider >= divider) 227 break; 228 } 229 230 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; 231 return (int)div->fdr; 232 } 233 234 static void mpc_i2c_setup_52xx(struct device_node *node, 235 struct mpc_i2c *i2c, 236 u32 clock, u32 prescaler) 237 { 238 int ret, fdr; 239 240 if (clock == MPC_I2C_CLOCK_PRESERVE) { 241 dev_dbg(i2c->dev, "using fdr %d\n", 242 readb(i2c->base + MPC_I2C_FDR)); 243 return; 244 } 245 246 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk); 247 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 248 249 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 250 251 if (ret >= 0) 252 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, 253 fdr); 254 } 255 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ 256 static void mpc_i2c_setup_52xx(struct device_node *node, 257 struct mpc_i2c *i2c, 258 u32 clock, u32 prescaler) 259 { 260 } 261 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ 262 263 #ifdef CONFIG_PPC_MPC512x 264 static void mpc_i2c_setup_512x(struct device_node *node, 265 struct mpc_i2c *i2c, 266 u32 clock, u32 prescaler) 267 { 268 struct device_node *node_ctrl; 269 void __iomem *ctrl; 270 const u32 *pval; 271 u32 idx; 272 273 /* Enable I2C interrupts for mpc5121 */ 274 node_ctrl = of_find_compatible_node(NULL, NULL, 275 "fsl,mpc5121-i2c-ctrl"); 276 if (node_ctrl) { 277 ctrl = of_iomap(node_ctrl, 0); 278 if (ctrl) { 279 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ 280 pval = of_get_property(node, "reg", NULL); 281 idx = (*pval & 0xff) / 0x20; 282 setbits32(ctrl, 1 << (24 + idx * 2)); 283 iounmap(ctrl); 284 } 285 of_node_put(node_ctrl); 286 } 287 288 /* The clock setup for the 52xx works also fine for the 512x */ 289 mpc_i2c_setup_52xx(node, i2c, clock, prescaler); 290 } 291 #else /* CONFIG_PPC_MPC512x */ 292 static void mpc_i2c_setup_512x(struct device_node *node, 293 struct mpc_i2c *i2c, 294 u32 clock, u32 prescaler) 295 { 296 } 297 #endif /* CONFIG_PPC_MPC512x */ 298 299 #ifdef CONFIG_FSL_SOC 300 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { 301 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 302 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 303 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 304 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, 305 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, 306 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, 307 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, 308 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, 309 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, 310 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, 311 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, 312 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, 313 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, 314 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, 315 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, 316 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, 317 {49152, 0x011e}, {61440, 0x011f} 318 }; 319 320 static u32 mpc_i2c_get_sec_cfg_8xxx(void) 321 { 322 struct device_node *node = NULL; 323 u32 __iomem *reg; 324 u32 val = 0; 325 326 node = of_find_node_by_name(NULL, "global-utilities"); 327 if (node) { 328 const u32 *prop = of_get_property(node, "reg", NULL); 329 if (prop) { 330 /* 331 * Map and check POR Device Status Register 2 332 * (PORDEVSR2) at 0xE0014 333 */ 334 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); 335 if (!reg) 336 printk(KERN_ERR 337 "Error: couldn't map PORDEVSR2\n"); 338 else 339 val = in_be32(reg) & 0x00000080; /* sec-cfg */ 340 iounmap(reg); 341 } 342 } 343 if (node) 344 of_node_put(node); 345 346 return val; 347 } 348 349 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 350 u32 prescaler, u32 *real_clk) 351 { 352 const struct mpc_i2c_divider *div = NULL; 353 u32 divider; 354 int i; 355 356 if (clock == MPC_I2C_CLOCK_LEGACY) { 357 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ 358 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); 359 return -EINVAL; 360 } 361 362 /* Determine proper divider value */ 363 if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) 364 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; 365 if (!prescaler) 366 prescaler = 1; 367 368 divider = fsl_get_sys_freq() / clock / prescaler; 369 370 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", 371 fsl_get_sys_freq(), clock, divider); 372 373 /* 374 * We want to choose an FDR/DFSR that generates an I2C bus speed that 375 * is equal to or lower than the requested speed. 376 */ 377 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { 378 div = &mpc_i2c_dividers_8xxx[i]; 379 if (div->divider >= divider) 380 break; 381 } 382 383 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; 384 return div ? (int)div->fdr : -EINVAL; 385 } 386 387 static void mpc_i2c_setup_8xxx(struct device_node *node, 388 struct mpc_i2c *i2c, 389 u32 clock, u32 prescaler) 390 { 391 int ret, fdr; 392 393 if (clock == MPC_I2C_CLOCK_PRESERVE) { 394 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", 395 readb(i2c->base + MPC_I2C_DFSRR), 396 readb(i2c->base + MPC_I2C_FDR)); 397 return; 398 } 399 400 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk); 401 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 402 403 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 404 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); 405 406 if (ret >= 0) 407 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", 408 i2c->real_clk, fdr >> 8, fdr & 0xff); 409 } 410 411 #else /* !CONFIG_FSL_SOC */ 412 static void mpc_i2c_setup_8xxx(struct device_node *node, 413 struct mpc_i2c *i2c, 414 u32 clock, u32 prescaler) 415 { 416 } 417 #endif /* CONFIG_FSL_SOC */ 418 419 static void mpc_i2c_start(struct mpc_i2c *i2c) 420 { 421 /* Clear arbitration */ 422 writeb(0, i2c->base + MPC_I2C_SR); 423 /* Start with MEN */ 424 writeccr(i2c, CCR_MEN); 425 } 426 427 static void mpc_i2c_stop(struct mpc_i2c *i2c) 428 { 429 writeccr(i2c, CCR_MEN); 430 } 431 432 static int mpc_write(struct mpc_i2c *i2c, int target, 433 const u8 *data, int length, int restart) 434 { 435 int i, result; 436 unsigned timeout = i2c->adap.timeout; 437 u32 flags = restart ? CCR_RSTA : 0; 438 439 /* Start as master */ 440 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 441 /* Write target byte */ 442 writeb((target << 1), i2c->base + MPC_I2C_DR); 443 444 result = i2c_wait(i2c, timeout, 1); 445 if (result < 0) 446 return result; 447 448 for (i = 0; i < length; i++) { 449 /* Write data byte */ 450 writeb(data[i], i2c->base + MPC_I2C_DR); 451 452 result = i2c_wait(i2c, timeout, 1); 453 if (result < 0) 454 return result; 455 } 456 457 return 0; 458 } 459 460 static int mpc_read(struct mpc_i2c *i2c, int target, 461 u8 *data, int length, int restart, bool recv_len) 462 { 463 unsigned timeout = i2c->adap.timeout; 464 int i, result; 465 u32 flags = restart ? CCR_RSTA : 0; 466 467 /* Switch to read - restart */ 468 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 469 /* Write target address byte - this time with the read flag set */ 470 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); 471 472 result = i2c_wait(i2c, timeout, 1); 473 if (result < 0) 474 return result; 475 476 if (length) { 477 if (length == 1 && !recv_len) 478 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 479 else 480 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); 481 /* Dummy read */ 482 readb(i2c->base + MPC_I2C_DR); 483 } 484 485 for (i = 0; i < length; i++) { 486 u8 byte; 487 488 result = i2c_wait(i2c, timeout, 0); 489 if (result < 0) 490 return result; 491 492 /* 493 * For block reads, we have to know the total length (1st byte) 494 * before we can determine if we are done. 495 */ 496 if (i || !recv_len) { 497 /* Generate txack on next to last byte */ 498 if (i == length - 2) 499 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 500 | CCR_TXAK); 501 /* Do not generate stop on last byte */ 502 if (i == length - 1) 503 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 504 | CCR_MTX); 505 } 506 507 byte = readb(i2c->base + MPC_I2C_DR); 508 509 /* 510 * Adjust length if first received byte is length. 511 * The length is 1 length byte plus actually data length 512 */ 513 if (i == 0 && recv_len) { 514 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) 515 return -EPROTO; 516 length += byte; 517 /* 518 * For block reads, generate txack here if data length 519 * is 1 byte (total length is 2 bytes). 520 */ 521 if (length == 2) 522 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 523 | CCR_TXAK); 524 } 525 data[i] = byte; 526 } 527 528 return length; 529 } 530 531 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 532 { 533 struct i2c_msg *pmsg; 534 int i; 535 int ret = 0; 536 unsigned long orig_jiffies = jiffies; 537 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 538 539 mpc_i2c_start(i2c); 540 541 /* Allow bus up to 1s to become not busy */ 542 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 543 if (signal_pending(current)) { 544 dev_dbg(i2c->dev, "Interrupted\n"); 545 writeccr(i2c, 0); 546 return -EINTR; 547 } 548 if (time_after(jiffies, orig_jiffies + HZ)) { 549 u8 status = readb(i2c->base + MPC_I2C_SR); 550 551 dev_dbg(i2c->dev, "timeout\n"); 552 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 553 writeb(status & ~CSR_MAL, 554 i2c->base + MPC_I2C_SR); 555 mpc_i2c_fixup(i2c); 556 } 557 return -EIO; 558 } 559 schedule(); 560 } 561 562 for (i = 0; ret >= 0 && i < num; i++) { 563 pmsg = &msgs[i]; 564 dev_dbg(i2c->dev, 565 "Doing %s %d bytes to 0x%02x - %d of %d messages\n", 566 pmsg->flags & I2C_M_RD ? "read" : "write", 567 pmsg->len, pmsg->addr, i + 1, num); 568 if (pmsg->flags & I2C_M_RD) { 569 bool recv_len = pmsg->flags & I2C_M_RECV_LEN; 570 571 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, 572 recv_len); 573 if (recv_len && ret > 0) 574 pmsg->len = ret; 575 } else { 576 ret = 577 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 578 } 579 } 580 mpc_i2c_stop(i2c); /* Initiate STOP */ 581 orig_jiffies = jiffies; 582 /* Wait until STOP is seen, allow up to 1 s */ 583 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 584 if (time_after(jiffies, orig_jiffies + HZ)) { 585 u8 status = readb(i2c->base + MPC_I2C_SR); 586 587 dev_dbg(i2c->dev, "timeout\n"); 588 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 589 writeb(status & ~CSR_MAL, 590 i2c->base + MPC_I2C_SR); 591 mpc_i2c_fixup(i2c); 592 } 593 return -EIO; 594 } 595 cond_resched(); 596 } 597 return (ret < 0) ? ret : num; 598 } 599 600 static u32 mpc_functionality(struct i2c_adapter *adap) 601 { 602 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 603 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 604 } 605 606 static const struct i2c_algorithm mpc_algo = { 607 .master_xfer = mpc_xfer, 608 .functionality = mpc_functionality, 609 }; 610 611 static struct i2c_adapter mpc_ops = { 612 .owner = THIS_MODULE, 613 .algo = &mpc_algo, 614 .timeout = HZ, 615 }; 616 617 static const struct of_device_id mpc_i2c_of_match[]; 618 static int fsl_i2c_probe(struct platform_device *op) 619 { 620 const struct of_device_id *match; 621 struct mpc_i2c *i2c; 622 const u32 *prop; 623 u32 clock = MPC_I2C_CLOCK_LEGACY; 624 int result = 0; 625 int plen; 626 struct resource res; 627 struct clk *clk; 628 int err; 629 630 match = of_match_device(mpc_i2c_of_match, &op->dev); 631 if (!match) 632 return -EINVAL; 633 634 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 635 if (!i2c) 636 return -ENOMEM; 637 638 i2c->dev = &op->dev; /* for debug and error output */ 639 640 init_waitqueue_head(&i2c->queue); 641 642 i2c->base = of_iomap(op->dev.of_node, 0); 643 if (!i2c->base) { 644 dev_err(i2c->dev, "failed to map controller\n"); 645 result = -ENOMEM; 646 goto fail_map; 647 } 648 649 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0); 650 if (i2c->irq) { /* no i2c->irq implies polling */ 651 result = request_irq(i2c->irq, mpc_i2c_isr, 652 IRQF_SHARED, "i2c-mpc", i2c); 653 if (result < 0) { 654 dev_err(i2c->dev, "failed to attach interrupt\n"); 655 goto fail_request; 656 } 657 } 658 659 /* 660 * enable clock for the I2C peripheral (non fatal), 661 * keep a reference upon successful allocation 662 */ 663 clk = devm_clk_get(&op->dev, NULL); 664 if (!IS_ERR(clk)) { 665 err = clk_prepare_enable(clk); 666 if (err) { 667 dev_err(&op->dev, "failed to enable clock\n"); 668 goto fail_request; 669 } else { 670 i2c->clk_per = clk; 671 } 672 } 673 674 if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) { 675 clock = MPC_I2C_CLOCK_PRESERVE; 676 } else { 677 prop = of_get_property(op->dev.of_node, "clock-frequency", 678 &plen); 679 if (prop && plen == sizeof(u32)) 680 clock = *prop; 681 } 682 683 if (match->data) { 684 const struct mpc_i2c_data *data = match->data; 685 data->setup(op->dev.of_node, i2c, clock, data->prescaler); 686 } else { 687 /* Backwards compatibility */ 688 if (of_get_property(op->dev.of_node, "dfsrr", NULL)) 689 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0); 690 } 691 692 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen); 693 if (prop && plen == sizeof(u32)) { 694 mpc_ops.timeout = *prop * HZ / 1000000; 695 if (mpc_ops.timeout < 5) 696 mpc_ops.timeout = 5; 697 } 698 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 699 700 platform_set_drvdata(op, i2c); 701 702 i2c->adap = mpc_ops; 703 of_address_to_resource(op->dev.of_node, 0, &res); 704 scnprintf(i2c->adap.name, sizeof(i2c->adap.name), 705 "MPC adapter at 0x%llx", (unsigned long long)res.start); 706 i2c_set_adapdata(&i2c->adap, i2c); 707 i2c->adap.dev.parent = &op->dev; 708 i2c->adap.dev.of_node = of_node_get(op->dev.of_node); 709 710 result = i2c_add_adapter(&i2c->adap); 711 if (result < 0) { 712 dev_err(i2c->dev, "failed to add adapter\n"); 713 goto fail_add; 714 } 715 716 return result; 717 718 fail_add: 719 if (i2c->clk_per) 720 clk_disable_unprepare(i2c->clk_per); 721 free_irq(i2c->irq, i2c); 722 fail_request: 723 irq_dispose_mapping(i2c->irq); 724 iounmap(i2c->base); 725 fail_map: 726 kfree(i2c); 727 return result; 728 }; 729 730 static int fsl_i2c_remove(struct platform_device *op) 731 { 732 struct mpc_i2c *i2c = platform_get_drvdata(op); 733 734 i2c_del_adapter(&i2c->adap); 735 736 if (i2c->clk_per) 737 clk_disable_unprepare(i2c->clk_per); 738 739 if (i2c->irq) 740 free_irq(i2c->irq, i2c); 741 742 irq_dispose_mapping(i2c->irq); 743 iounmap(i2c->base); 744 kfree(i2c); 745 return 0; 746 }; 747 748 #ifdef CONFIG_PM_SLEEP 749 static int mpc_i2c_suspend(struct device *dev) 750 { 751 struct mpc_i2c *i2c = dev_get_drvdata(dev); 752 753 i2c->fdr = readb(i2c->base + MPC_I2C_FDR); 754 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); 755 756 return 0; 757 } 758 759 static int mpc_i2c_resume(struct device *dev) 760 { 761 struct mpc_i2c *i2c = dev_get_drvdata(dev); 762 763 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); 764 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); 765 766 return 0; 767 } 768 769 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); 770 #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops) 771 #else 772 #define MPC_I2C_PM_OPS NULL 773 #endif 774 775 static const struct mpc_i2c_data mpc_i2c_data_512x = { 776 .setup = mpc_i2c_setup_512x, 777 }; 778 779 static const struct mpc_i2c_data mpc_i2c_data_52xx = { 780 .setup = mpc_i2c_setup_52xx, 781 }; 782 783 static const struct mpc_i2c_data mpc_i2c_data_8313 = { 784 .setup = mpc_i2c_setup_8xxx, 785 }; 786 787 static const struct mpc_i2c_data mpc_i2c_data_8543 = { 788 .setup = mpc_i2c_setup_8xxx, 789 .prescaler = 2, 790 }; 791 792 static const struct mpc_i2c_data mpc_i2c_data_8544 = { 793 .setup = mpc_i2c_setup_8xxx, 794 .prescaler = 3, 795 }; 796 797 static const struct of_device_id mpc_i2c_of_match[] = { 798 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 799 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, 800 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 801 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, 802 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, 803 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, 804 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, 805 /* Backward compatibility */ 806 {.compatible = "fsl-i2c", }, 807 {}, 808 }; 809 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 810 811 /* Structure for a device driver */ 812 static struct platform_driver mpc_i2c_driver = { 813 .probe = fsl_i2c_probe, 814 .remove = fsl_i2c_remove, 815 .driver = { 816 .owner = THIS_MODULE, 817 .name = DRV_NAME, 818 .of_match_table = mpc_i2c_of_match, 819 .pm = MPC_I2C_PM_OPS, 820 }, 821 }; 822 823 module_platform_driver(mpc_i2c_driver); 824 825 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 826 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 827 "MPC824x/83xx/85xx/86xx/512x/52xx processors"); 828 MODULE_LICENSE("GPL"); 829