1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This is a combined i2c adapter and algorithm driver for the 4 * MPC107/Tsi107 PowerPC northbridge and processors that include 5 * the same I2C unit (8240, 8245, 85xx). 6 * 7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk 8 * Copyright (C) 2021 Allied Telesis Labs 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched/signal.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/property.h> 18 #include <linux/slab.h> 19 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/fsl_devices.h> 23 #include <linux/i2c.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 27 #include <asm/mpc52xx.h> 28 #include <asm/mpc85xx.h> 29 #include <sysdev/fsl_soc.h> 30 31 #define DRV_NAME "mpc-i2c" 32 33 #define MPC_I2C_CLOCK_LEGACY 0 34 #define MPC_I2C_CLOCK_PRESERVE (~0U) 35 36 #define MPC_I2C_FDR 0x04 37 #define MPC_I2C_CR 0x08 38 #define MPC_I2C_SR 0x0c 39 #define MPC_I2C_DR 0x10 40 #define MPC_I2C_DFSRR 0x14 41 42 #define CCR_MEN 0x80 43 #define CCR_MIEN 0x40 44 #define CCR_MSTA 0x20 45 #define CCR_MTX 0x10 46 #define CCR_TXAK 0x08 47 #define CCR_RSTA 0x04 48 49 #define CSR_MCF 0x80 50 #define CSR_MAAS 0x40 51 #define CSR_MBB 0x20 52 #define CSR_MAL 0x10 53 #define CSR_SRW 0x04 54 #define CSR_MIF 0x02 55 #define CSR_RXAK 0x01 56 57 enum mpc_i2c_action { 58 MPC_I2C_ACTION_START = 1, 59 MPC_I2C_ACTION_RESTART, 60 MPC_I2C_ACTION_READ_BEGIN, 61 MPC_I2C_ACTION_READ_BYTE, 62 MPC_I2C_ACTION_WRITE, 63 MPC_I2C_ACTION_STOP, 64 65 __MPC_I2C_ACTION_CNT 66 }; 67 68 static const char * const action_str[] = { 69 "invalid", 70 "start", 71 "restart", 72 "read begin", 73 "read", 74 "write", 75 "stop", 76 }; 77 78 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT); 79 80 struct mpc_i2c { 81 struct device *dev; 82 void __iomem *base; 83 u32 interrupt; 84 wait_queue_head_t waitq; 85 spinlock_t lock; 86 struct i2c_adapter adap; 87 int irq; 88 u32 real_clk; 89 u8 fdr, dfsrr; 90 struct clk *clk_per; 91 u32 cntl_bits; 92 enum mpc_i2c_action action; 93 struct i2c_msg *msgs; 94 int num_msgs; 95 int curr_msg; 96 u32 byte_posn; 97 u32 block; 98 int rc; 99 int expect_rxack; 100 101 }; 102 103 struct mpc_i2c_divider { 104 u16 divider; 105 u16 fdr; /* including dfsrr */ 106 }; 107 108 struct mpc_i2c_data { 109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock); 110 }; 111 112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) 113 { 114 writeb(x, i2c->base + MPC_I2C_CR); 115 } 116 117 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release 118 * the bus, because it wants to send ACK. 119 * Following sequence of enabling/disabling and sending start/stop generates 120 * the 9 pulses, so it's all OK. 121 */ 122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) 123 { 124 int k; 125 u32 delay_val = 1000000 / i2c->real_clk + 1; 126 127 if (delay_val < 2) 128 delay_val = 2; 129 130 for (k = 9; k; k--) { 131 writeccr(i2c, 0); 132 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); 133 readb(i2c->base + MPC_I2C_DR); 134 writeccr(i2c, CCR_MEN); 135 udelay(delay_val << 1); 136 } 137 } 138 139 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) 140 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 141 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 142 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 143 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 144 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, 145 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, 146 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, 147 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, 148 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, 149 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, 150 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, 151 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, 152 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, 153 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, 154 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, 155 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, 156 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, 157 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, 158 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 159 }; 160 161 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, 162 u32 *real_clk) 163 { 164 const struct mpc_i2c_divider *div = NULL; 165 unsigned int pvr = mfspr(SPRN_PVR); 166 u32 divider; 167 int i; 168 169 if (clock == MPC_I2C_CLOCK_LEGACY) { 170 /* see below - default fdr = 0x3f -> div = 2048 */ 171 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048; 172 return -EINVAL; 173 } 174 175 /* Determine divider value */ 176 divider = mpc5xxx_get_bus_frequency(node) / clock; 177 178 /* 179 * We want to choose an FDR/DFSR that generates an I2C bus speed that 180 * is equal to or lower than the requested speed. 181 */ 182 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { 183 div = &mpc_i2c_dividers_52xx[i]; 184 /* Old MPC5200 rev A CPUs do not support the high bits */ 185 if (div->fdr & 0xc0 && pvr == 0x80822011) 186 continue; 187 if (div->divider >= divider) 188 break; 189 } 190 191 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; 192 return (int)div->fdr; 193 } 194 195 static void mpc_i2c_setup_52xx(struct device_node *node, 196 struct mpc_i2c *i2c, 197 u32 clock) 198 { 199 int ret, fdr; 200 201 if (clock == MPC_I2C_CLOCK_PRESERVE) { 202 dev_dbg(i2c->dev, "using fdr %d\n", 203 readb(i2c->base + MPC_I2C_FDR)); 204 return; 205 } 206 207 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk); 208 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 209 210 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 211 212 if (ret >= 0) 213 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, 214 fdr); 215 } 216 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ 217 static void mpc_i2c_setup_52xx(struct device_node *node, 218 struct mpc_i2c *i2c, 219 u32 clock) 220 { 221 } 222 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ 223 224 #ifdef CONFIG_PPC_MPC512x 225 static void mpc_i2c_setup_512x(struct device_node *node, 226 struct mpc_i2c *i2c, 227 u32 clock) 228 { 229 struct device_node *node_ctrl; 230 void __iomem *ctrl; 231 const u32 *pval; 232 u32 idx; 233 234 /* Enable I2C interrupts for mpc5121 */ 235 node_ctrl = of_find_compatible_node(NULL, NULL, 236 "fsl,mpc5121-i2c-ctrl"); 237 if (node_ctrl) { 238 ctrl = of_iomap(node_ctrl, 0); 239 if (ctrl) { 240 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ 241 pval = of_get_property(node, "reg", NULL); 242 idx = (*pval & 0xff) / 0x20; 243 setbits32(ctrl, 1 << (24 + idx * 2)); 244 iounmap(ctrl); 245 } 246 of_node_put(node_ctrl); 247 } 248 249 /* The clock setup for the 52xx works also fine for the 512x */ 250 mpc_i2c_setup_52xx(node, i2c, clock); 251 } 252 #else /* CONFIG_PPC_MPC512x */ 253 static void mpc_i2c_setup_512x(struct device_node *node, 254 struct mpc_i2c *i2c, 255 u32 clock) 256 { 257 } 258 #endif /* CONFIG_PPC_MPC512x */ 259 260 #ifdef CONFIG_FSL_SOC 261 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { 262 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 263 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 264 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 265 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, 266 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, 267 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, 268 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, 269 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, 270 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, 271 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, 272 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, 273 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, 274 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, 275 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, 276 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, 277 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, 278 {49152, 0x011e}, {61440, 0x011f} 279 }; 280 281 static u32 mpc_i2c_get_sec_cfg_8xxx(void) 282 { 283 struct device_node *node; 284 u32 __iomem *reg; 285 u32 val = 0; 286 287 node = of_find_node_by_name(NULL, "global-utilities"); 288 if (node) { 289 const u32 *prop = of_get_property(node, "reg", NULL); 290 if (prop) { 291 /* 292 * Map and check POR Device Status Register 2 293 * (PORDEVSR2) at 0xE0014. Note than while MPC8533 294 * and MPC8544 indicate SEC frequency ratio 295 * configuration as bit 26 in PORDEVSR2, other MPC8xxx 296 * parts may store it differently or may not have it 297 * at all. 298 */ 299 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); 300 if (!reg) 301 printk(KERN_ERR 302 "Error: couldn't map PORDEVSR2\n"); 303 else 304 val = in_be32(reg) & 0x00000020; /* sec-cfg */ 305 iounmap(reg); 306 } 307 } 308 of_node_put(node); 309 310 return val; 311 } 312 313 static u32 mpc_i2c_get_prescaler_8xxx(void) 314 { 315 /* 316 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx 317 * may have prescaler 1, 2, or 3, depending on the power-on 318 * configuration. 319 */ 320 u32 prescaler = 1; 321 322 /* mpc85xx */ 323 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2) 324 || pvr_version_is(PVR_VER_E500MC) 325 || pvr_version_is(PVR_VER_E5500) 326 || pvr_version_is(PVR_VER_E6500)) { 327 unsigned int svr = mfspr(SPRN_SVR); 328 329 if ((SVR_SOC_VER(svr) == SVR_8540) 330 || (SVR_SOC_VER(svr) == SVR_8541) 331 || (SVR_SOC_VER(svr) == SVR_8560) 332 || (SVR_SOC_VER(svr) == SVR_8555) 333 || (SVR_SOC_VER(svr) == SVR_8610)) 334 /* the above 85xx SoCs have prescaler 1 */ 335 prescaler = 1; 336 else if ((SVR_SOC_VER(svr) == SVR_8533) 337 || (SVR_SOC_VER(svr) == SVR_8544)) 338 /* the above 85xx SoCs have prescaler 3 or 2 */ 339 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; 340 else 341 /* all the other 85xx have prescaler 2 */ 342 prescaler = 2; 343 } 344 345 return prescaler; 346 } 347 348 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 349 u32 *real_clk) 350 { 351 const struct mpc_i2c_divider *div = NULL; 352 u32 prescaler = mpc_i2c_get_prescaler_8xxx(); 353 u32 divider; 354 int i; 355 356 if (clock == MPC_I2C_CLOCK_LEGACY) { 357 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ 358 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); 359 return -EINVAL; 360 } 361 362 divider = fsl_get_sys_freq() / clock / prescaler; 363 364 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", 365 fsl_get_sys_freq(), clock, divider); 366 367 /* 368 * We want to choose an FDR/DFSR that generates an I2C bus speed that 369 * is equal to or lower than the requested speed. 370 */ 371 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { 372 div = &mpc_i2c_dividers_8xxx[i]; 373 if (div->divider >= divider) 374 break; 375 } 376 377 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; 378 return (int)div->fdr; 379 } 380 381 static void mpc_i2c_setup_8xxx(struct device_node *node, 382 struct mpc_i2c *i2c, 383 u32 clock) 384 { 385 int ret, fdr; 386 387 if (clock == MPC_I2C_CLOCK_PRESERVE) { 388 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", 389 readb(i2c->base + MPC_I2C_DFSRR), 390 readb(i2c->base + MPC_I2C_FDR)); 391 return; 392 } 393 394 ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk); 395 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 396 397 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 398 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); 399 400 if (ret >= 0) 401 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", 402 i2c->real_clk, fdr >> 8, fdr & 0xff); 403 } 404 405 #else /* !CONFIG_FSL_SOC */ 406 static void mpc_i2c_setup_8xxx(struct device_node *node, 407 struct mpc_i2c *i2c, 408 u32 clock) 409 { 410 } 411 #endif /* CONFIG_FSL_SOC */ 412 413 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc) 414 { 415 i2c->rc = rc; 416 i2c->block = 0; 417 i2c->cntl_bits = CCR_MEN; 418 writeccr(i2c, i2c->cntl_bits); 419 wake_up(&i2c->waitq); 420 } 421 422 static void mpc_i2c_do_action(struct mpc_i2c *i2c) 423 { 424 struct i2c_msg *msg = &i2c->msgs[i2c->curr_msg]; 425 int dir = 0; 426 int recv_len = 0; 427 u8 byte; 428 429 dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]); 430 431 i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK); 432 433 if (msg->flags & I2C_M_RD) 434 dir = 1; 435 if (msg->flags & I2C_M_RECV_LEN) 436 recv_len = 1; 437 438 switch (i2c->action) { 439 case MPC_I2C_ACTION_RESTART: 440 i2c->cntl_bits |= CCR_RSTA; 441 fallthrough; 442 443 case MPC_I2C_ACTION_START: 444 i2c->cntl_bits |= CCR_MSTA | CCR_MTX; 445 writeccr(i2c, i2c->cntl_bits); 446 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR); 447 i2c->expect_rxack = 1; 448 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE; 449 break; 450 451 case MPC_I2C_ACTION_READ_BEGIN: 452 if (msg->len) { 453 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) 454 i2c->cntl_bits |= CCR_TXAK; 455 456 writeccr(i2c, i2c->cntl_bits); 457 /* Dummy read */ 458 readb(i2c->base + MPC_I2C_DR); 459 } 460 i2c->action = MPC_I2C_ACTION_READ_BYTE; 461 break; 462 463 case MPC_I2C_ACTION_READ_BYTE: 464 if (i2c->byte_posn || !recv_len) { 465 /* Generate Tx ACK on next to last byte */ 466 if (i2c->byte_posn == msg->len - 2) 467 i2c->cntl_bits |= CCR_TXAK; 468 /* Do not generate stop on last byte */ 469 if (i2c->byte_posn == msg->len - 1) 470 i2c->cntl_bits |= CCR_MTX; 471 472 writeccr(i2c, i2c->cntl_bits); 473 } 474 475 byte = readb(i2c->base + MPC_I2C_DR); 476 477 if (i2c->byte_posn == 0 && recv_len) { 478 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) { 479 mpc_i2c_finish(i2c, -EPROTO); 480 return; 481 } 482 msg->len += byte; 483 /* 484 * For block reads, generate Tx ACK here if data length 485 * is 1 byte (total length is 2 bytes). 486 */ 487 if (msg->len == 2) { 488 i2c->cntl_bits |= CCR_TXAK; 489 writeccr(i2c, i2c->cntl_bits); 490 } 491 } 492 493 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte); 494 msg->buf[i2c->byte_posn++] = byte; 495 break; 496 497 case MPC_I2C_ACTION_WRITE: 498 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], 499 msg->buf[i2c->byte_posn]); 500 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR); 501 i2c->expect_rxack = 1; 502 break; 503 504 case MPC_I2C_ACTION_STOP: 505 mpc_i2c_finish(i2c, 0); 506 break; 507 508 default: 509 WARN(1, "Unexpected action %d\n", i2c->action); 510 break; 511 } 512 513 if (msg->len == i2c->byte_posn) { 514 i2c->curr_msg++; 515 i2c->byte_posn = 0; 516 517 if (i2c->curr_msg == i2c->num_msgs) { 518 i2c->action = MPC_I2C_ACTION_STOP; 519 /* 520 * We don't get another interrupt on read so 521 * finish the transfer now 522 */ 523 if (dir) 524 mpc_i2c_finish(i2c, 0); 525 } else { 526 i2c->action = MPC_I2C_ACTION_RESTART; 527 } 528 } 529 } 530 531 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status) 532 { 533 spin_lock(&i2c->lock); 534 535 if (!(status & CSR_MCF)) { 536 dev_dbg(i2c->dev, "unfinished\n"); 537 mpc_i2c_finish(i2c, -EIO); 538 goto out; 539 } 540 541 if (status & CSR_MAL) { 542 dev_dbg(i2c->dev, "arbitration lost\n"); 543 mpc_i2c_finish(i2c, -EAGAIN); 544 goto out; 545 } 546 547 if (i2c->expect_rxack && (status & CSR_RXAK)) { 548 dev_dbg(i2c->dev, "no Rx ACK\n"); 549 mpc_i2c_finish(i2c, -ENXIO); 550 goto out; 551 } 552 i2c->expect_rxack = 0; 553 554 mpc_i2c_do_action(i2c); 555 556 out: 557 spin_unlock(&i2c->lock); 558 } 559 560 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 561 { 562 struct mpc_i2c *i2c = dev_id; 563 u8 status; 564 565 status = readb(i2c->base + MPC_I2C_SR); 566 if (status & CSR_MIF) { 567 writeb(0, i2c->base + MPC_I2C_SR); 568 mpc_i2c_do_intr(i2c, status); 569 return IRQ_HANDLED; 570 } 571 return IRQ_NONE; 572 } 573 574 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c) 575 { 576 long time_left; 577 578 time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout); 579 if (!time_left) 580 return -ETIMEDOUT; 581 if (time_left < 0) 582 return time_left; 583 584 return 0; 585 } 586 587 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c) 588 { 589 unsigned long orig_jiffies; 590 unsigned long flags; 591 int ret; 592 593 spin_lock_irqsave(&i2c->lock, flags); 594 595 i2c->curr_msg = 0; 596 i2c->rc = 0; 597 i2c->byte_posn = 0; 598 i2c->block = 1; 599 i2c->action = MPC_I2C_ACTION_START; 600 601 i2c->cntl_bits = CCR_MEN | CCR_MIEN; 602 writeb(0, i2c->base + MPC_I2C_SR); 603 writeccr(i2c, i2c->cntl_bits); 604 605 mpc_i2c_do_action(i2c); 606 607 spin_unlock_irqrestore(&i2c->lock, flags); 608 609 ret = mpc_i2c_wait_for_completion(i2c); 610 if (ret) 611 i2c->rc = ret; 612 613 if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT) 614 i2c_recover_bus(&i2c->adap); 615 616 orig_jiffies = jiffies; 617 /* Wait until STOP is seen, allow up to 1 s */ 618 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 619 if (time_after(jiffies, orig_jiffies + HZ)) { 620 u8 status = readb(i2c->base + MPC_I2C_SR); 621 622 dev_dbg(i2c->dev, "timeout\n"); 623 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 624 writeb(status & ~CSR_MAL, 625 i2c->base + MPC_I2C_SR); 626 i2c_recover_bus(&i2c->adap); 627 } 628 return -EIO; 629 } 630 cond_resched(); 631 } 632 633 return i2c->rc; 634 } 635 636 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 637 { 638 int rc, ret = num; 639 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 640 int i; 641 642 dev_dbg(i2c->dev, "num = %d\n", num); 643 for (i = 0; i < num; i++) 644 dev_dbg(i2c->dev, " addr = %02x, flags = %02x, len = %d, %*ph\n", 645 msgs[i].addr, msgs[i].flags, msgs[i].len, 646 msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len, 647 msgs[i].buf); 648 649 WARN_ON(i2c->msgs != NULL); 650 i2c->msgs = msgs; 651 i2c->num_msgs = num; 652 653 rc = mpc_i2c_execute_msg(i2c); 654 if (rc < 0) 655 ret = rc; 656 657 i2c->num_msgs = 0; 658 i2c->msgs = NULL; 659 660 return ret; 661 } 662 663 static u32 mpc_functionality(struct i2c_adapter *adap) 664 { 665 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 666 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 667 } 668 669 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap) 670 { 671 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 672 673 mpc_i2c_fixup(i2c); 674 675 return 0; 676 } 677 678 static const struct i2c_algorithm mpc_algo = { 679 .master_xfer = mpc_xfer, 680 .functionality = mpc_functionality, 681 }; 682 683 static struct i2c_adapter mpc_ops = { 684 .owner = THIS_MODULE, 685 .algo = &mpc_algo, 686 .timeout = HZ, 687 }; 688 689 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = { 690 .recover_bus = fsl_i2c_bus_recovery, 691 }; 692 693 static int fsl_i2c_probe(struct platform_device *op) 694 { 695 const struct mpc_i2c_data *data; 696 struct mpc_i2c *i2c; 697 const u32 *prop; 698 u32 clock = MPC_I2C_CLOCK_LEGACY; 699 int result = 0; 700 int plen; 701 struct clk *clk; 702 int err; 703 704 i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL); 705 if (!i2c) 706 return -ENOMEM; 707 708 i2c->dev = &op->dev; /* for debug and error output */ 709 710 init_waitqueue_head(&i2c->waitq); 711 spin_lock_init(&i2c->lock); 712 713 i2c->base = devm_platform_ioremap_resource(op, 0); 714 if (IS_ERR(i2c->base)) 715 return PTR_ERR(i2c->base); 716 717 i2c->irq = platform_get_irq(op, 0); 718 if (i2c->irq < 0) 719 return i2c->irq; 720 721 result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr, 722 IRQF_SHARED, "i2c-mpc", i2c); 723 if (result < 0) { 724 dev_err(i2c->dev, "failed to attach interrupt\n"); 725 return result; 726 } 727 728 /* 729 * enable clock for the I2C peripheral (non fatal), 730 * keep a reference upon successful allocation 731 */ 732 clk = devm_clk_get_optional(&op->dev, NULL); 733 if (IS_ERR(clk)) 734 return PTR_ERR(clk); 735 736 err = clk_prepare_enable(clk); 737 if (err) { 738 dev_err(&op->dev, "failed to enable clock\n"); 739 return err; 740 } 741 742 i2c->clk_per = clk; 743 744 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) { 745 clock = MPC_I2C_CLOCK_PRESERVE; 746 } else { 747 prop = of_get_property(op->dev.of_node, "clock-frequency", 748 &plen); 749 if (prop && plen == sizeof(u32)) 750 clock = *prop; 751 } 752 753 data = device_get_match_data(&op->dev); 754 if (data) { 755 data->setup(op->dev.of_node, i2c, clock); 756 } else { 757 /* Backwards compatibility */ 758 if (of_get_property(op->dev.of_node, "dfsrr", NULL)) 759 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock); 760 } 761 762 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen); 763 if (prop && plen == sizeof(u32)) { 764 mpc_ops.timeout = *prop * HZ / 1000000; 765 if (mpc_ops.timeout < 5) 766 mpc_ops.timeout = 5; 767 } 768 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 769 770 i2c->adap = mpc_ops; 771 scnprintf(i2c->adap.name, sizeof(i2c->adap.name), 772 "MPC adapter (%s)", of_node_full_name(op->dev.of_node)); 773 i2c->adap.dev.parent = &op->dev; 774 i2c->adap.nr = op->id; 775 i2c->adap.dev.of_node = of_node_get(op->dev.of_node); 776 i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info; 777 platform_set_drvdata(op, i2c); 778 i2c_set_adapdata(&i2c->adap, i2c); 779 780 result = i2c_add_numbered_adapter(&i2c->adap); 781 if (result) 782 goto fail_add; 783 784 return 0; 785 786 fail_add: 787 clk_disable_unprepare(i2c->clk_per); 788 789 return result; 790 }; 791 792 static int fsl_i2c_remove(struct platform_device *op) 793 { 794 struct mpc_i2c *i2c = platform_get_drvdata(op); 795 796 i2c_del_adapter(&i2c->adap); 797 798 clk_disable_unprepare(i2c->clk_per); 799 800 return 0; 801 }; 802 803 static int __maybe_unused mpc_i2c_suspend(struct device *dev) 804 { 805 struct mpc_i2c *i2c = dev_get_drvdata(dev); 806 807 i2c->fdr = readb(i2c->base + MPC_I2C_FDR); 808 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); 809 810 return 0; 811 } 812 813 static int __maybe_unused mpc_i2c_resume(struct device *dev) 814 { 815 struct mpc_i2c *i2c = dev_get_drvdata(dev); 816 817 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); 818 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); 819 820 return 0; 821 } 822 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); 823 824 static const struct mpc_i2c_data mpc_i2c_data_512x = { 825 .setup = mpc_i2c_setup_512x, 826 }; 827 828 static const struct mpc_i2c_data mpc_i2c_data_52xx = { 829 .setup = mpc_i2c_setup_52xx, 830 }; 831 832 static const struct mpc_i2c_data mpc_i2c_data_8313 = { 833 .setup = mpc_i2c_setup_8xxx, 834 }; 835 836 static const struct mpc_i2c_data mpc_i2c_data_8543 = { 837 .setup = mpc_i2c_setup_8xxx, 838 }; 839 840 static const struct mpc_i2c_data mpc_i2c_data_8544 = { 841 .setup = mpc_i2c_setup_8xxx, 842 }; 843 844 static const struct of_device_id mpc_i2c_of_match[] = { 845 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 846 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, 847 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 848 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, 849 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, 850 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, 851 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, 852 /* Backward compatibility */ 853 {.compatible = "fsl-i2c", }, 854 {}, 855 }; 856 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 857 858 /* Structure for a device driver */ 859 static struct platform_driver mpc_i2c_driver = { 860 .probe = fsl_i2c_probe, 861 .remove = fsl_i2c_remove, 862 .driver = { 863 .name = DRV_NAME, 864 .of_match_table = mpc_i2c_of_match, 865 .pm = &mpc_i2c_pm_ops, 866 }, 867 }; 868 869 module_platform_driver(mpc_i2c_driver); 870 871 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 872 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 873 "MPC824x/83xx/85xx/86xx/512x/52xx processors"); 874 MODULE_LICENSE("GPL"); 875