1 /* 2 * (C) Copyright 2003-2004 3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk. 4 5 * This is a combined i2c adapter and algorithm driver for the 6 * MPC107/Tsi107 PowerPC northbridge and processors that include 7 * the same I2C unit (8240, 8245, 85xx). 8 * 9 * Release 0.8 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/sched.h> 19 #include <linux/init.h> 20 #include <linux/of_platform.h> 21 #include <linux/of_i2c.h> 22 #include <linux/slab.h> 23 24 #include <linux/io.h> 25 #include <linux/fsl_devices.h> 26 #include <linux/i2c.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 30 #include <asm/mpc52xx.h> 31 #include <sysdev/fsl_soc.h> 32 33 #define DRV_NAME "mpc-i2c" 34 35 #define MPC_I2C_CLOCK_LEGACY 0 36 #define MPC_I2C_CLOCK_PRESERVE (~0U) 37 38 #define MPC_I2C_FDR 0x04 39 #define MPC_I2C_CR 0x08 40 #define MPC_I2C_SR 0x0c 41 #define MPC_I2C_DR 0x10 42 #define MPC_I2C_DFSRR 0x14 43 44 #define CCR_MEN 0x80 45 #define CCR_MIEN 0x40 46 #define CCR_MSTA 0x20 47 #define CCR_MTX 0x10 48 #define CCR_TXAK 0x08 49 #define CCR_RSTA 0x04 50 51 #define CSR_MCF 0x80 52 #define CSR_MAAS 0x40 53 #define CSR_MBB 0x20 54 #define CSR_MAL 0x10 55 #define CSR_SRW 0x04 56 #define CSR_MIF 0x02 57 #define CSR_RXAK 0x01 58 59 struct mpc_i2c { 60 struct device *dev; 61 void __iomem *base; 62 u32 interrupt; 63 wait_queue_head_t queue; 64 struct i2c_adapter adap; 65 int irq; 66 u32 real_clk; 67 #ifdef CONFIG_PM 68 u8 fdr, dfsrr; 69 #endif 70 }; 71 72 struct mpc_i2c_divider { 73 u16 divider; 74 u16 fdr; /* including dfsrr */ 75 }; 76 77 struct mpc_i2c_data { 78 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, 79 u32 clock, u32 prescaler); 80 u32 prescaler; 81 }; 82 83 static inline void writeccr(struct mpc_i2c *i2c, u32 x) 84 { 85 writeb(x, i2c->base + MPC_I2C_CR); 86 } 87 88 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 89 { 90 struct mpc_i2c *i2c = dev_id; 91 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { 92 /* Read again to allow register to stabilise */ 93 i2c->interrupt = readb(i2c->base + MPC_I2C_SR); 94 writeb(0, i2c->base + MPC_I2C_SR); 95 wake_up(&i2c->queue); 96 } 97 return IRQ_HANDLED; 98 } 99 100 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release 101 * the bus, because it wants to send ACK. 102 * Following sequence of enabling/disabling and sending start/stop generates 103 * the 9 pulses, so it's all OK. 104 */ 105 static void mpc_i2c_fixup(struct mpc_i2c *i2c) 106 { 107 int k; 108 u32 delay_val = 1000000 / i2c->real_clk + 1; 109 110 if (delay_val < 2) 111 delay_val = 2; 112 113 for (k = 9; k; k--) { 114 writeccr(i2c, 0); 115 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); 116 udelay(delay_val); 117 writeccr(i2c, CCR_MEN); 118 udelay(delay_val << 1); 119 } 120 } 121 122 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 123 { 124 unsigned long orig_jiffies = jiffies; 125 u32 x; 126 int result = 0; 127 128 if (!i2c->irq) { 129 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { 130 schedule(); 131 if (time_after(jiffies, orig_jiffies + timeout)) { 132 dev_dbg(i2c->dev, "timeout\n"); 133 writeccr(i2c, 0); 134 result = -EIO; 135 break; 136 } 137 } 138 x = readb(i2c->base + MPC_I2C_SR); 139 writeb(0, i2c->base + MPC_I2C_SR); 140 } else { 141 /* Interrupt mode */ 142 result = wait_event_timeout(i2c->queue, 143 (i2c->interrupt & CSR_MIF), timeout); 144 145 if (unlikely(!(i2c->interrupt & CSR_MIF))) { 146 dev_dbg(i2c->dev, "wait timeout\n"); 147 writeccr(i2c, 0); 148 result = -ETIMEDOUT; 149 } 150 151 x = i2c->interrupt; 152 i2c->interrupt = 0; 153 } 154 155 if (result < 0) 156 return result; 157 158 if (!(x & CSR_MCF)) { 159 dev_dbg(i2c->dev, "unfinished\n"); 160 return -EIO; 161 } 162 163 if (x & CSR_MAL) { 164 dev_dbg(i2c->dev, "MAL\n"); 165 return -EIO; 166 } 167 168 if (writing && (x & CSR_RXAK)) { 169 dev_dbg(i2c->dev, "No RXAK\n"); 170 /* generate stop */ 171 writeccr(i2c, CCR_MEN); 172 return -EIO; 173 } 174 return 0; 175 } 176 177 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) 178 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = { 179 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 180 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 181 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 182 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, 183 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, 184 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, 185 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, 186 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, 187 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, 188 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, 189 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, 190 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, 191 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, 192 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, 193 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, 194 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, 195 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, 196 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 197 }; 198 199 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, 200 int prescaler, u32 *real_clk) 201 { 202 const struct mpc_i2c_divider *div = NULL; 203 unsigned int pvr = mfspr(SPRN_PVR); 204 u32 divider; 205 int i; 206 207 if (clock == MPC_I2C_CLOCK_LEGACY) { 208 /* see below - default fdr = 0x3f -> div = 2048 */ 209 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048; 210 return -EINVAL; 211 } 212 213 /* Determine divider value */ 214 divider = mpc5xxx_get_bus_frequency(node) / clock; 215 216 /* 217 * We want to choose an FDR/DFSR that generates an I2C bus speed that 218 * is equal to or lower than the requested speed. 219 */ 220 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { 221 div = &mpc_i2c_dividers_52xx[i]; 222 /* Old MPC5200 rev A CPUs do not support the high bits */ 223 if (div->fdr & 0xc0 && pvr == 0x80822011) 224 continue; 225 if (div->divider >= divider) 226 break; 227 } 228 229 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; 230 return (int)div->fdr; 231 } 232 233 static void __devinit mpc_i2c_setup_52xx(struct device_node *node, 234 struct mpc_i2c *i2c, 235 u32 clock, u32 prescaler) 236 { 237 int ret, fdr; 238 239 if (clock == MPC_I2C_CLOCK_PRESERVE) { 240 dev_dbg(i2c->dev, "using fdr %d\n", 241 readb(i2c->base + MPC_I2C_FDR)); 242 return; 243 } 244 245 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk); 246 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 247 248 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 249 250 if (ret >= 0) 251 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, 252 fdr); 253 } 254 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ 255 static void __devinit mpc_i2c_setup_52xx(struct device_node *node, 256 struct mpc_i2c *i2c, 257 u32 clock, u32 prescaler) 258 { 259 } 260 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ 261 262 #ifdef CONFIG_PPC_MPC512x 263 static void __devinit mpc_i2c_setup_512x(struct device_node *node, 264 struct mpc_i2c *i2c, 265 u32 clock, u32 prescaler) 266 { 267 struct device_node *node_ctrl; 268 void __iomem *ctrl; 269 const u32 *pval; 270 u32 idx; 271 272 /* Enable I2C interrupts for mpc5121 */ 273 node_ctrl = of_find_compatible_node(NULL, NULL, 274 "fsl,mpc5121-i2c-ctrl"); 275 if (node_ctrl) { 276 ctrl = of_iomap(node_ctrl, 0); 277 if (ctrl) { 278 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ 279 pval = of_get_property(node, "reg", NULL); 280 idx = (*pval & 0xff) / 0x20; 281 setbits32(ctrl, 1 << (24 + idx * 2)); 282 iounmap(ctrl); 283 } 284 of_node_put(node_ctrl); 285 } 286 287 /* The clock setup for the 52xx works also fine for the 512x */ 288 mpc_i2c_setup_52xx(node, i2c, clock, prescaler); 289 } 290 #else /* CONFIG_PPC_MPC512x */ 291 static void __devinit mpc_i2c_setup_512x(struct device_node *node, 292 struct mpc_i2c *i2c, 293 u32 clock, u32 prescaler) 294 { 295 } 296 #endif /* CONFIG_PPC_MPC512x */ 297 298 #ifdef CONFIG_FSL_SOC 299 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = { 300 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 301 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 302 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 303 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, 304 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, 305 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, 306 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, 307 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, 308 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, 309 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, 310 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, 311 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, 312 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, 313 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, 314 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, 315 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, 316 {49152, 0x011e}, {61440, 0x011f} 317 }; 318 319 static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void) 320 { 321 struct device_node *node = NULL; 322 u32 __iomem *reg; 323 u32 val = 0; 324 325 node = of_find_node_by_name(NULL, "global-utilities"); 326 if (node) { 327 const u32 *prop = of_get_property(node, "reg", NULL); 328 if (prop) { 329 /* 330 * Map and check POR Device Status Register 2 331 * (PORDEVSR2) at 0xE0014 332 */ 333 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); 334 if (!reg) 335 printk(KERN_ERR 336 "Error: couldn't map PORDEVSR2\n"); 337 else 338 val = in_be32(reg) & 0x00000080; /* sec-cfg */ 339 iounmap(reg); 340 } 341 } 342 if (node) 343 of_node_put(node); 344 345 return val; 346 } 347 348 static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 349 u32 prescaler, u32 *real_clk) 350 { 351 const struct mpc_i2c_divider *div = NULL; 352 u32 divider; 353 int i; 354 355 if (clock == MPC_I2C_CLOCK_LEGACY) { 356 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ 357 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); 358 return -EINVAL; 359 } 360 361 /* Determine proper divider value */ 362 if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) 363 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; 364 if (!prescaler) 365 prescaler = 1; 366 367 divider = fsl_get_sys_freq() / clock / prescaler; 368 369 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", 370 fsl_get_sys_freq(), clock, divider); 371 372 /* 373 * We want to choose an FDR/DFSR that generates an I2C bus speed that 374 * is equal to or lower than the requested speed. 375 */ 376 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { 377 div = &mpc_i2c_dividers_8xxx[i]; 378 if (div->divider >= divider) 379 break; 380 } 381 382 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; 383 return div ? (int)div->fdr : -EINVAL; 384 } 385 386 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node, 387 struct mpc_i2c *i2c, 388 u32 clock, u32 prescaler) 389 { 390 int ret, fdr; 391 392 if (clock == MPC_I2C_CLOCK_PRESERVE) { 393 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", 394 readb(i2c->base + MPC_I2C_DFSRR), 395 readb(i2c->base + MPC_I2C_FDR)); 396 return; 397 } 398 399 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk); 400 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 401 402 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 403 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); 404 405 if (ret >= 0) 406 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", 407 i2c->real_clk, fdr >> 8, fdr & 0xff); 408 } 409 410 #else /* !CONFIG_FSL_SOC */ 411 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node, 412 struct mpc_i2c *i2c, 413 u32 clock, u32 prescaler) 414 { 415 } 416 #endif /* CONFIG_FSL_SOC */ 417 418 static void mpc_i2c_start(struct mpc_i2c *i2c) 419 { 420 /* Clear arbitration */ 421 writeb(0, i2c->base + MPC_I2C_SR); 422 /* Start with MEN */ 423 writeccr(i2c, CCR_MEN); 424 } 425 426 static void mpc_i2c_stop(struct mpc_i2c *i2c) 427 { 428 writeccr(i2c, CCR_MEN); 429 } 430 431 static int mpc_write(struct mpc_i2c *i2c, int target, 432 const u8 *data, int length, int restart) 433 { 434 int i, result; 435 unsigned timeout = i2c->adap.timeout; 436 u32 flags = restart ? CCR_RSTA : 0; 437 438 /* Start as master */ 439 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 440 /* Write target byte */ 441 writeb((target << 1), i2c->base + MPC_I2C_DR); 442 443 result = i2c_wait(i2c, timeout, 1); 444 if (result < 0) 445 return result; 446 447 for (i = 0; i < length; i++) { 448 /* Write data byte */ 449 writeb(data[i], i2c->base + MPC_I2C_DR); 450 451 result = i2c_wait(i2c, timeout, 1); 452 if (result < 0) 453 return result; 454 } 455 456 return 0; 457 } 458 459 static int mpc_read(struct mpc_i2c *i2c, int target, 460 u8 *data, int length, int restart, bool recv_len) 461 { 462 unsigned timeout = i2c->adap.timeout; 463 int i, result; 464 u32 flags = restart ? CCR_RSTA : 0; 465 466 /* Switch to read - restart */ 467 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 468 /* Write target address byte - this time with the read flag set */ 469 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); 470 471 result = i2c_wait(i2c, timeout, 1); 472 if (result < 0) 473 return result; 474 475 if (length) { 476 if (length == 1 && !recv_len) 477 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 478 else 479 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); 480 /* Dummy read */ 481 readb(i2c->base + MPC_I2C_DR); 482 } 483 484 for (i = 0; i < length; i++) { 485 u8 byte; 486 487 result = i2c_wait(i2c, timeout, 0); 488 if (result < 0) 489 return result; 490 491 /* 492 * For block reads, we have to know the total length (1st byte) 493 * before we can determine if we are done. 494 */ 495 if (i || !recv_len) { 496 /* Generate txack on next to last byte */ 497 if (i == length - 2) 498 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 499 | CCR_TXAK); 500 /* Do not generate stop on last byte */ 501 if (i == length - 1) 502 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 503 | CCR_MTX); 504 } 505 506 byte = readb(i2c->base + MPC_I2C_DR); 507 508 /* 509 * Adjust length if first received byte is length. 510 * The length is 1 length byte plus actually data length 511 */ 512 if (i == 0 && recv_len) { 513 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) 514 return -EPROTO; 515 length += byte; 516 /* 517 * For block reads, generate txack here if data length 518 * is 1 byte (total length is 2 bytes). 519 */ 520 if (length == 2) 521 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 522 | CCR_TXAK); 523 } 524 data[i] = byte; 525 } 526 527 return length; 528 } 529 530 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 531 { 532 struct i2c_msg *pmsg; 533 int i; 534 int ret = 0; 535 unsigned long orig_jiffies = jiffies; 536 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 537 538 mpc_i2c_start(i2c); 539 540 /* Allow bus up to 1s to become not busy */ 541 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 542 if (signal_pending(current)) { 543 dev_dbg(i2c->dev, "Interrupted\n"); 544 writeccr(i2c, 0); 545 return -EINTR; 546 } 547 if (time_after(jiffies, orig_jiffies + HZ)) { 548 u8 status = readb(i2c->base + MPC_I2C_SR); 549 550 dev_dbg(i2c->dev, "timeout\n"); 551 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 552 writeb(status & ~CSR_MAL, 553 i2c->base + MPC_I2C_SR); 554 mpc_i2c_fixup(i2c); 555 } 556 return -EIO; 557 } 558 schedule(); 559 } 560 561 for (i = 0; ret >= 0 && i < num; i++) { 562 pmsg = &msgs[i]; 563 dev_dbg(i2c->dev, 564 "Doing %s %d bytes to 0x%02x - %d of %d messages\n", 565 pmsg->flags & I2C_M_RD ? "read" : "write", 566 pmsg->len, pmsg->addr, i + 1, num); 567 if (pmsg->flags & I2C_M_RD) { 568 bool recv_len = pmsg->flags & I2C_M_RECV_LEN; 569 570 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, 571 recv_len); 572 if (recv_len && ret > 0) 573 pmsg->len = ret; 574 } else { 575 ret = 576 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 577 } 578 } 579 mpc_i2c_stop(i2c); /* Initiate STOP */ 580 orig_jiffies = jiffies; 581 /* Wait until STOP is seen, allow up to 1 s */ 582 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 583 if (time_after(jiffies, orig_jiffies + HZ)) { 584 u8 status = readb(i2c->base + MPC_I2C_SR); 585 586 dev_dbg(i2c->dev, "timeout\n"); 587 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 588 writeb(status & ~CSR_MAL, 589 i2c->base + MPC_I2C_SR); 590 mpc_i2c_fixup(i2c); 591 } 592 return -EIO; 593 } 594 cond_resched(); 595 } 596 return (ret < 0) ? ret : num; 597 } 598 599 static u32 mpc_functionality(struct i2c_adapter *adap) 600 { 601 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 602 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 603 } 604 605 static const struct i2c_algorithm mpc_algo = { 606 .master_xfer = mpc_xfer, 607 .functionality = mpc_functionality, 608 }; 609 610 static struct i2c_adapter mpc_ops = { 611 .owner = THIS_MODULE, 612 .name = "MPC adapter", 613 .algo = &mpc_algo, 614 .timeout = HZ, 615 }; 616 617 static const struct of_device_id mpc_i2c_of_match[]; 618 static int __devinit fsl_i2c_probe(struct platform_device *op) 619 { 620 const struct of_device_id *match; 621 struct mpc_i2c *i2c; 622 const u32 *prop; 623 u32 clock = MPC_I2C_CLOCK_LEGACY; 624 int result = 0; 625 int plen; 626 627 match = of_match_device(mpc_i2c_of_match, &op->dev); 628 if (!match) 629 return -EINVAL; 630 631 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 632 if (!i2c) 633 return -ENOMEM; 634 635 i2c->dev = &op->dev; /* for debug and error output */ 636 637 init_waitqueue_head(&i2c->queue); 638 639 i2c->base = of_iomap(op->dev.of_node, 0); 640 if (!i2c->base) { 641 dev_err(i2c->dev, "failed to map controller\n"); 642 result = -ENOMEM; 643 goto fail_map; 644 } 645 646 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0); 647 if (i2c->irq) { /* no i2c->irq implies polling */ 648 result = request_irq(i2c->irq, mpc_i2c_isr, 649 IRQF_SHARED, "i2c-mpc", i2c); 650 if (result < 0) { 651 dev_err(i2c->dev, "failed to attach interrupt\n"); 652 goto fail_request; 653 } 654 } 655 656 if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) { 657 clock = MPC_I2C_CLOCK_PRESERVE; 658 } else { 659 prop = of_get_property(op->dev.of_node, "clock-frequency", 660 &plen); 661 if (prop && plen == sizeof(u32)) 662 clock = *prop; 663 } 664 665 if (match->data) { 666 const struct mpc_i2c_data *data = match->data; 667 data->setup(op->dev.of_node, i2c, clock, data->prescaler); 668 } else { 669 /* Backwards compatibility */ 670 if (of_get_property(op->dev.of_node, "dfsrr", NULL)) 671 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0); 672 } 673 674 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen); 675 if (prop && plen == sizeof(u32)) { 676 mpc_ops.timeout = *prop * HZ / 1000000; 677 if (mpc_ops.timeout < 5) 678 mpc_ops.timeout = 5; 679 } 680 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 681 682 dev_set_drvdata(&op->dev, i2c); 683 684 i2c->adap = mpc_ops; 685 i2c_set_adapdata(&i2c->adap, i2c); 686 i2c->adap.dev.parent = &op->dev; 687 i2c->adap.dev.of_node = of_node_get(op->dev.of_node); 688 689 result = i2c_add_adapter(&i2c->adap); 690 if (result < 0) { 691 dev_err(i2c->dev, "failed to add adapter\n"); 692 goto fail_add; 693 } 694 of_i2c_register_devices(&i2c->adap); 695 696 return result; 697 698 fail_add: 699 dev_set_drvdata(&op->dev, NULL); 700 free_irq(i2c->irq, i2c); 701 fail_request: 702 irq_dispose_mapping(i2c->irq); 703 iounmap(i2c->base); 704 fail_map: 705 kfree(i2c); 706 return result; 707 }; 708 709 static int __devexit fsl_i2c_remove(struct platform_device *op) 710 { 711 struct mpc_i2c *i2c = dev_get_drvdata(&op->dev); 712 713 i2c_del_adapter(&i2c->adap); 714 dev_set_drvdata(&op->dev, NULL); 715 716 if (i2c->irq) 717 free_irq(i2c->irq, i2c); 718 719 irq_dispose_mapping(i2c->irq); 720 iounmap(i2c->base); 721 kfree(i2c); 722 return 0; 723 }; 724 725 #ifdef CONFIG_PM 726 static int mpc_i2c_suspend(struct device *dev) 727 { 728 struct mpc_i2c *i2c = dev_get_drvdata(dev); 729 730 i2c->fdr = readb(i2c->base + MPC_I2C_FDR); 731 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); 732 733 return 0; 734 } 735 736 static int mpc_i2c_resume(struct device *dev) 737 { 738 struct mpc_i2c *i2c = dev_get_drvdata(dev); 739 740 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); 741 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); 742 743 return 0; 744 } 745 746 SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); 747 #endif 748 749 static const struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = { 750 .setup = mpc_i2c_setup_512x, 751 }; 752 753 static const struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = { 754 .setup = mpc_i2c_setup_52xx, 755 }; 756 757 static const struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = { 758 .setup = mpc_i2c_setup_8xxx, 759 }; 760 761 static const struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = { 762 .setup = mpc_i2c_setup_8xxx, 763 .prescaler = 2, 764 }; 765 766 static const struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = { 767 .setup = mpc_i2c_setup_8xxx, 768 .prescaler = 3, 769 }; 770 771 static const struct of_device_id mpc_i2c_of_match[] = { 772 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 773 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, 774 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 775 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, 776 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, 777 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, 778 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, 779 /* Backward compatibility */ 780 {.compatible = "fsl-i2c", }, 781 {}, 782 }; 783 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 784 785 /* Structure for a device driver */ 786 static struct platform_driver mpc_i2c_driver = { 787 .probe = fsl_i2c_probe, 788 .remove = __devexit_p(fsl_i2c_remove), 789 .driver = { 790 .owner = THIS_MODULE, 791 .name = DRV_NAME, 792 .of_match_table = mpc_i2c_of_match, 793 #ifdef CONFIG_PM 794 .pm = &mpc_i2c_pm_ops, 795 #endif 796 }, 797 }; 798 799 module_platform_driver(mpc_i2c_driver); 800 801 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 802 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 803 "MPC824x/83xx/85xx/86xx/512x/52xx processors"); 804 MODULE_LICENSE("GPL"); 805