1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/i2c.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/string.h> 20 21 /* Defines what functionality is present. */ 22 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 23 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 24 25 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 26 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 27 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 28 I2C_FUNC_SMBUS_PROC_CALL) 29 30 #define MLXBF_I2C_FUNC_ALL \ 31 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 32 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 33 34 #define MLXBF_I2C_SMBUS_MAX 3 35 36 /* Shared resources info in BlueField platforms. */ 37 38 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 39 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 40 41 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 42 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 43 44 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 45 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 46 47 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 48 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 49 50 #define MLXBF_I2C_SHARED_RES_MAX 3 51 52 /* 53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 54 * refer to their respective offsets relative to the corresponding 55 * memory-mapped region whose addresses are specified in either the DT or 56 * the ACPI tables or above. 57 */ 58 59 /* 60 * SMBus Master core clock frequency. Timing configurations are 61 * strongly dependent on the core clock frequency of the SMBus 62 * Master. Default value is set to 400MHz. 63 */ 64 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 65 /* Reference clock for Bluefield 1 - 156 MHz. */ 66 #define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000) 67 /* Reference clock for BlueField 2 - 200 MHz. */ 68 #define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000) 69 70 /* Constant used to determine the PLL frequency. */ 71 #define MLNXBF_I2C_COREPLL_CONST 16384 72 73 /* PLL registers. */ 74 #define MLXBF_I2C_CORE_PLL_REG0 0x0 75 #define MLXBF_I2C_CORE_PLL_REG1 0x4 76 #define MLXBF_I2C_CORE_PLL_REG2 0x8 77 78 /* OR cause register. */ 79 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 80 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 81 82 /* Arbiter Cause Register. */ 83 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 84 85 /* 86 * Cause Status flags. Note that those bits might be considered 87 * as interrupt enabled bits. 88 */ 89 90 /* Transaction ended with STOP. */ 91 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 92 /* Master arbitration lost. */ 93 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 94 /* Unexpected start detected. */ 95 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 96 /* Unexpected stop detected. */ 97 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 98 /* Wait for transfer continuation. */ 99 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 100 /* Failed to generate STOP. */ 101 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 102 /* Failed to generate START. */ 103 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 104 /* Clock toggle completed. */ 105 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 106 /* Transfer timeout occurred. */ 107 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 108 /* Master busy bit reset. */ 109 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 110 111 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 112 113 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 114 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 115 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 116 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 117 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 118 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 119 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 120 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 121 122 /* 123 * Slave cause status flags. Note that those bits might be considered 124 * as interrupt enabled bits. 125 */ 126 127 /* Write transaction received successfully. */ 128 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 129 /* Read transaction received, waiting for response. */ 130 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 131 /* Slave busy bit reset. */ 132 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 133 134 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0) 135 136 /* Cause coalesce registers. */ 137 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 138 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04 139 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08 140 141 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX 142 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 143 144 /* Functional enable register. */ 145 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 146 /* Force OE enable register. */ 147 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 148 /* 149 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 150 * SDA/SCL lines: 151 * 152 * SMBUS GW0 -> bits[26:25] 153 * SMBUS GW1 -> bits[28:27] 154 * SMBUS GW2 -> bits[30:29] 155 */ 156 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 157 158 /* Note that gw_id can be 0,1 or 2. */ 159 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 160 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 161 162 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 163 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 164 165 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 166 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 167 168 /* SMBus timing parameters. */ 169 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 170 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 171 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 172 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 173 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 174 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 175 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 176 177 enum { 178 MLXBF_I2C_TIMING_100KHZ = 100000, 179 MLXBF_I2C_TIMING_400KHZ = 400000, 180 MLXBF_I2C_TIMING_1000KHZ = 1000000, 181 }; 182 183 /* 184 * Defines SMBus operating frequency and core clock frequency. 185 * According to ADB files, default values are compliant to 100KHz SMBus 186 * @ 400MHz core clock. The driver should be able to calculate core 187 * frequency based on PLL parameters. 188 */ 189 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 190 191 /* Core PLL TYU configuration. */ 192 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(12, 0) 193 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(3, 0) 194 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(5, 0) 195 196 #define MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT 3 197 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT 16 198 #define MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT 20 199 200 /* Core PLL YU configuration. */ 201 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 202 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 203 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(5, 0) 204 205 #define MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT 0 206 #define MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT 1 207 #define MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT 26 208 209 /* Core PLL frequency. */ 210 static u64 mlxbf_i2c_corepll_frequency; 211 212 /* SMBus Master GW. */ 213 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200 214 /* Number of bytes received and sent. */ 215 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300 216 /* Packet error check (PEC) value. */ 217 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304 218 /* Status bits (ACK/NACK/FW Timeout). */ 219 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308 220 /* SMbus Master Finite State Machine. */ 221 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310 222 223 /* 224 * When enabled, the master will issue a stop condition in case of 225 * timeout while waiting for FW response. 226 */ 227 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c 228 229 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 230 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 231 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 232 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 233 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 234 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 235 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 236 237 #define MLXBF_I2C_MASTER_ENABLE \ 238 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 239 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 240 241 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 242 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 243 244 #define MLXBF_I2C_MASTER_ENABLE_READ \ 245 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 246 247 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */ 248 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */ 249 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */ 250 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */ 251 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */ 252 253 /* SMBus master GW Data descriptor. */ 254 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280 255 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 256 257 /* Maximum bytes to read/write per SMBus transaction. */ 258 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 259 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 260 261 /* All bytes were transmitted. */ 262 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 263 /* NACK received. */ 264 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 265 /* Slave's byte count >128 bytes. */ 266 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 267 /* Timeout occurred. */ 268 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 269 270 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 271 272 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 273 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 274 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 275 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 276 277 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 278 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 279 280 /* SMBus slave GW. */ 281 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400 282 /* Number of bytes received and sent from/to master. */ 283 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500 284 /* Packet error check (PEC) value. */ 285 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504 286 /* SMBus slave Finite State Machine (FSM). */ 287 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510 288 /* 289 * Should be set when all raised causes handled, and cleared by HW on 290 * every new cause. 291 */ 292 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c 293 294 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 295 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 296 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 297 298 #define MLXBF_I2C_SLAVE_ENABLE \ 299 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 300 301 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 302 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 303 304 /* SMBus slave GW Data descriptor. */ 305 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480 306 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 307 308 /* SMbus slave configuration registers. */ 309 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514 310 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 311 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 312 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 313 314 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \ 315 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) 316 317 /* 318 * Timeout is given in microsends. Note also that timeout handling is not 319 * exact. 320 */ 321 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 322 323 /* Encapsulates timing parameters. */ 324 struct mlxbf_i2c_timings { 325 u16 scl_high; /* Clock high period. */ 326 u16 scl_low; /* Clock low period. */ 327 u8 sda_rise; /* Data rise time. */ 328 u8 sda_fall; /* Data fall time. */ 329 u8 scl_rise; /* Clock rise time. */ 330 u8 scl_fall; /* Clock fall time. */ 331 u16 hold_start; /* Hold time after (REPEATED) START. */ 332 u16 hold_data; /* Data hold time. */ 333 u16 setup_start; /* REPEATED START condition setup time. */ 334 u16 setup_stop; /* STOP condition setup time. */ 335 u16 setup_data; /* Data setup time. */ 336 u16 pad; /* Padding. */ 337 u16 buf; /* Bus free time between STOP and START. */ 338 u16 thigh_max; /* Thigh max. */ 339 u32 timeout; /* Detect clock low timeout. */ 340 }; 341 342 enum { 343 MLXBF_I2C_F_READ = BIT(0), 344 MLXBF_I2C_F_WRITE = BIT(1), 345 MLXBF_I2C_F_NORESTART = BIT(3), 346 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 347 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 348 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 349 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 350 }; 351 352 struct mlxbf_i2c_smbus_operation { 353 u32 flags; 354 u32 length; /* Buffer length in bytes. */ 355 u8 *buffer; 356 }; 357 358 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 359 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 360 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 361 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 362 363 struct mlxbf_i2c_smbus_request { 364 u8 slave; 365 u8 operation_cnt; 366 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 367 }; 368 369 struct mlxbf_i2c_resource { 370 void __iomem *io; 371 struct resource *params; 372 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 373 u8 type; 374 }; 375 376 /* List of chip resources that are being accessed by the driver. */ 377 enum { 378 MLXBF_I2C_SMBUS_RES, 379 MLXBF_I2C_MST_CAUSE_RES, 380 MLXBF_I2C_SLV_CAUSE_RES, 381 MLXBF_I2C_COALESCE_RES, 382 MLXBF_I2C_COREPLL_RES, 383 MLXBF_I2C_GPIO_RES, 384 MLXBF_I2C_END_RES, 385 }; 386 387 /* Helper macro to define an I2C resource parameters. */ 388 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 389 { \ 390 .start = (addr), \ 391 .end = (addr) + (size) - 1, \ 392 .name = (str) \ 393 } 394 395 static struct resource mlxbf_i2c_coalesce_tyu_params = 396 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 397 MLXBF_I2C_COALESCE_TYU_SIZE, 398 "COALESCE_MEM"); 399 static struct resource mlxbf_i2c_corepll_tyu_params = 400 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 401 MLXBF_I2C_COREPLL_TYU_SIZE, 402 "COREPLL_MEM"); 403 static struct resource mlxbf_i2c_corepll_yu_params = 404 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 405 MLXBF_I2C_COREPLL_YU_SIZE, 406 "COREPLL_MEM"); 407 static struct resource mlxbf_i2c_gpio_tyu_params = 408 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 409 MLXBF_I2C_GPIO_TYU_SIZE, 410 "GPIO_MEM"); 411 412 static struct mutex mlxbf_i2c_coalesce_lock; 413 static struct mutex mlxbf_i2c_corepll_lock; 414 static struct mutex mlxbf_i2c_gpio_lock; 415 416 /* Mellanox BlueField chip type. */ 417 enum mlxbf_i2c_chip_type { 418 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 419 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */ 420 }; 421 422 struct mlxbf_i2c_chip_info { 423 enum mlxbf_i2c_chip_type type; 424 /* Chip shared resources that are being used by the I2C controller. */ 425 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 426 427 /* Callback to calculate the core PLL frequency. */ 428 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 429 }; 430 431 struct mlxbf_i2c_priv { 432 const struct mlxbf_i2c_chip_info *chip; 433 struct i2c_adapter adap; 434 struct mlxbf_i2c_resource *smbus; 435 struct mlxbf_i2c_resource *mst_cause; 436 struct mlxbf_i2c_resource *slv_cause; 437 struct mlxbf_i2c_resource *coalesce; 438 u64 frequency; /* Core frequency in Hz. */ 439 int bus; /* Physical bus identifier. */ 440 int irq; 441 struct i2c_client *slave; 442 }; 443 444 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 445 [MLXBF_I2C_CHIP_TYPE_1] = { 446 .params = &mlxbf_i2c_coalesce_tyu_params, 447 .lock = &mlxbf_i2c_coalesce_lock, 448 .type = MLXBF_I2C_COALESCE_RES 449 }, 450 {} 451 }; 452 453 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 454 [MLXBF_I2C_CHIP_TYPE_1] = { 455 .params = &mlxbf_i2c_corepll_tyu_params, 456 .lock = &mlxbf_i2c_corepll_lock, 457 .type = MLXBF_I2C_COREPLL_RES 458 }, 459 [MLXBF_I2C_CHIP_TYPE_2] = { 460 .params = &mlxbf_i2c_corepll_yu_params, 461 .lock = &mlxbf_i2c_corepll_lock, 462 .type = MLXBF_I2C_COREPLL_RES, 463 } 464 }; 465 466 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 467 [MLXBF_I2C_CHIP_TYPE_1] = { 468 .params = &mlxbf_i2c_gpio_tyu_params, 469 .lock = &mlxbf_i2c_gpio_lock, 470 .type = MLXBF_I2C_GPIO_RES 471 }, 472 {} 473 }; 474 475 static u8 mlxbf_i2c_bus_count; 476 477 static struct mutex mlxbf_i2c_bus_lock; 478 479 /* Polling frequency in microseconds. */ 480 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 481 482 #define MLXBF_I2C_SHIFT_0 0 483 #define MLXBF_I2C_SHIFT_8 8 484 #define MLXBF_I2C_SHIFT_16 16 485 #define MLXBF_I2C_SHIFT_24 24 486 487 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 488 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 489 490 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000 491 492 static void mlxbf_i2c_write(void __iomem *io, int reg, u32 val) 493 { 494 writel(val, io + reg); 495 } 496 497 static u32 mlxbf_i2c_read(void __iomem *io, int reg) 498 { 499 return readl(io + reg); 500 } 501 502 /* 503 * This function is used to read data from Master GW Data Descriptor. 504 * Data bytes in the Master GW Data Descriptor are shifted left so the 505 * data starts at the MSB of the descriptor registers as set by the 506 * underlying hardware. TYU_READ_DATA enables byte swapping while 507 * reading data bytes, and MUST be called by the SMBus read routines 508 * to copy data from the 32 * 32-bit HW Data registers a.k.a Master GW 509 * Data Descriptor. 510 */ 511 static u32 mlxbf_i2c_read_data(void __iomem *io, int reg) 512 { 513 return (u32)be32_to_cpu(mlxbf_i2c_read(io, reg)); 514 } 515 516 /* 517 * This function is used to write data to the Master GW Data Descriptor. 518 * Data copied to the Master GW Data Descriptor MUST be shifted left so 519 * the data starts at the MSB of the descriptor registers as required by 520 * the underlying hardware. TYU_WRITE_DATA enables byte swapping when 521 * writing data bytes, and MUST be called by the SMBus write routines to 522 * copy data to the 32 * 32-bit HW Data registers a.k.a Master GW Data 523 * Descriptor. 524 */ 525 static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val) 526 { 527 mlxbf_i2c_write(io, reg, (u32)cpu_to_be32(val)); 528 } 529 530 /* 531 * Function to poll a set of bits at a specific address; it checks whether 532 * the bits are equal to zero when eq_zero is set to 'true', and not equal 533 * to zero when eq_zero is set to 'false'. 534 * Note that the timeout is given in microseconds. 535 */ 536 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask, 537 bool eq_zero, u32 timeout) 538 { 539 u32 bits; 540 541 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 542 543 do { 544 bits = mlxbf_i2c_read(io, addr) & mask; 545 if (eq_zero ? bits == 0 : bits != 0) 546 return eq_zero ? 1 : bits; 547 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); 548 } while (timeout-- != 0); 549 550 return 0; 551 } 552 553 /* 554 * SW must make sure that the SMBus Master GW is idle before starting 555 * a transaction. Accordingly, this function polls the Master FSM stop 556 * bit; it returns false when the bit is asserted, true if not. 557 */ 558 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) 559 { 560 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK; 561 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM; 562 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT; 563 564 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout)) 565 return true; 566 567 return false; 568 } 569 570 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 571 u32 cause_status) 572 { 573 /* 574 * When transaction ended with STOP, all bytes were transmitted, 575 * and no NACK received, then the transaction ended successfully. 576 * On the other hand, when the GW is configured with the stop bit 577 * de-asserted then the SMBus expects the following GW configuration 578 * for transfer continuation. 579 */ 580 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 581 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 582 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 583 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 584 return true; 585 586 return false; 587 } 588 589 /* 590 * Poll SMBus master status and return transaction status, 591 * i.e. whether succeeded or failed. I2C and SMBus fault codes 592 * are returned as negative numbers from most calls, with zero 593 * or some positive number indicating a non-fault return. 594 */ 595 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 596 { 597 u32 master_status_bits; 598 u32 cause_status_bits; 599 600 /* 601 * GW busy bit is raised by the driver and cleared by the HW 602 * when the transaction is completed. The busy bit is a good 603 * indicator of transaction status. So poll the busy bit, and 604 * then read the cause and master status bits to determine if 605 * errors occurred during the transaction. 606 */ 607 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 608 MLXBF_I2C_MASTER_BUSY_BIT, true, 609 MLXBF_I2C_SMBUS_TIMEOUT); 610 611 /* Read cause status bits. */ 612 cause_status_bits = mlxbf_i2c_read(priv->mst_cause->io, 613 MLXBF_I2C_CAUSE_ARBITER); 614 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 615 616 /* 617 * Parse both Cause and Master GW bits, then return transaction status. 618 */ 619 620 master_status_bits = mlxbf_i2c_read(priv->smbus->io, 621 MLXBF_I2C_SMBUS_MASTER_STATUS); 622 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 623 624 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 625 cause_status_bits)) 626 return 0; 627 628 /* 629 * In case of timeout on GW busy, the ISR will clear busy bit but 630 * transaction ended bits cause will not be set so the transaction 631 * fails. Then, we must check Master GW status bits. 632 */ 633 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 634 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 635 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 636 return -EIO; 637 638 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 639 return -EAGAIN; 640 641 return -ETIMEDOUT; 642 } 643 644 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 645 const u8 *data, u8 length, u32 addr) 646 { 647 u8 offset, aligned_length; 648 u32 data32; 649 650 aligned_length = round_up(length, 4); 651 652 /* Copy data bytes from 4-byte aligned source buffer. */ 653 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 654 data32 = *((u32 *)(data + offset)); 655 mlxbf_i2c_write_data(priv->smbus->io, addr + offset, data32); 656 } 657 } 658 659 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 660 u8 *data, u8 length, u32 addr) 661 { 662 u32 data32, mask; 663 u8 byte, offset; 664 665 mask = sizeof(u32) - 1; 666 667 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 668 data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset); 669 *((u32 *)(data + offset)) = data32; 670 } 671 672 if (!(length & mask)) 673 return; 674 675 data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset); 676 677 for (byte = 0; byte < (length & mask); byte++) { 678 data[offset + byte] = data32 & GENMASK(7, 0); 679 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 680 } 681 } 682 683 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 684 u8 len, u8 block_en, u8 pec_en, bool read) 685 { 686 u32 command; 687 688 /* Set Master GW control word. */ 689 if (read) { 690 command = MLXBF_I2C_MASTER_ENABLE_READ; 691 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 692 } else { 693 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 694 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 695 } 696 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 697 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 698 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 699 700 /* Clear status bits. */ 701 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_STATUS, 0x0); 702 /* Set the cause data. */ 703 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0); 704 /* Zero PEC byte. */ 705 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_PEC, 0x0); 706 /* Zero byte count. */ 707 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_RS_BYTES, 0x0); 708 709 /* GW activation. */ 710 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, command); 711 712 /* 713 * Poll master status and check status bits. An ACK is sent when 714 * completing writing data to the bus (Master 'byte_count_done' bit 715 * is set to 1). 716 */ 717 return mlxbf_i2c_smbus_check_status(priv); 718 } 719 720 static int 721 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 722 struct mlxbf_i2c_smbus_request *request) 723 { 724 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 725 u8 op_idx, data_idx, data_len, write_len, read_len; 726 struct mlxbf_i2c_smbus_operation *operation; 727 u8 read_en, write_en, block_en, pec_en; 728 u8 slave, flags, addr; 729 u8 *read_buf; 730 int ret = 0; 731 732 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 733 return -EINVAL; 734 735 read_buf = NULL; 736 data_idx = 0; 737 read_en = 0; 738 write_en = 0; 739 write_len = 0; 740 read_len = 0; 741 block_en = 0; 742 pec_en = 0; 743 slave = request->slave & GENMASK(6, 0); 744 addr = slave << 1; 745 746 /* First of all, check whether the HW is idle. */ 747 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) 748 return -EBUSY; 749 750 /* Set first byte. */ 751 data_desc[data_idx++] = addr; 752 753 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 754 operation = &request->operation[op_idx]; 755 flags = operation->flags; 756 757 /* 758 * Note that read and write operations might be handled by a 759 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 760 * then write command byte and set the optional SMBus specific 761 * bits such as block_en and pec_en. These bits MUST be 762 * submitted by the first operation only. 763 */ 764 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 765 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 766 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 767 } 768 769 if (flags & MLXBF_I2C_F_WRITE) { 770 write_en = 1; 771 write_len += operation->length; 772 memcpy(data_desc + data_idx, 773 operation->buffer, operation->length); 774 data_idx += operation->length; 775 } 776 /* 777 * We assume that read operations are performed only once per 778 * SMBus transaction. *TBD* protect this statement so it won't 779 * be executed twice? or return an error if we try to read more 780 * than once? 781 */ 782 if (flags & MLXBF_I2C_F_READ) { 783 read_en = 1; 784 /* Subtract 1 as required by HW. */ 785 read_len = operation->length - 1; 786 read_buf = operation->buffer; 787 } 788 } 789 790 /* Set Master GW data descriptor. */ 791 data_len = write_len + 1; /* Add one byte of the slave address. */ 792 /* 793 * Note that data_len cannot be 0. Indeed, the slave address byte 794 * must be written to the data registers. 795 */ 796 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 797 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 798 799 if (write_en) { 800 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 801 pec_en, 0); 802 if (ret) 803 return ret; 804 } 805 806 if (read_en) { 807 /* Write slave address to Master GW data descriptor. */ 808 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 809 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 810 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 811 pec_en, 1); 812 if (!ret) { 813 /* Get Master GW data descriptor. */ 814 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 815 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 816 817 /* Get data from Master GW data descriptor. */ 818 memcpy(read_buf, data_desc, read_len + 1); 819 } 820 821 /* 822 * After a read operation the SMBus FSM ps (present state) 823 * needs to be 'manually' reset. This should be removed in 824 * next tag integration. 825 */ 826 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_FSM, 827 MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK); 828 } 829 830 return ret; 831 } 832 833 /* I2C SMBus protocols. */ 834 835 static void 836 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 837 u8 read) 838 { 839 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 840 841 request->operation[0].length = 0; 842 request->operation[0].flags = MLXBF_I2C_F_WRITE; 843 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 844 } 845 846 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 847 u8 *data, bool read, bool pec_check) 848 { 849 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 850 851 request->operation[0].length = 1; 852 request->operation[0].length += pec_check; 853 854 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 855 request->operation[0].flags |= read ? 856 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 857 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 858 859 request->operation[0].buffer = data; 860 } 861 862 static void 863 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 864 u8 *command, u8 *data, bool read, bool pec_check) 865 { 866 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 867 868 request->operation[0].length = 1; 869 request->operation[0].flags = 870 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 871 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 872 request->operation[0].buffer = command; 873 874 request->operation[1].length = 1; 875 request->operation[1].length += pec_check; 876 request->operation[1].flags = read ? 877 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 878 request->operation[1].buffer = data; 879 } 880 881 static void 882 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 883 u8 *command, u8 *data, bool read, bool pec_check) 884 { 885 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 886 887 request->operation[0].length = 1; 888 request->operation[0].flags = 889 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 890 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 891 request->operation[0].buffer = command; 892 893 request->operation[1].length = 2; 894 request->operation[1].length += pec_check; 895 request->operation[1].flags = read ? 896 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 897 request->operation[1].buffer = data; 898 } 899 900 static void 901 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 902 u8 *command, u8 *data, u8 *data_len, bool read, 903 bool pec_check) 904 { 905 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 906 907 request->operation[0].length = 1; 908 request->operation[0].flags = 909 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 910 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 911 request->operation[0].buffer = command; 912 913 /* 914 * As specified in the standard, the max number of bytes to read/write 915 * per block operation is 32 bytes. In Golan code, the controller can 916 * read up to 128 bytes and write up to 127 bytes. 917 */ 918 request->operation[1].length = 919 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 920 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 921 request->operation[1].flags = read ? 922 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 923 /* 924 * Skip the first data byte, which corresponds to the number of bytes 925 * to read/write. 926 */ 927 request->operation[1].buffer = data + 1; 928 929 *data_len = request->operation[1].length; 930 931 /* Set the number of byte to read. This will be used by userspace. */ 932 if (read) 933 data[0] = *data_len; 934 } 935 936 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 937 u8 *command, u8 *data, u8 *data_len, 938 bool read, bool pec_check) 939 { 940 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 941 942 request->operation[0].length = 1; 943 request->operation[0].flags = 944 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 945 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 946 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 947 request->operation[0].buffer = command; 948 949 request->operation[1].length = 950 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 951 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 952 request->operation[1].flags = read ? 953 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 954 request->operation[1].buffer = data + 1; 955 956 *data_len = request->operation[1].length; 957 958 /* Set the number of bytes to read. This will be used by userspace. */ 959 if (read) 960 data[0] = *data_len; 961 } 962 963 static void 964 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 965 u8 *command, u8 *data, bool pec_check) 966 { 967 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 968 969 request->operation[0].length = 1; 970 request->operation[0].flags = 971 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 972 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 973 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 974 request->operation[0].buffer = command; 975 976 request->operation[1].length = 2; 977 request->operation[1].flags = MLXBF_I2C_F_WRITE; 978 request->operation[1].buffer = data; 979 980 request->operation[2].length = 3; 981 request->operation[2].flags = MLXBF_I2C_F_READ; 982 request->operation[2].buffer = data; 983 } 984 985 static void 986 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 987 u8 *command, u8 *data, u8 *data_len, 988 bool pec_check) 989 { 990 u32 length; 991 992 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 993 994 request->operation[0].length = 1; 995 request->operation[0].flags = 996 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 997 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 998 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 999 request->operation[0].buffer = command; 1000 1001 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 1002 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 1003 1004 request->operation[1].length = length - pec_check; 1005 request->operation[1].flags = MLXBF_I2C_F_WRITE; 1006 request->operation[1].buffer = data; 1007 1008 request->operation[2].length = length; 1009 request->operation[2].flags = MLXBF_I2C_F_READ; 1010 request->operation[2].buffer = data; 1011 1012 *data_len = length; /* including PEC byte. */ 1013 } 1014 1015 /* Initialization functions. */ 1016 1017 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 1018 { 1019 return priv->chip->type == type; 1020 } 1021 1022 static struct mlxbf_i2c_resource * 1023 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 1024 { 1025 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1026 struct mlxbf_i2c_resource *res; 1027 u8 res_idx = 0; 1028 1029 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1030 res = chip->shared_res[res_idx]; 1031 if (res && res->type == type) 1032 return res; 1033 } 1034 1035 return NULL; 1036 } 1037 1038 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1039 struct mlxbf_i2c_resource **res, 1040 u8 type) 1041 { 1042 struct mlxbf_i2c_resource *tmp_res; 1043 struct device *dev = &pdev->dev; 1044 1045 if (!res || *res || type >= MLXBF_I2C_END_RES) 1046 return -EINVAL; 1047 1048 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1049 GFP_KERNEL); 1050 if (!tmp_res) 1051 return -ENOMEM; 1052 1053 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type); 1054 if (!tmp_res->params) { 1055 devm_kfree(dev, tmp_res); 1056 return -EIO; 1057 } 1058 1059 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params); 1060 if (IS_ERR(tmp_res->io)) { 1061 devm_kfree(dev, tmp_res); 1062 return PTR_ERR(tmp_res->io); 1063 } 1064 1065 tmp_res->type = type; 1066 1067 *res = tmp_res; 1068 1069 return 0; 1070 } 1071 1072 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1073 bool minimum) 1074 { 1075 u64 frequency; 1076 u32 ticks; 1077 1078 /* 1079 * Compute ticks as follow: 1080 * 1081 * Ticks 1082 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1083 * Frequency 1084 */ 1085 frequency = priv->frequency; 1086 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1087 /* 1088 * The number of ticks is rounded down and if minimum is equal to 1 1089 * then add one tick. 1090 */ 1091 if (minimum) 1092 ticks++; 1093 1094 return ticks; 1095 } 1096 1097 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1098 u32 mask, u8 shift) 1099 { 1100 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1101 1102 return val; 1103 } 1104 1105 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1106 const struct mlxbf_i2c_timings *timings) 1107 { 1108 u32 timer; 1109 1110 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1111 false, MLXBF_I2C_MASK_16, 1112 MLXBF_I2C_SHIFT_0); 1113 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1114 false, MLXBF_I2C_MASK_16, 1115 MLXBF_I2C_SHIFT_16); 1116 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH, 1117 timer); 1118 1119 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1120 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1121 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1122 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1123 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1124 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1125 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1126 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1127 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE, 1128 timer); 1129 1130 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1131 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1132 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1133 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1134 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_THOLD, timer); 1135 1136 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1137 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1138 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1139 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1140 mlxbf_i2c_write(priv->smbus->io, 1141 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP, timer); 1142 1143 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1144 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1145 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA, 1146 timer); 1147 1148 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1149 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1150 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1151 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1152 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_THIGH_MAX_TBUF, 1153 timer); 1154 1155 timer = timings->timeout; 1156 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT, 1157 timer); 1158 } 1159 1160 enum mlxbf_i2c_timings_config { 1161 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1162 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1163 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1164 }; 1165 1166 /* 1167 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1168 * bus frequency, it is impacted by the time it takes the driver to 1169 * complete data transmission before transaction abort. 1170 */ 1171 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1172 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1173 .scl_high = 4810, 1174 .scl_low = 5000, 1175 .hold_start = 4000, 1176 .setup_start = 4800, 1177 .setup_stop = 4000, 1178 .setup_data = 250, 1179 .sda_rise = 50, 1180 .sda_fall = 50, 1181 .scl_rise = 50, 1182 .scl_fall = 50, 1183 .hold_data = 300, 1184 .buf = 20000, 1185 .thigh_max = 5000, 1186 .timeout = 106500 1187 }, 1188 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1189 .scl_high = 1011, 1190 .scl_low = 1300, 1191 .hold_start = 600, 1192 .setup_start = 700, 1193 .setup_stop = 600, 1194 .setup_data = 100, 1195 .sda_rise = 50, 1196 .sda_fall = 50, 1197 .scl_rise = 50, 1198 .scl_fall = 50, 1199 .hold_data = 300, 1200 .buf = 20000, 1201 .thigh_max = 5000, 1202 .timeout = 106500 1203 }, 1204 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1205 .scl_high = 600, 1206 .scl_low = 1300, 1207 .hold_start = 600, 1208 .setup_start = 600, 1209 .setup_stop = 600, 1210 .setup_data = 100, 1211 .sda_rise = 50, 1212 .sda_fall = 50, 1213 .scl_rise = 50, 1214 .scl_fall = 50, 1215 .hold_data = 300, 1216 .buf = 20000, 1217 .thigh_max = 5000, 1218 .timeout = 106500 1219 } 1220 }; 1221 1222 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1223 struct mlxbf_i2c_priv *priv) 1224 { 1225 enum mlxbf_i2c_timings_config config_idx; 1226 struct device *dev = &pdev->dev; 1227 u32 config_khz; 1228 1229 int ret; 1230 1231 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1232 if (ret < 0) 1233 config_khz = MLXBF_I2C_TIMING_100KHZ; 1234 1235 switch (config_khz) { 1236 default: 1237 /* Default settings is 100 KHz. */ 1238 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1239 config_khz); 1240 fallthrough; 1241 case MLXBF_I2C_TIMING_100KHZ: 1242 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1243 break; 1244 1245 case MLXBF_I2C_TIMING_400KHZ: 1246 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1247 break; 1248 1249 case MLXBF_I2C_TIMING_1000KHZ: 1250 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1251 break; 1252 } 1253 1254 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1255 1256 return 0; 1257 } 1258 1259 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1260 struct mlxbf_i2c_priv *priv) 1261 { 1262 struct mlxbf_i2c_resource *gpio_res; 1263 struct device *dev = &pdev->dev; 1264 struct resource *params; 1265 resource_size_t size; 1266 1267 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1268 if (!gpio_res) 1269 return -EPERM; 1270 1271 /* 1272 * The GPIO region in TYU space is shared among I2C busses. 1273 * This function MUST be serialized to avoid racing when 1274 * claiming the memory region and/or setting up the GPIO. 1275 */ 1276 lockdep_assert_held(gpio_res->lock); 1277 1278 /* Check whether the memory map exist. */ 1279 if (gpio_res->io) 1280 return 0; 1281 1282 params = gpio_res->params; 1283 size = resource_size(params); 1284 1285 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1286 return -EFAULT; 1287 1288 gpio_res->io = devm_ioremap(dev, params->start, size); 1289 if (IS_ERR(gpio_res->io)) { 1290 devm_release_mem_region(dev, params->start, size); 1291 return PTR_ERR(gpio_res->io); 1292 } 1293 1294 return 0; 1295 } 1296 1297 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1298 struct mlxbf_i2c_priv *priv) 1299 { 1300 struct mlxbf_i2c_resource *gpio_res; 1301 struct device *dev = &pdev->dev; 1302 struct resource *params; 1303 1304 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1305 if (!gpio_res) 1306 return 0; 1307 1308 mutex_lock(gpio_res->lock); 1309 1310 if (gpio_res->io) { 1311 /* Release the GPIO resource. */ 1312 params = gpio_res->params; 1313 devm_iounmap(dev, gpio_res->io); 1314 devm_release_mem_region(dev, params->start, 1315 resource_size(params)); 1316 } 1317 1318 mutex_unlock(gpio_res->lock); 1319 1320 return 0; 1321 } 1322 1323 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1324 struct mlxbf_i2c_priv *priv) 1325 { 1326 struct mlxbf_i2c_resource *corepll_res; 1327 struct device *dev = &pdev->dev; 1328 struct resource *params; 1329 resource_size_t size; 1330 1331 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1332 MLXBF_I2C_COREPLL_RES); 1333 if (!corepll_res) 1334 return -EPERM; 1335 1336 /* 1337 * The COREPLL region in TYU space is shared among I2C busses. 1338 * This function MUST be serialized to avoid racing when 1339 * claiming the memory region. 1340 */ 1341 lockdep_assert_held(corepll_res->lock); 1342 1343 /* Check whether the memory map exist. */ 1344 if (corepll_res->io) 1345 return 0; 1346 1347 params = corepll_res->params; 1348 size = resource_size(params); 1349 1350 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1351 return -EFAULT; 1352 1353 corepll_res->io = devm_ioremap(dev, params->start, size); 1354 if (IS_ERR(corepll_res->io)) { 1355 devm_release_mem_region(dev, params->start, size); 1356 return PTR_ERR(corepll_res->io); 1357 } 1358 1359 return 0; 1360 } 1361 1362 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1363 struct mlxbf_i2c_priv *priv) 1364 { 1365 struct mlxbf_i2c_resource *corepll_res; 1366 struct device *dev = &pdev->dev; 1367 struct resource *params; 1368 1369 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1370 MLXBF_I2C_COREPLL_RES); 1371 1372 mutex_lock(corepll_res->lock); 1373 1374 if (corepll_res->io) { 1375 /* Release the CorePLL resource. */ 1376 params = corepll_res->params; 1377 devm_iounmap(dev, corepll_res->io); 1378 devm_release_mem_region(dev, params->start, 1379 resource_size(params)); 1380 } 1381 1382 mutex_unlock(corepll_res->lock); 1383 1384 return 0; 1385 } 1386 1387 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1388 struct mlxbf_i2c_priv *priv) 1389 { 1390 struct mlxbf_i2c_resource *gpio_res; 1391 struct device *dev = &pdev->dev; 1392 u32 config_reg; 1393 int ret; 1394 1395 /* This configuration is only needed for BlueField 1. */ 1396 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1397 return 0; 1398 1399 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1400 if (!gpio_res) 1401 return -EPERM; 1402 1403 /* 1404 * The GPIO region in TYU space is shared among I2C busses. 1405 * This function MUST be serialized to avoid racing when 1406 * claiming the memory region and/or setting up the GPIO. 1407 */ 1408 1409 mutex_lock(gpio_res->lock); 1410 1411 ret = mlxbf_i2c_get_gpio(pdev, priv); 1412 if (ret < 0) { 1413 dev_err(dev, "Failed to get gpio resource"); 1414 mutex_unlock(gpio_res->lock); 1415 return ret; 1416 } 1417 1418 /* 1419 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1420 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1421 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1422 * instead of HW_OE. 1423 * For now, we do not reset the GPIO state when the driver is removed. 1424 * First, it is not necessary to disable the bus since we are using 1425 * the same busses. Then, some busses might be shared among Linux and 1426 * platform firmware; disabling the bus might compromise the system 1427 * functionality. 1428 */ 1429 config_reg = mlxbf_i2c_read(gpio_res->io, 1430 MLXBF_I2C_GPIO_0_FUNC_EN_0); 1431 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1432 config_reg); 1433 mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FUNC_EN_0, 1434 config_reg); 1435 1436 config_reg = mlxbf_i2c_read(gpio_res->io, 1437 MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1438 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1439 config_reg); 1440 mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FORCE_OE_EN, 1441 config_reg); 1442 1443 mutex_unlock(gpio_res->lock); 1444 1445 return 0; 1446 } 1447 1448 static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1449 { 1450 u64 core_frequency, pad_frequency; 1451 u8 core_od, core_r; 1452 u32 corepll_val; 1453 u16 core_f; 1454 1455 pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ; 1456 1457 corepll_val = mlxbf_i2c_read(corepll_res->io, 1458 MLXBF_I2C_CORE_PLL_REG1); 1459 1460 /* Get Core PLL configuration bits. */ 1461 core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) & 1462 MLXBF_I2C_COREPLL_CORE_F_TYU_MASK; 1463 core_od = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT) & 1464 MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK; 1465 core_r = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT) & 1466 MLXBF_I2C_COREPLL_CORE_R_TYU_MASK; 1467 1468 /* 1469 * Compute PLL output frequency as follow: 1470 * 1471 * CORE_F + 1 1472 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1473 * (CORE_R + 1) * (CORE_OD + 1) 1474 * 1475 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1476 * and PadFrequency, respectively. 1477 */ 1478 core_frequency = pad_frequency * (++core_f); 1479 core_frequency /= (++core_r) * (++core_od); 1480 1481 return core_frequency; 1482 } 1483 1484 static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1485 { 1486 u32 corepll_reg1_val, corepll_reg2_val; 1487 u64 corepll_frequency, pad_frequency; 1488 u8 core_od, core_r; 1489 u32 core_f; 1490 1491 pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ; 1492 1493 corepll_reg1_val = mlxbf_i2c_read(corepll_res->io, 1494 MLXBF_I2C_CORE_PLL_REG1); 1495 corepll_reg2_val = mlxbf_i2c_read(corepll_res->io, 1496 MLXBF_I2C_CORE_PLL_REG2); 1497 1498 /* Get Core PLL configuration bits */ 1499 core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) & 1500 MLXBF_I2C_COREPLL_CORE_F_YU_MASK; 1501 core_r = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT) & 1502 MLXBF_I2C_COREPLL_CORE_R_YU_MASK; 1503 core_od = rol32(corepll_reg2_val, MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT) & 1504 MLXBF_I2C_COREPLL_CORE_OD_YU_MASK; 1505 1506 /* 1507 * Compute PLL output frequency as follow: 1508 * 1509 * CORE_F / 16384 1510 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1511 * (CORE_R + 1) * (CORE_OD + 1) 1512 * 1513 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1514 * and PadFrequency, respectively. 1515 */ 1516 corepll_frequency = (pad_frequency * core_f) / MLNXBF_I2C_COREPLL_CONST; 1517 corepll_frequency /= (++core_r) * (++core_od); 1518 1519 return corepll_frequency; 1520 } 1521 1522 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1523 struct mlxbf_i2c_priv *priv) 1524 { 1525 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1526 struct mlxbf_i2c_resource *corepll_res; 1527 struct device *dev = &pdev->dev; 1528 u64 *freq = &priv->frequency; 1529 int ret; 1530 1531 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1532 MLXBF_I2C_COREPLL_RES); 1533 if (!corepll_res) 1534 return -EPERM; 1535 1536 /* 1537 * First, check whether the TYU core Clock frequency is set. 1538 * The TYU core frequency is the same for all I2C busses; when 1539 * the first device gets probed the frequency is determined and 1540 * stored into a globally visible variable. So, first of all, 1541 * check whether the frequency is already set. Here, we assume 1542 * that the frequency is expected to be greater than 0. 1543 */ 1544 mutex_lock(corepll_res->lock); 1545 if (!mlxbf_i2c_corepll_frequency) { 1546 if (!chip->calculate_freq) { 1547 mutex_unlock(corepll_res->lock); 1548 return -EPERM; 1549 } 1550 1551 ret = mlxbf_i2c_get_corepll(pdev, priv); 1552 if (ret < 0) { 1553 dev_err(dev, "Failed to get corePLL resource"); 1554 mutex_unlock(corepll_res->lock); 1555 return ret; 1556 } 1557 1558 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1559 } 1560 mutex_unlock(corepll_res->lock); 1561 1562 *freq = mlxbf_i2c_corepll_frequency; 1563 1564 return 0; 1565 } 1566 1567 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) 1568 { 1569 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; 1570 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; 1571 bool avail, disabled; 1572 1573 disabled = false; 1574 avail = false; 1575 1576 if (!priv) 1577 return -EPERM; 1578 1579 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1580 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1581 1582 /* 1583 * Read the slave registers. There are 4 * 32-bit slave registers. 1584 * Each slave register can hold up to 4 * 8-bit slave configuration 1585 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1586 */ 1587 for (reg = 0; reg < reg_cnt; reg++) { 1588 slave_reg = mlxbf_i2c_read(priv->smbus->io, 1589 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1590 /* 1591 * Each register holds 4 slave addresses. So, we have to keep 1592 * the byte order consistent with the value read in order to 1593 * update the register correctly, if needed. 1594 */ 1595 slave_reg_tmp = slave_reg; 1596 for (byte = 0; byte < 4; byte++) { 1597 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1598 1599 /* 1600 * Mark the first available slave address slot, i.e. its 1601 * enabled bit should be unset. This slot might be used 1602 * later on to register our slave. 1603 */ 1604 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { 1605 avail = true; 1606 reg_avail = reg; 1607 byte_avail = byte; 1608 slave_reg_avail = slave_reg; 1609 } 1610 1611 /* 1612 * Parse slave address bytes and check whether the 1613 * slave address already exists and it's enabled, 1614 * i.e. most significant bit is set. 1615 */ 1616 if ((addr_tmp & slave_addr_mask) == addr) { 1617 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) 1618 return 0; 1619 disabled = true; 1620 break; 1621 } 1622 1623 /* Parse next byte. */ 1624 slave_reg_tmp >>= 8; 1625 } 1626 1627 /* Exit the loop if the slave address is found. */ 1628 if (disabled) 1629 break; 1630 } 1631 1632 if (!avail && !disabled) 1633 return -EINVAL; /* No room for a new slave address. */ 1634 1635 if (avail && !disabled) { 1636 reg = reg_avail; 1637 byte = byte_avail; 1638 /* Set the slave address. */ 1639 slave_reg_avail &= ~(slave_addr_mask << (byte * 8)); 1640 slave_reg_avail |= addr << (byte * 8); 1641 slave_reg = slave_reg_avail; 1642 } 1643 1644 /* Enable the slave address and update the register. */ 1645 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1646 mlxbf_i2c_write(priv->smbus->io, 1647 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg); 1648 1649 return 0; 1650 } 1651 1652 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) 1653 { 1654 u32 slave_reg, slave_reg_tmp, slave_addr_mask; 1655 u8 addr, addr_tmp, reg, reg_cnt, slave_byte; 1656 struct i2c_client *client = priv->slave; 1657 bool exist; 1658 1659 exist = false; 1660 1661 addr = client->addr; 1662 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1663 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1664 1665 /* 1666 * Read the slave registers. There are 4 * 32-bit slave registers. 1667 * Each slave register can hold up to 4 * 8-bit slave configuration 1668 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1669 */ 1670 for (reg = 0; reg < reg_cnt; reg++) { 1671 slave_reg = mlxbf_i2c_read(priv->smbus->io, 1672 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1673 1674 /* Check whether the address slots are empty. */ 1675 if (slave_reg == 0) 1676 continue; 1677 1678 /* 1679 * Each register holds 4 slave addresses. So, we have to keep 1680 * the byte order consistent with the value read in order to 1681 * update the register correctly, if needed. 1682 */ 1683 slave_reg_tmp = slave_reg; 1684 slave_byte = 0; 1685 while (slave_reg_tmp != 0) { 1686 addr_tmp = slave_reg_tmp & slave_addr_mask; 1687 /* 1688 * Parse slave address bytes and check whether the 1689 * slave address already exists. 1690 */ 1691 if (addr_tmp == addr) { 1692 exist = true; 1693 break; 1694 } 1695 1696 /* Parse next byte. */ 1697 slave_reg_tmp >>= 8; 1698 slave_byte += 1; 1699 } 1700 1701 /* Exit the loop if the slave address is found. */ 1702 if (exist) 1703 break; 1704 } 1705 1706 if (!exist) 1707 return 0; /* Slave is not registered, nothing to do. */ 1708 1709 /* Cleanup the slave address slot. */ 1710 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1711 mlxbf_i2c_write(priv->smbus->io, 1712 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg); 1713 1714 return 0; 1715 } 1716 1717 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1718 struct mlxbf_i2c_priv *priv) 1719 { 1720 struct mlxbf_i2c_resource *coalesce_res; 1721 struct resource *params; 1722 resource_size_t size; 1723 int ret = 0; 1724 1725 /* 1726 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1727 * resource in the next generations of BlueField. 1728 */ 1729 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1730 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1731 MLXBF_I2C_COALESCE_RES); 1732 if (!coalesce_res) 1733 return -EPERM; 1734 1735 /* 1736 * The Cause Coalesce group in TYU space is shared among 1737 * I2C busses. This function MUST be serialized to avoid 1738 * racing when claiming the memory region. 1739 */ 1740 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1741 1742 /* Check whether the memory map exist. */ 1743 if (coalesce_res->io) { 1744 priv->coalesce = coalesce_res; 1745 return 0; 1746 } 1747 1748 params = coalesce_res->params; 1749 size = resource_size(params); 1750 1751 if (!request_mem_region(params->start, size, params->name)) 1752 return -EFAULT; 1753 1754 coalesce_res->io = ioremap(params->start, size); 1755 if (IS_ERR(coalesce_res->io)) { 1756 release_mem_region(params->start, size); 1757 return PTR_ERR(coalesce_res->io); 1758 } 1759 1760 priv->coalesce = coalesce_res; 1761 1762 } else { 1763 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1764 MLXBF_I2C_COALESCE_RES); 1765 } 1766 1767 return ret; 1768 } 1769 1770 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1771 struct mlxbf_i2c_priv *priv) 1772 { 1773 struct mlxbf_i2c_resource *coalesce_res; 1774 struct device *dev = &pdev->dev; 1775 struct resource *params; 1776 resource_size_t size; 1777 1778 coalesce_res = priv->coalesce; 1779 1780 if (coalesce_res->io) { 1781 params = coalesce_res->params; 1782 size = resource_size(params); 1783 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1784 mutex_lock(coalesce_res->lock); 1785 iounmap(coalesce_res->io); 1786 release_mem_region(params->start, size); 1787 mutex_unlock(coalesce_res->lock); 1788 } else { 1789 devm_release_mem_region(dev, params->start, size); 1790 } 1791 } 1792 1793 return 0; 1794 } 1795 1796 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1797 struct mlxbf_i2c_priv *priv) 1798 { 1799 struct device *dev = &pdev->dev; 1800 u32 int_reg; 1801 int ret; 1802 1803 /* Reset FSM. */ 1804 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_FSM, 0); 1805 1806 /* 1807 * Enable slave cause interrupt bits. Drive 1808 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1809 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1810 * masters issue a Read and Write, respectively. But, clear all 1811 * interrupts first. 1812 */ 1813 mlxbf_i2c_write(priv->slv_cause->io, 1814 MLXBF_I2C_CAUSE_OR_CLEAR, ~0); 1815 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1816 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1817 mlxbf_i2c_write(priv->slv_cause->io, 1818 MLXBF_I2C_CAUSE_OR_EVTEN0, int_reg); 1819 1820 /* Finally, set the 'ready' bit to start handling transactions. */ 1821 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 1822 1823 /* Initialize the cause coalesce resource. */ 1824 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1825 if (ret < 0) { 1826 dev_err(dev, "failed to initialize cause coalesce\n"); 1827 return ret; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1834 bool *write) 1835 { 1836 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1837 u32 coalesce0_reg, cause_reg; 1838 u8 slave_shift, is_set; 1839 1840 *write = false; 1841 *read = false; 1842 1843 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1844 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1845 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1846 1847 coalesce0_reg = mlxbf_i2c_read(priv->coalesce->io, 1848 MLXBF_I2C_CAUSE_COALESCE_0); 1849 is_set = coalesce0_reg & (1 << slave_shift); 1850 1851 if (!is_set) 1852 return false; 1853 1854 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1855 cause_reg = mlxbf_i2c_read(priv->slv_cause->io, 1856 MLXBF_I2C_CAUSE_ARBITER); 1857 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1858 *read = true; 1859 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1860 *write = true; 1861 1862 /* Clear cause bits. */ 1863 mlxbf_i2c_write(priv->slv_cause->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0); 1864 1865 return true; 1866 } 1867 1868 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, 1869 u32 timeout) 1870 { 1871 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL; 1872 u32 addr = MLXBF_I2C_CAUSE_ARBITER; 1873 1874 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout)) 1875 return true; 1876 1877 return false; 1878 } 1879 1880 /* Send byte to 'external' smbus master. */ 1881 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1882 { 1883 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1884 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size; 1885 struct i2c_client *slave = priv->slave; 1886 u32 control32, data32; 1887 int ret; 1888 1889 if (!slave) 1890 return -EINVAL; 1891 1892 addr = 0; 1893 byte = 0; 1894 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; 1895 1896 /* 1897 * Read bytes received from the external master. These bytes should 1898 * be located in the first data descriptor register of the slave GW. 1899 * These bytes are the slave address byte and the internal register 1900 * address, if supplied. 1901 */ 1902 if (recv_bytes > 0) { 1903 data32 = mlxbf_i2c_read_data(priv->smbus->io, 1904 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1905 1906 /* Parse the received bytes. */ 1907 switch (recv_bytes) { 1908 case 2: 1909 byte = (data32 >> 8) & GENMASK(7, 0); 1910 fallthrough; 1911 case 1: 1912 addr = (data32 & GENMASK(7, 0)) >> 1; 1913 } 1914 1915 /* Check whether it's our slave address. */ 1916 if (slave->addr != addr) 1917 return -EINVAL; 1918 } 1919 1920 /* 1921 * I2C read transactions may start by a WRITE followed by a READ. 1922 * Indeed, most slave devices would expect the internal address 1923 * following the slave address byte. So, write that byte first, 1924 * and then, send the requested data bytes to the master. 1925 */ 1926 if (recv_bytes > 1) { 1927 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1928 value = byte; 1929 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1930 &value); 1931 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1932 1933 if (ret < 0) 1934 return ret; 1935 } 1936 1937 /* 1938 * Now, send data to the master; currently, the driver supports 1939 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the 1940 * hardware can send up to 128 bytes per transfer. That is the 1941 * size of its data registers. 1942 */ 1943 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1944 1945 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { 1946 data_desc[byte_cnt] = value; 1947 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1948 } 1949 1950 /* Send a stop condition to the backend. */ 1951 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1952 1953 /* Handle the actual transfer. */ 1954 1955 /* Set the number of bytes to write to master. */ 1956 write_size = (byte_cnt - 1) & 0x7f; 1957 1958 /* Write data to Slave GW data descriptor. */ 1959 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1960 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1961 1962 pec_en = 0; /* Disable PEC since it is not supported. */ 1963 1964 /* Prepare control word. */ 1965 control32 = MLXBF_I2C_SLAVE_ENABLE; 1966 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1967 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1968 1969 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_GW, control32); 1970 1971 /* 1972 * Wait until the transfer is completed; the driver will wait 1973 * until the GW is idle, a cause will rise on fall of GW busy. 1974 */ 1975 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1976 1977 /* Release the Slave GW. */ 1978 mlxbf_i2c_write(priv->smbus->io, 1979 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0); 1980 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0); 1981 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 1982 1983 return 0; 1984 } 1985 1986 /* Receive bytes from 'external' smbus master. */ 1987 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1988 { 1989 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1990 struct i2c_client *slave = priv->slave; 1991 u8 value, byte, addr; 1992 int ret = 0; 1993 1994 if (!slave) 1995 return -EINVAL; 1996 1997 /* Read data from Slave GW data descriptor. */ 1998 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1999 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 2000 2001 /* Check whether its our slave address. */ 2002 addr = data_desc[0] >> 1; 2003 if (slave->addr != addr) 2004 return -EINVAL; 2005 2006 /* 2007 * Notify the slave backend; another I2C master wants to write data 2008 * to us. This event is sent once the slave address and the write bit 2009 * is detected. 2010 */ 2011 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 2012 2013 /* Send the received data to the slave backend. */ 2014 for (byte = 1; byte < recv_bytes; byte++) { 2015 value = data_desc[byte]; 2016 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 2017 &value); 2018 if (ret < 0) 2019 break; 2020 } 2021 2022 /* Send a stop condition to the backend. */ 2023 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 2024 2025 /* Release the Slave GW. */ 2026 mlxbf_i2c_write(priv->smbus->io, 2027 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0); 2028 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0); 2029 mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 2030 2031 return ret; 2032 } 2033 2034 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) 2035 { 2036 struct mlxbf_i2c_priv *priv = ptr; 2037 bool read, write, irq_is_set; 2038 u32 rw_bytes_reg; 2039 u8 recv_bytes; 2040 2041 /* 2042 * Read TYU interrupt register and determine the source of the 2043 * interrupt. Based on the source of the interrupt one of the 2044 * following actions are performed: 2045 * - Receive data and send response to master. 2046 * - Send data and release slave GW. 2047 * 2048 * Handle read/write transaction only. CRmaster and Iarp requests 2049 * are ignored for now. 2050 */ 2051 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 2052 if (!irq_is_set || (!read && !write)) { 2053 /* Nothing to do here, interrupt was not from this device. */ 2054 return IRQ_NONE; 2055 } 2056 2057 /* 2058 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 2059 * bytes from/to master. These are defined by 8-bits each. If the lower 2060 * 8 bits are set, then the master expect to read N bytes from the 2061 * slave, if the higher 8 bits are sent then the slave expect N bytes 2062 * from the master. 2063 */ 2064 rw_bytes_reg = mlxbf_i2c_read(priv->smbus->io, 2065 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2066 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2067 2068 /* 2069 * For now, the slave supports 128 bytes transfer. Discard remaining 2070 * data bytes if the master wrote more than 2071 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2072 * data descriptor. 2073 * 2074 * Note that we will never expect to transfer more than 128 bytes; as 2075 * specified in the SMBus standard, block transactions cannot exceed 2076 * 32 bytes. 2077 */ 2078 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2079 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2080 2081 if (read) 2082 mlxbf_smbus_irq_send(priv, recv_bytes); 2083 else 2084 mlxbf_smbus_irq_recv(priv, recv_bytes); 2085 2086 return IRQ_HANDLED; 2087 } 2088 2089 /* Return negative errno on error. */ 2090 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2091 unsigned short flags, char read_write, 2092 u8 command, int size, 2093 union i2c_smbus_data *data) 2094 { 2095 struct mlxbf_i2c_smbus_request request = { 0 }; 2096 struct mlxbf_i2c_priv *priv; 2097 bool read, pec; 2098 u8 byte_cnt; 2099 2100 request.slave = addr; 2101 2102 read = (read_write == I2C_SMBUS_READ); 2103 pec = flags & I2C_FUNC_SMBUS_PEC; 2104 2105 switch (size) { 2106 case I2C_SMBUS_QUICK: 2107 mlxbf_i2c_smbus_quick_command(&request, read); 2108 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2109 break; 2110 2111 case I2C_SMBUS_BYTE: 2112 mlxbf_i2c_smbus_byte_func(&request, 2113 read ? &data->byte : &command, read, 2114 pec); 2115 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2116 read ? "read" : "write", addr); 2117 break; 2118 2119 case I2C_SMBUS_BYTE_DATA: 2120 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2121 read, pec); 2122 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2123 read ? "read" : "write", command, addr); 2124 break; 2125 2126 case I2C_SMBUS_WORD_DATA: 2127 mlxbf_i2c_smbus_data_word_func(&request, &command, 2128 (u8 *)&data->word, read, pec); 2129 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2130 read ? "read" : "write", command, addr); 2131 break; 2132 2133 case I2C_SMBUS_I2C_BLOCK_DATA: 2134 byte_cnt = data->block[0]; 2135 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2136 &byte_cnt, read, pec); 2137 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2138 read ? "read" : "write", byte_cnt, command, addr); 2139 break; 2140 2141 case I2C_SMBUS_BLOCK_DATA: 2142 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2143 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2144 &byte_cnt, read, pec); 2145 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2146 read ? "read" : "write", byte_cnt, command, addr); 2147 break; 2148 2149 case I2C_FUNC_SMBUS_PROC_CALL: 2150 mlxbf_i2c_smbus_process_call_func(&request, &command, 2151 (u8 *)&data->word, pec); 2152 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2153 command, addr); 2154 break; 2155 2156 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2157 byte_cnt = data->block[0]; 2158 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2159 data->block, &byte_cnt, 2160 pec); 2161 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2162 byte_cnt, addr); 2163 break; 2164 2165 default: 2166 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2167 size); 2168 return -EOPNOTSUPP; 2169 } 2170 2171 priv = i2c_get_adapdata(adap); 2172 2173 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2174 } 2175 2176 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2177 { 2178 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2179 int ret; 2180 2181 if (priv->slave) 2182 return -EBUSY; 2183 2184 /* 2185 * Do not support ten bit chip address and do not use Packet Error 2186 * Checking (PEC). 2187 */ 2188 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) 2189 return -EAFNOSUPPORT; 2190 2191 ret = mlxbf_slave_enable(priv, slave->addr); 2192 if (ret < 0) 2193 return ret; 2194 2195 priv->slave = slave; 2196 2197 return 0; 2198 } 2199 2200 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2201 { 2202 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2203 int ret; 2204 2205 WARN_ON(!priv->slave); 2206 2207 /* Unregister slave, i.e. disable the slave address in hardware. */ 2208 ret = mlxbf_slave_disable(priv); 2209 if (ret < 0) 2210 return ret; 2211 2212 priv->slave = NULL; 2213 2214 return 0; 2215 } 2216 2217 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2218 { 2219 return MLXBF_I2C_FUNC_ALL; 2220 } 2221 2222 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2223 [MLXBF_I2C_CHIP_TYPE_1] = { 2224 .type = MLXBF_I2C_CHIP_TYPE_1, 2225 .shared_res = { 2226 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2227 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2228 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2229 }, 2230 .calculate_freq = mlxbf_calculate_freq_from_tyu 2231 }, 2232 [MLXBF_I2C_CHIP_TYPE_2] = { 2233 .type = MLXBF_I2C_CHIP_TYPE_2, 2234 .shared_res = { 2235 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2236 }, 2237 .calculate_freq = mlxbf_calculate_freq_from_yu 2238 } 2239 }; 2240 2241 static const struct i2c_algorithm mlxbf_i2c_algo = { 2242 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2243 .functionality = mlxbf_i2c_functionality, 2244 .reg_slave = mlxbf_i2c_reg_slave, 2245 .unreg_slave = mlxbf_i2c_unreg_slave, 2246 }; 2247 2248 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2249 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2250 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2251 }; 2252 2253 static const struct of_device_id mlxbf_i2c_dt_ids[] = { 2254 { 2255 .compatible = "mellanox,i2c-mlxbf1", 2256 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] 2257 }, 2258 { 2259 .compatible = "mellanox,i2c-mlxbf2", 2260 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] 2261 }, 2262 {}, 2263 }; 2264 2265 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2266 2267 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2268 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2269 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2270 {}, 2271 }; 2272 2273 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2274 2275 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2276 { 2277 const struct acpi_device_id *aid; 2278 struct acpi_device *adev; 2279 unsigned long bus_id = 0; 2280 const char *uid; 2281 int ret; 2282 2283 if (acpi_disabled) 2284 return -ENOENT; 2285 2286 adev = ACPI_COMPANION(dev); 2287 if (!adev) 2288 return -ENXIO; 2289 2290 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2291 if (!aid) 2292 return -ENODEV; 2293 2294 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2295 2296 uid = acpi_device_uid(adev); 2297 if (!uid || !(*uid)) { 2298 dev_err(dev, "Cannot retrieve UID\n"); 2299 return -ENODEV; 2300 } 2301 2302 ret = kstrtoul(uid, 0, &bus_id); 2303 if (!ret) 2304 priv->bus = bus_id; 2305 2306 return ret; 2307 } 2308 2309 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2310 { 2311 const struct of_device_id *oid; 2312 int bus_id = -1; 2313 2314 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 2315 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node); 2316 if (!oid) 2317 return -ENODEV; 2318 2319 priv->chip = oid->data; 2320 2321 bus_id = of_alias_get_id(dev->of_node, "i2c"); 2322 if (bus_id >= 0) 2323 priv->bus = bus_id; 2324 } 2325 2326 if (bus_id < 0) { 2327 dev_err(dev, "Cannot get bus id"); 2328 return bus_id; 2329 } 2330 2331 return 0; 2332 } 2333 2334 static int mlxbf_i2c_probe(struct platform_device *pdev) 2335 { 2336 struct device *dev = &pdev->dev; 2337 struct mlxbf_i2c_priv *priv; 2338 struct i2c_adapter *adap; 2339 int irq, ret; 2340 2341 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2342 if (!priv) 2343 return -ENOMEM; 2344 2345 ret = mlxbf_i2c_acpi_probe(dev, priv); 2346 if (ret < 0 && ret != -ENOENT && ret != -ENXIO) 2347 ret = mlxbf_i2c_of_probe(dev, priv); 2348 2349 if (ret < 0) 2350 return ret; 2351 2352 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2353 MLXBF_I2C_SMBUS_RES); 2354 if (ret < 0) { 2355 dev_err(dev, "Cannot fetch smbus resource info"); 2356 return ret; 2357 } 2358 2359 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2360 MLXBF_I2C_MST_CAUSE_RES); 2361 if (ret < 0) { 2362 dev_err(dev, "Cannot fetch cause master resource info"); 2363 return ret; 2364 } 2365 2366 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2367 MLXBF_I2C_SLV_CAUSE_RES); 2368 if (ret < 0) { 2369 dev_err(dev, "Cannot fetch cause slave resource info"); 2370 return ret; 2371 } 2372 2373 adap = &priv->adap; 2374 adap->owner = THIS_MODULE; 2375 adap->class = I2C_CLASS_HWMON; 2376 adap->algo = &mlxbf_i2c_algo; 2377 adap->quirks = &mlxbf_i2c_quirks; 2378 adap->dev.parent = dev; 2379 adap->dev.of_node = dev->of_node; 2380 adap->nr = priv->bus; 2381 2382 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2383 i2c_set_adapdata(adap, priv); 2384 2385 /* Read Core PLL frequency. */ 2386 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2387 if (ret < 0) { 2388 dev_err(dev, "cannot get core clock frequency\n"); 2389 /* Set to default value. */ 2390 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2391 } 2392 2393 /* 2394 * Initialize master. 2395 * Note that a physical bus might be shared among Linux and firmware 2396 * (e.g., ATF). Thus, the bus should be initialized and ready and 2397 * bus initialization would be unnecessary. This requires additional 2398 * knowledge about physical busses. But, since an extra initialization 2399 * does not really hurt, then keep the code as is. 2400 */ 2401 ret = mlxbf_i2c_init_master(pdev, priv); 2402 if (ret < 0) { 2403 dev_err(dev, "failed to initialize smbus master %d", 2404 priv->bus); 2405 return ret; 2406 } 2407 2408 mlxbf_i2c_init_timings(pdev, priv); 2409 2410 mlxbf_i2c_init_slave(pdev, priv); 2411 2412 irq = platform_get_irq(pdev, 0); 2413 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2414 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2415 dev_name(dev), priv); 2416 if (ret < 0) { 2417 dev_err(dev, "Cannot get irq %d\n", irq); 2418 return ret; 2419 } 2420 2421 priv->irq = irq; 2422 2423 platform_set_drvdata(pdev, priv); 2424 2425 ret = i2c_add_numbered_adapter(adap); 2426 if (ret < 0) 2427 return ret; 2428 2429 mutex_lock(&mlxbf_i2c_bus_lock); 2430 mlxbf_i2c_bus_count++; 2431 mutex_unlock(&mlxbf_i2c_bus_lock); 2432 2433 return 0; 2434 } 2435 2436 static int mlxbf_i2c_remove(struct platform_device *pdev) 2437 { 2438 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2439 struct device *dev = &pdev->dev; 2440 struct resource *params; 2441 2442 params = priv->smbus->params; 2443 devm_release_mem_region(dev, params->start, resource_size(params)); 2444 2445 params = priv->mst_cause->params; 2446 devm_release_mem_region(dev, params->start, resource_size(params)); 2447 2448 params = priv->slv_cause->params; 2449 devm_release_mem_region(dev, params->start, resource_size(params)); 2450 2451 /* 2452 * Release shared resources. This should be done when releasing 2453 * the I2C controller. 2454 */ 2455 mutex_lock(&mlxbf_i2c_bus_lock); 2456 if (--mlxbf_i2c_bus_count == 0) { 2457 mlxbf_i2c_release_coalesce(pdev, priv); 2458 mlxbf_i2c_release_corepll(pdev, priv); 2459 mlxbf_i2c_release_gpio(pdev, priv); 2460 } 2461 mutex_unlock(&mlxbf_i2c_bus_lock); 2462 2463 devm_free_irq(dev, priv->irq, priv); 2464 2465 i2c_del_adapter(&priv->adap); 2466 2467 return 0; 2468 } 2469 2470 static struct platform_driver mlxbf_i2c_driver = { 2471 .probe = mlxbf_i2c_probe, 2472 .remove = mlxbf_i2c_remove, 2473 .driver = { 2474 .name = "i2c-mlxbf", 2475 .of_match_table = mlxbf_i2c_dt_ids, 2476 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2477 }, 2478 }; 2479 2480 static int __init mlxbf_i2c_init(void) 2481 { 2482 mutex_init(&mlxbf_i2c_coalesce_lock); 2483 mutex_init(&mlxbf_i2c_corepll_lock); 2484 mutex_init(&mlxbf_i2c_gpio_lock); 2485 2486 mutex_init(&mlxbf_i2c_bus_lock); 2487 2488 return platform_driver_register(&mlxbf_i2c_driver); 2489 } 2490 module_init(mlxbf_i2c_init); 2491 2492 static void __exit mlxbf_i2c_exit(void) 2493 { 2494 platform_driver_unregister(&mlxbf_i2c_driver); 2495 2496 mutex_destroy(&mlxbf_i2c_bus_lock); 2497 2498 mutex_destroy(&mlxbf_i2c_gpio_lock); 2499 mutex_destroy(&mlxbf_i2c_corepll_lock); 2500 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2501 } 2502 module_exit(mlxbf_i2c_exit); 2503 2504 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2505 MODULE_AUTHOR("Khalil Blaiech <kblaiech@mellanox.com>"); 2506 MODULE_LICENSE("GPL v2"); 2507