1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/i2c.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/string.h> 20 21 /* Defines what functionality is present. */ 22 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 23 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 24 25 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 26 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 27 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 28 I2C_FUNC_SMBUS_PROC_CALL) 29 30 #define MLXBF_I2C_FUNC_ALL \ 31 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 32 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 33 34 #define MLXBF_I2C_SMBUS_MAX 3 35 36 /* Shared resources info in BlueField platforms. */ 37 38 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 39 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 40 41 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 42 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 43 44 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 45 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 46 47 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 48 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 49 50 #define MLXBF_I2C_SHARED_RES_MAX 3 51 52 /* 53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 54 * refer to their respective offsets relative to the corresponding 55 * memory-mapped region whose addresses are specified in either the DT or 56 * the ACPI tables or above. 57 */ 58 59 /* 60 * SMBus Master core clock frequency. Timing configurations are 61 * strongly dependent on the core clock frequency of the SMBus 62 * Master. Default value is set to 400MHz. 63 */ 64 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 65 /* Reference clock for Bluefield - 156 MHz. */ 66 #define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000) 67 68 /* Constant used to determine the PLL frequency. */ 69 #define MLNXBF_I2C_COREPLL_CONST 16384 70 71 /* PLL registers. */ 72 #define MLXBF_I2C_CORE_PLL_REG0 0x0 73 #define MLXBF_I2C_CORE_PLL_REG1 0x4 74 #define MLXBF_I2C_CORE_PLL_REG2 0x8 75 76 /* OR cause register. */ 77 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 78 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 79 80 /* Arbiter Cause Register. */ 81 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 82 83 /* 84 * Cause Status flags. Note that those bits might be considered 85 * as interrupt enabled bits. 86 */ 87 88 /* Transaction ended with STOP. */ 89 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 90 /* Master arbitration lost. */ 91 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 92 /* Unexpected start detected. */ 93 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 94 /* Unexpected stop detected. */ 95 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 96 /* Wait for transfer continuation. */ 97 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 98 /* Failed to generate STOP. */ 99 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 100 /* Failed to generate START. */ 101 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 102 /* Clock toggle completed. */ 103 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 104 /* Transfer timeout occurred. */ 105 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 106 /* Master busy bit reset. */ 107 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 108 109 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 110 111 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 112 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 113 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 114 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 115 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 116 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 117 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 118 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 119 120 /* 121 * Slave cause status flags. Note that those bits might be considered 122 * as interrupt enabled bits. 123 */ 124 125 /* Write transaction received successfully. */ 126 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 127 /* Read transaction received, waiting for response. */ 128 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 129 /* Slave busy bit reset. */ 130 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 131 132 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0) 133 134 /* Cause coalesce registers. */ 135 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 136 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04 137 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08 138 139 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX 140 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 141 142 /* Functional enable register. */ 143 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 144 /* Force OE enable register. */ 145 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 146 /* 147 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 148 * SDA/SCL lines: 149 * 150 * SMBUS GW0 -> bits[26:25] 151 * SMBUS GW1 -> bits[28:27] 152 * SMBUS GW2 -> bits[30:29] 153 */ 154 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 155 156 /* Note that gw_id can be 0,1 or 2. */ 157 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 158 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 159 160 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 161 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 162 163 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 164 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 165 166 /* SMBus timing parameters. */ 167 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 168 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 169 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 170 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 171 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 172 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 173 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 174 175 enum { 176 MLXBF_I2C_TIMING_100KHZ = 100000, 177 MLXBF_I2C_TIMING_400KHZ = 400000, 178 MLXBF_I2C_TIMING_1000KHZ = 1000000, 179 }; 180 181 /* 182 * Defines SMBus operating frequency and core clock frequency. 183 * According to ADB files, default values are compliant to 100KHz SMBus 184 * @ 400MHz core clock. The driver should be able to calculate core 185 * frequency based on PLL parameters. 186 */ 187 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 188 189 /* Core PLL TYU configuration. */ 190 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(12, 0) 191 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(3, 0) 192 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(5, 0) 193 194 #define MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT 3 195 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT 16 196 #define MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT 20 197 198 /* Core PLL YU configuration. */ 199 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 200 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 201 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(5, 0) 202 203 #define MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT 0 204 #define MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT 1 205 #define MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT 26 206 207 /* Core PLL frequency. */ 208 static u64 mlxbf_i2c_corepll_frequency; 209 210 /* SMBus Master GW. */ 211 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200 212 /* Number of bytes received and sent. */ 213 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300 214 /* Packet error check (PEC) value. */ 215 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304 216 /* Status bits (ACK/NACK/FW Timeout). */ 217 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308 218 /* SMbus Master Finite State Machine. */ 219 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310 220 221 /* 222 * When enabled, the master will issue a stop condition in case of 223 * timeout while waiting for FW response. 224 */ 225 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c 226 227 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 228 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 229 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 230 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 231 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 232 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 233 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 234 235 #define MLXBF_I2C_MASTER_ENABLE \ 236 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 237 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 238 239 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 240 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 241 242 #define MLXBF_I2C_MASTER_ENABLE_READ \ 243 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 244 245 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */ 246 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */ 247 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */ 248 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */ 249 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */ 250 251 /* SMBus master GW Data descriptor. */ 252 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280 253 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 254 255 /* Maximum bytes to read/write per SMBus transaction. */ 256 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 257 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 258 259 /* All bytes were transmitted. */ 260 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 261 /* NACK received. */ 262 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 263 /* Slave's byte count >128 bytes. */ 264 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 265 /* Timeout occurred. */ 266 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 267 268 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 269 270 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 271 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 272 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 273 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 274 275 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 276 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 277 278 /* SMBus slave GW. */ 279 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400 280 /* Number of bytes received and sent from/to master. */ 281 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500 282 /* Packet error check (PEC) value. */ 283 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504 284 /* SMBus slave Finite State Machine (FSM). */ 285 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510 286 /* 287 * Should be set when all raised causes handled, and cleared by HW on 288 * every new cause. 289 */ 290 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c 291 292 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 293 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 294 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 295 296 #define MLXBF_I2C_SLAVE_ENABLE \ 297 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 298 299 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 300 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 301 302 /* SMBus slave GW Data descriptor. */ 303 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480 304 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 305 306 /* SMbus slave configuration registers. */ 307 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514 308 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 309 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 310 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 311 312 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \ 313 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) 314 315 /* 316 * Timeout is given in microsends. Note also that timeout handling is not 317 * exact. 318 */ 319 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 320 321 /* Encapsulates timing parameters. */ 322 struct mlxbf_i2c_timings { 323 u16 scl_high; /* Clock high period. */ 324 u16 scl_low; /* Clock low period. */ 325 u8 sda_rise; /* Data rise time. */ 326 u8 sda_fall; /* Data fall time. */ 327 u8 scl_rise; /* Clock rise time. */ 328 u8 scl_fall; /* Clock fall time. */ 329 u16 hold_start; /* Hold time after (REPEATED) START. */ 330 u16 hold_data; /* Data hold time. */ 331 u16 setup_start; /* REPEATED START condition setup time. */ 332 u16 setup_stop; /* STOP condition setup time. */ 333 u16 setup_data; /* Data setup time. */ 334 u16 pad; /* Padding. */ 335 u16 buf; /* Bus free time between STOP and START. */ 336 u16 thigh_max; /* Thigh max. */ 337 u32 timeout; /* Detect clock low timeout. */ 338 }; 339 340 enum { 341 MLXBF_I2C_F_READ = BIT(0), 342 MLXBF_I2C_F_WRITE = BIT(1), 343 MLXBF_I2C_F_NORESTART = BIT(3), 344 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 345 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 346 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 347 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 348 }; 349 350 struct mlxbf_i2c_smbus_operation { 351 u32 flags; 352 u32 length; /* Buffer length in bytes. */ 353 u8 *buffer; 354 }; 355 356 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 357 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 358 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 359 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 360 361 struct mlxbf_i2c_smbus_request { 362 u8 slave; 363 u8 operation_cnt; 364 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 365 }; 366 367 struct mlxbf_i2c_resource { 368 void __iomem *io; 369 struct resource *params; 370 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 371 u8 type; 372 }; 373 374 /* List of chip resources that are being accessed by the driver. */ 375 enum { 376 MLXBF_I2C_SMBUS_RES, 377 MLXBF_I2C_MST_CAUSE_RES, 378 MLXBF_I2C_SLV_CAUSE_RES, 379 MLXBF_I2C_COALESCE_RES, 380 MLXBF_I2C_COREPLL_RES, 381 MLXBF_I2C_GPIO_RES, 382 MLXBF_I2C_END_RES, 383 }; 384 385 /* Helper macro to define an I2C resource parameters. */ 386 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 387 { \ 388 .start = (addr), \ 389 .end = (addr) + (size) - 1, \ 390 .name = (str) \ 391 } 392 393 static struct resource mlxbf_i2c_coalesce_tyu_params = 394 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 395 MLXBF_I2C_COALESCE_TYU_SIZE, 396 "COALESCE_MEM"); 397 static struct resource mlxbf_i2c_corepll_tyu_params = 398 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 399 MLXBF_I2C_COREPLL_TYU_SIZE, 400 "COREPLL_MEM"); 401 static struct resource mlxbf_i2c_corepll_yu_params = 402 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 403 MLXBF_I2C_COREPLL_YU_SIZE, 404 "COREPLL_MEM"); 405 static struct resource mlxbf_i2c_gpio_tyu_params = 406 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 407 MLXBF_I2C_GPIO_TYU_SIZE, 408 "GPIO_MEM"); 409 410 static struct mutex mlxbf_i2c_coalesce_lock; 411 static struct mutex mlxbf_i2c_corepll_lock; 412 static struct mutex mlxbf_i2c_gpio_lock; 413 414 /* Mellanox BlueField chip type. */ 415 enum mlxbf_i2c_chip_type { 416 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 417 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */ 418 }; 419 420 struct mlxbf_i2c_chip_info { 421 enum mlxbf_i2c_chip_type type; 422 /* Chip shared resources that are being used by the I2C controller. */ 423 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 424 425 /* Callback to calculate the core PLL frequency. */ 426 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 427 }; 428 429 struct mlxbf_i2c_priv { 430 const struct mlxbf_i2c_chip_info *chip; 431 struct i2c_adapter adap; 432 struct mlxbf_i2c_resource *smbus; 433 struct mlxbf_i2c_resource *mst_cause; 434 struct mlxbf_i2c_resource *slv_cause; 435 struct mlxbf_i2c_resource *coalesce; 436 u64 frequency; /* Core frequency in Hz. */ 437 int bus; /* Physical bus identifier. */ 438 int irq; 439 struct i2c_client *slave; 440 }; 441 442 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 443 [MLXBF_I2C_CHIP_TYPE_1] = { 444 .params = &mlxbf_i2c_coalesce_tyu_params, 445 .lock = &mlxbf_i2c_coalesce_lock, 446 .type = MLXBF_I2C_COALESCE_RES 447 }, 448 {} 449 }; 450 451 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 452 [MLXBF_I2C_CHIP_TYPE_1] = { 453 .params = &mlxbf_i2c_corepll_tyu_params, 454 .lock = &mlxbf_i2c_corepll_lock, 455 .type = MLXBF_I2C_COREPLL_RES 456 }, 457 [MLXBF_I2C_CHIP_TYPE_2] = { 458 .params = &mlxbf_i2c_corepll_yu_params, 459 .lock = &mlxbf_i2c_corepll_lock, 460 .type = MLXBF_I2C_COREPLL_RES, 461 } 462 }; 463 464 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 465 [MLXBF_I2C_CHIP_TYPE_1] = { 466 .params = &mlxbf_i2c_gpio_tyu_params, 467 .lock = &mlxbf_i2c_gpio_lock, 468 .type = MLXBF_I2C_GPIO_RES 469 }, 470 {} 471 }; 472 473 static u8 mlxbf_i2c_bus_count; 474 475 static struct mutex mlxbf_i2c_bus_lock; 476 477 /* Polling frequency in microseconds. */ 478 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 479 480 #define MLXBF_I2C_SHIFT_0 0 481 #define MLXBF_I2C_SHIFT_8 8 482 #define MLXBF_I2C_SHIFT_16 16 483 #define MLXBF_I2C_SHIFT_24 24 484 485 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 486 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 487 488 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000 489 490 /* 491 * Function to poll a set of bits at a specific address; it checks whether 492 * the bits are equal to zero when eq_zero is set to 'true', and not equal 493 * to zero when eq_zero is set to 'false'. 494 * Note that the timeout is given in microseconds. 495 */ 496 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask, 497 bool eq_zero, u32 timeout) 498 { 499 u32 bits; 500 501 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 502 503 do { 504 bits = readl(io + addr) & mask; 505 if (eq_zero ? bits == 0 : bits != 0) 506 return eq_zero ? 1 : bits; 507 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); 508 } while (timeout-- != 0); 509 510 return 0; 511 } 512 513 /* 514 * SW must make sure that the SMBus Master GW is idle before starting 515 * a transaction. Accordingly, this function polls the Master FSM stop 516 * bit; it returns false when the bit is asserted, true if not. 517 */ 518 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) 519 { 520 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK; 521 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM; 522 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT; 523 524 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout)) 525 return true; 526 527 return false; 528 } 529 530 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 531 u32 cause_status) 532 { 533 /* 534 * When transaction ended with STOP, all bytes were transmitted, 535 * and no NACK received, then the transaction ended successfully. 536 * On the other hand, when the GW is configured with the stop bit 537 * de-asserted then the SMBus expects the following GW configuration 538 * for transfer continuation. 539 */ 540 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 541 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 542 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 543 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 544 return true; 545 546 return false; 547 } 548 549 /* 550 * Poll SMBus master status and return transaction status, 551 * i.e. whether succeeded or failed. I2C and SMBus fault codes 552 * are returned as negative numbers from most calls, with zero 553 * or some positive number indicating a non-fault return. 554 */ 555 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 556 { 557 u32 master_status_bits; 558 u32 cause_status_bits; 559 560 /* 561 * GW busy bit is raised by the driver and cleared by the HW 562 * when the transaction is completed. The busy bit is a good 563 * indicator of transaction status. So poll the busy bit, and 564 * then read the cause and master status bits to determine if 565 * errors occurred during the transaction. 566 */ 567 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 568 MLXBF_I2C_MASTER_BUSY_BIT, true, 569 MLXBF_I2C_SMBUS_TIMEOUT); 570 571 /* Read cause status bits. */ 572 cause_status_bits = readl(priv->mst_cause->io + 573 MLXBF_I2C_CAUSE_ARBITER); 574 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 575 576 /* 577 * Parse both Cause and Master GW bits, then return transaction status. 578 */ 579 580 master_status_bits = readl(priv->smbus->io + 581 MLXBF_I2C_SMBUS_MASTER_STATUS); 582 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 583 584 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 585 cause_status_bits)) 586 return 0; 587 588 /* 589 * In case of timeout on GW busy, the ISR will clear busy bit but 590 * transaction ended bits cause will not be set so the transaction 591 * fails. Then, we must check Master GW status bits. 592 */ 593 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 594 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 595 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 596 return -EIO; 597 598 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 599 return -EAGAIN; 600 601 return -ETIMEDOUT; 602 } 603 604 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 605 const u8 *data, u8 length, u32 addr) 606 { 607 u8 offset, aligned_length; 608 u32 data32; 609 610 aligned_length = round_up(length, 4); 611 612 /* 613 * Copy data bytes from 4-byte aligned source buffer. 614 * Data copied to the Master GW Data Descriptor MUST be shifted 615 * left so the data starts at the MSB of the descriptor registers 616 * as required by the underlying hardware. Enable byte swapping 617 * when writing data bytes to the 32 * 32-bit HW Data registers 618 * a.k.a Master GW Data Descriptor. 619 */ 620 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 621 data32 = *((u32 *)(data + offset)); 622 iowrite32be(data32, priv->smbus->io + addr + offset); 623 } 624 } 625 626 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 627 u8 *data, u8 length, u32 addr) 628 { 629 u32 data32, mask; 630 u8 byte, offset; 631 632 mask = sizeof(u32) - 1; 633 634 /* 635 * Data bytes in the Master GW Data Descriptor are shifted left 636 * so the data starts at the MSB of the descriptor registers as 637 * set by the underlying hardware. Enable byte swapping while 638 * reading data bytes from the 32 * 32-bit HW Data registers 639 * a.k.a Master GW Data Descriptor. 640 */ 641 642 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 643 data32 = ioread32be(priv->smbus->io + addr + offset); 644 *((u32 *)(data + offset)) = data32; 645 } 646 647 if (!(length & mask)) 648 return; 649 650 data32 = ioread32be(priv->smbus->io + addr + offset); 651 652 for (byte = 0; byte < (length & mask); byte++) { 653 data[offset + byte] = data32 & GENMASK(7, 0); 654 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 655 } 656 } 657 658 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 659 u8 len, u8 block_en, u8 pec_en, bool read) 660 { 661 u32 command; 662 663 /* Set Master GW control word. */ 664 if (read) { 665 command = MLXBF_I2C_MASTER_ENABLE_READ; 666 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 667 } else { 668 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 669 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 670 } 671 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 672 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 673 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 674 675 /* Clear status bits. */ 676 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 677 /* Set the cause data. */ 678 writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR); 679 /* Zero PEC byte. */ 680 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC); 681 /* Zero byte count. */ 682 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES); 683 684 /* GW activation. */ 685 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 686 687 /* 688 * Poll master status and check status bits. An ACK is sent when 689 * completing writing data to the bus (Master 'byte_count_done' bit 690 * is set to 1). 691 */ 692 return mlxbf_i2c_smbus_check_status(priv); 693 } 694 695 static int 696 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 697 struct mlxbf_i2c_smbus_request *request) 698 { 699 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 700 u8 op_idx, data_idx, data_len, write_len, read_len; 701 struct mlxbf_i2c_smbus_operation *operation; 702 u8 read_en, write_en, block_en, pec_en; 703 u8 slave, flags, addr; 704 u8 *read_buf; 705 int ret = 0; 706 707 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 708 return -EINVAL; 709 710 read_buf = NULL; 711 data_idx = 0; 712 read_en = 0; 713 write_en = 0; 714 write_len = 0; 715 read_len = 0; 716 block_en = 0; 717 pec_en = 0; 718 slave = request->slave & GENMASK(6, 0); 719 addr = slave << 1; 720 721 /* First of all, check whether the HW is idle. */ 722 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) 723 return -EBUSY; 724 725 /* Set first byte. */ 726 data_desc[data_idx++] = addr; 727 728 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 729 operation = &request->operation[op_idx]; 730 flags = operation->flags; 731 732 /* 733 * Note that read and write operations might be handled by a 734 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 735 * then write command byte and set the optional SMBus specific 736 * bits such as block_en and pec_en. These bits MUST be 737 * submitted by the first operation only. 738 */ 739 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 740 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 741 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 742 } 743 744 if (flags & MLXBF_I2C_F_WRITE) { 745 write_en = 1; 746 write_len += operation->length; 747 memcpy(data_desc + data_idx, 748 operation->buffer, operation->length); 749 data_idx += operation->length; 750 } 751 /* 752 * We assume that read operations are performed only once per 753 * SMBus transaction. *TBD* protect this statement so it won't 754 * be executed twice? or return an error if we try to read more 755 * than once? 756 */ 757 if (flags & MLXBF_I2C_F_READ) { 758 read_en = 1; 759 /* Subtract 1 as required by HW. */ 760 read_len = operation->length - 1; 761 read_buf = operation->buffer; 762 } 763 } 764 765 /* Set Master GW data descriptor. */ 766 data_len = write_len + 1; /* Add one byte of the slave address. */ 767 /* 768 * Note that data_len cannot be 0. Indeed, the slave address byte 769 * must be written to the data registers. 770 */ 771 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 772 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 773 774 if (write_en) { 775 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 776 pec_en, 0); 777 if (ret) 778 return ret; 779 } 780 781 if (read_en) { 782 /* Write slave address to Master GW data descriptor. */ 783 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 784 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 785 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 786 pec_en, 1); 787 if (!ret) { 788 /* Get Master GW data descriptor. */ 789 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 790 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 791 792 /* Get data from Master GW data descriptor. */ 793 memcpy(read_buf, data_desc, read_len + 1); 794 } 795 796 /* 797 * After a read operation the SMBus FSM ps (present state) 798 * needs to be 'manually' reset. This should be removed in 799 * next tag integration. 800 */ 801 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 802 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); 803 } 804 805 return ret; 806 } 807 808 /* I2C SMBus protocols. */ 809 810 static void 811 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 812 u8 read) 813 { 814 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 815 816 request->operation[0].length = 0; 817 request->operation[0].flags = MLXBF_I2C_F_WRITE; 818 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 819 } 820 821 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 822 u8 *data, bool read, bool pec_check) 823 { 824 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 825 826 request->operation[0].length = 1; 827 request->operation[0].length += pec_check; 828 829 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 830 request->operation[0].flags |= read ? 831 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 832 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 833 834 request->operation[0].buffer = data; 835 } 836 837 static void 838 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 839 u8 *command, u8 *data, bool read, bool pec_check) 840 { 841 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 842 843 request->operation[0].length = 1; 844 request->operation[0].flags = 845 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 846 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 847 request->operation[0].buffer = command; 848 849 request->operation[1].length = 1; 850 request->operation[1].length += pec_check; 851 request->operation[1].flags = read ? 852 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 853 request->operation[1].buffer = data; 854 } 855 856 static void 857 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 858 u8 *command, u8 *data, bool read, bool pec_check) 859 { 860 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 861 862 request->operation[0].length = 1; 863 request->operation[0].flags = 864 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 865 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 866 request->operation[0].buffer = command; 867 868 request->operation[1].length = 2; 869 request->operation[1].length += pec_check; 870 request->operation[1].flags = read ? 871 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 872 request->operation[1].buffer = data; 873 } 874 875 static void 876 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 877 u8 *command, u8 *data, u8 *data_len, bool read, 878 bool pec_check) 879 { 880 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 881 882 request->operation[0].length = 1; 883 request->operation[0].flags = 884 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 885 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 886 request->operation[0].buffer = command; 887 888 /* 889 * As specified in the standard, the max number of bytes to read/write 890 * per block operation is 32 bytes. In Golan code, the controller can 891 * read up to 128 bytes and write up to 127 bytes. 892 */ 893 request->operation[1].length = 894 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 895 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 896 request->operation[1].flags = read ? 897 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 898 /* 899 * Skip the first data byte, which corresponds to the number of bytes 900 * to read/write. 901 */ 902 request->operation[1].buffer = data + 1; 903 904 *data_len = request->operation[1].length; 905 906 /* Set the number of byte to read. This will be used by userspace. */ 907 if (read) 908 data[0] = *data_len; 909 } 910 911 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 912 u8 *command, u8 *data, u8 *data_len, 913 bool read, bool pec_check) 914 { 915 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 916 917 request->operation[0].length = 1; 918 request->operation[0].flags = 919 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 920 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 921 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 922 request->operation[0].buffer = command; 923 924 request->operation[1].length = 925 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 926 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 927 request->operation[1].flags = read ? 928 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 929 request->operation[1].buffer = data + 1; 930 931 *data_len = request->operation[1].length; 932 933 /* Set the number of bytes to read. This will be used by userspace. */ 934 if (read) 935 data[0] = *data_len; 936 } 937 938 static void 939 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 940 u8 *command, u8 *data, bool pec_check) 941 { 942 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 943 944 request->operation[0].length = 1; 945 request->operation[0].flags = 946 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 947 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 948 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 949 request->operation[0].buffer = command; 950 951 request->operation[1].length = 2; 952 request->operation[1].flags = MLXBF_I2C_F_WRITE; 953 request->operation[1].buffer = data; 954 955 request->operation[2].length = 3; 956 request->operation[2].flags = MLXBF_I2C_F_READ; 957 request->operation[2].buffer = data; 958 } 959 960 static void 961 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 962 u8 *command, u8 *data, u8 *data_len, 963 bool pec_check) 964 { 965 u32 length; 966 967 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 968 969 request->operation[0].length = 1; 970 request->operation[0].flags = 971 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 972 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 973 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 974 request->operation[0].buffer = command; 975 976 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 977 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 978 979 request->operation[1].length = length - pec_check; 980 request->operation[1].flags = MLXBF_I2C_F_WRITE; 981 request->operation[1].buffer = data; 982 983 request->operation[2].length = length; 984 request->operation[2].flags = MLXBF_I2C_F_READ; 985 request->operation[2].buffer = data; 986 987 *data_len = length; /* including PEC byte. */ 988 } 989 990 /* Initialization functions. */ 991 992 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 993 { 994 return priv->chip->type == type; 995 } 996 997 static struct mlxbf_i2c_resource * 998 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 999 { 1000 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1001 struct mlxbf_i2c_resource *res; 1002 u8 res_idx = 0; 1003 1004 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1005 res = chip->shared_res[res_idx]; 1006 if (res && res->type == type) 1007 return res; 1008 } 1009 1010 return NULL; 1011 } 1012 1013 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1014 struct mlxbf_i2c_resource **res, 1015 u8 type) 1016 { 1017 struct mlxbf_i2c_resource *tmp_res; 1018 struct device *dev = &pdev->dev; 1019 1020 if (!res || *res || type >= MLXBF_I2C_END_RES) 1021 return -EINVAL; 1022 1023 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1024 GFP_KERNEL); 1025 if (!tmp_res) 1026 return -ENOMEM; 1027 1028 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type); 1029 if (!tmp_res->params) { 1030 devm_kfree(dev, tmp_res); 1031 return -EIO; 1032 } 1033 1034 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params); 1035 if (IS_ERR(tmp_res->io)) { 1036 devm_kfree(dev, tmp_res); 1037 return PTR_ERR(tmp_res->io); 1038 } 1039 1040 tmp_res->type = type; 1041 1042 *res = tmp_res; 1043 1044 return 0; 1045 } 1046 1047 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1048 bool minimum) 1049 { 1050 u64 frequency; 1051 u32 ticks; 1052 1053 /* 1054 * Compute ticks as follow: 1055 * 1056 * Ticks 1057 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1058 * Frequency 1059 */ 1060 frequency = priv->frequency; 1061 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1062 /* 1063 * The number of ticks is rounded down and if minimum is equal to 1 1064 * then add one tick. 1065 */ 1066 if (minimum) 1067 ticks++; 1068 1069 return ticks; 1070 } 1071 1072 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1073 u32 mask, u8 shift) 1074 { 1075 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1076 1077 return val; 1078 } 1079 1080 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1081 const struct mlxbf_i2c_timings *timings) 1082 { 1083 u32 timer; 1084 1085 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1086 false, MLXBF_I2C_MASK_16, 1087 MLXBF_I2C_SHIFT_0); 1088 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1089 false, MLXBF_I2C_MASK_16, 1090 MLXBF_I2C_SHIFT_16); 1091 writel(timer, priv->smbus->io + 1092 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1093 1094 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1095 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1096 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1097 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1098 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1099 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1100 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1101 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1102 writel(timer, priv->smbus->io + 1103 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1104 1105 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1106 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1107 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1108 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1109 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1110 1111 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1112 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1113 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1114 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1115 writel(timer, priv->smbus->io + 1116 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1117 1118 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1119 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1120 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1121 1122 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1123 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1124 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1125 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1126 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1127 1128 timer = timings->timeout; 1129 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1130 } 1131 1132 enum mlxbf_i2c_timings_config { 1133 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1134 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1135 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1136 }; 1137 1138 /* 1139 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1140 * bus frequency, it is impacted by the time it takes the driver to 1141 * complete data transmission before transaction abort. 1142 */ 1143 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1144 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1145 .scl_high = 4810, 1146 .scl_low = 5000, 1147 .hold_start = 4000, 1148 .setup_start = 4800, 1149 .setup_stop = 4000, 1150 .setup_data = 250, 1151 .sda_rise = 50, 1152 .sda_fall = 50, 1153 .scl_rise = 50, 1154 .scl_fall = 50, 1155 .hold_data = 300, 1156 .buf = 20000, 1157 .thigh_max = 5000, 1158 .timeout = 106500 1159 }, 1160 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1161 .scl_high = 1011, 1162 .scl_low = 1300, 1163 .hold_start = 600, 1164 .setup_start = 700, 1165 .setup_stop = 600, 1166 .setup_data = 100, 1167 .sda_rise = 50, 1168 .sda_fall = 50, 1169 .scl_rise = 50, 1170 .scl_fall = 50, 1171 .hold_data = 300, 1172 .buf = 20000, 1173 .thigh_max = 5000, 1174 .timeout = 106500 1175 }, 1176 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1177 .scl_high = 600, 1178 .scl_low = 1300, 1179 .hold_start = 600, 1180 .setup_start = 600, 1181 .setup_stop = 600, 1182 .setup_data = 100, 1183 .sda_rise = 50, 1184 .sda_fall = 50, 1185 .scl_rise = 50, 1186 .scl_fall = 50, 1187 .hold_data = 300, 1188 .buf = 20000, 1189 .thigh_max = 5000, 1190 .timeout = 106500 1191 } 1192 }; 1193 1194 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1195 struct mlxbf_i2c_priv *priv) 1196 { 1197 enum mlxbf_i2c_timings_config config_idx; 1198 struct device *dev = &pdev->dev; 1199 u32 config_khz; 1200 1201 int ret; 1202 1203 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1204 if (ret < 0) 1205 config_khz = MLXBF_I2C_TIMING_100KHZ; 1206 1207 switch (config_khz) { 1208 default: 1209 /* Default settings is 100 KHz. */ 1210 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1211 config_khz); 1212 fallthrough; 1213 case MLXBF_I2C_TIMING_100KHZ: 1214 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1215 break; 1216 1217 case MLXBF_I2C_TIMING_400KHZ: 1218 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1219 break; 1220 1221 case MLXBF_I2C_TIMING_1000KHZ: 1222 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1223 break; 1224 } 1225 1226 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1227 1228 return 0; 1229 } 1230 1231 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1232 struct mlxbf_i2c_priv *priv) 1233 { 1234 struct mlxbf_i2c_resource *gpio_res; 1235 struct device *dev = &pdev->dev; 1236 struct resource *params; 1237 resource_size_t size; 1238 1239 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1240 if (!gpio_res) 1241 return -EPERM; 1242 1243 /* 1244 * The GPIO region in TYU space is shared among I2C busses. 1245 * This function MUST be serialized to avoid racing when 1246 * claiming the memory region and/or setting up the GPIO. 1247 */ 1248 lockdep_assert_held(gpio_res->lock); 1249 1250 /* Check whether the memory map exist. */ 1251 if (gpio_res->io) 1252 return 0; 1253 1254 params = gpio_res->params; 1255 size = resource_size(params); 1256 1257 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1258 return -EFAULT; 1259 1260 gpio_res->io = devm_ioremap(dev, params->start, size); 1261 if (IS_ERR(gpio_res->io)) { 1262 devm_release_mem_region(dev, params->start, size); 1263 return PTR_ERR(gpio_res->io); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1270 struct mlxbf_i2c_priv *priv) 1271 { 1272 struct mlxbf_i2c_resource *gpio_res; 1273 struct device *dev = &pdev->dev; 1274 struct resource *params; 1275 1276 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1277 if (!gpio_res) 1278 return 0; 1279 1280 mutex_lock(gpio_res->lock); 1281 1282 if (gpio_res->io) { 1283 /* Release the GPIO resource. */ 1284 params = gpio_res->params; 1285 devm_iounmap(dev, gpio_res->io); 1286 devm_release_mem_region(dev, params->start, 1287 resource_size(params)); 1288 } 1289 1290 mutex_unlock(gpio_res->lock); 1291 1292 return 0; 1293 } 1294 1295 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1296 struct mlxbf_i2c_priv *priv) 1297 { 1298 struct mlxbf_i2c_resource *corepll_res; 1299 struct device *dev = &pdev->dev; 1300 struct resource *params; 1301 resource_size_t size; 1302 1303 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1304 MLXBF_I2C_COREPLL_RES); 1305 if (!corepll_res) 1306 return -EPERM; 1307 1308 /* 1309 * The COREPLL region in TYU space is shared among I2C busses. 1310 * This function MUST be serialized to avoid racing when 1311 * claiming the memory region. 1312 */ 1313 lockdep_assert_held(corepll_res->lock); 1314 1315 /* Check whether the memory map exist. */ 1316 if (corepll_res->io) 1317 return 0; 1318 1319 params = corepll_res->params; 1320 size = resource_size(params); 1321 1322 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1323 return -EFAULT; 1324 1325 corepll_res->io = devm_ioremap(dev, params->start, size); 1326 if (IS_ERR(corepll_res->io)) { 1327 devm_release_mem_region(dev, params->start, size); 1328 return PTR_ERR(corepll_res->io); 1329 } 1330 1331 return 0; 1332 } 1333 1334 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1335 struct mlxbf_i2c_priv *priv) 1336 { 1337 struct mlxbf_i2c_resource *corepll_res; 1338 struct device *dev = &pdev->dev; 1339 struct resource *params; 1340 1341 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1342 MLXBF_I2C_COREPLL_RES); 1343 1344 mutex_lock(corepll_res->lock); 1345 1346 if (corepll_res->io) { 1347 /* Release the CorePLL resource. */ 1348 params = corepll_res->params; 1349 devm_iounmap(dev, corepll_res->io); 1350 devm_release_mem_region(dev, params->start, 1351 resource_size(params)); 1352 } 1353 1354 mutex_unlock(corepll_res->lock); 1355 1356 return 0; 1357 } 1358 1359 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1360 struct mlxbf_i2c_priv *priv) 1361 { 1362 struct mlxbf_i2c_resource *gpio_res; 1363 struct device *dev = &pdev->dev; 1364 u32 config_reg; 1365 int ret; 1366 1367 /* This configuration is only needed for BlueField 1. */ 1368 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1369 return 0; 1370 1371 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1372 if (!gpio_res) 1373 return -EPERM; 1374 1375 /* 1376 * The GPIO region in TYU space is shared among I2C busses. 1377 * This function MUST be serialized to avoid racing when 1378 * claiming the memory region and/or setting up the GPIO. 1379 */ 1380 1381 mutex_lock(gpio_res->lock); 1382 1383 ret = mlxbf_i2c_get_gpio(pdev, priv); 1384 if (ret < 0) { 1385 dev_err(dev, "Failed to get gpio resource"); 1386 mutex_unlock(gpio_res->lock); 1387 return ret; 1388 } 1389 1390 /* 1391 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1392 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1393 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1394 * instead of HW_OE. 1395 * For now, we do not reset the GPIO state when the driver is removed. 1396 * First, it is not necessary to disable the bus since we are using 1397 * the same busses. Then, some busses might be shared among Linux and 1398 * platform firmware; disabling the bus might compromise the system 1399 * functionality. 1400 */ 1401 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1402 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1403 config_reg); 1404 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1405 1406 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1407 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1408 config_reg); 1409 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1410 1411 mutex_unlock(gpio_res->lock); 1412 1413 return 0; 1414 } 1415 1416 static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1417 { 1418 u64 core_frequency, pad_frequency; 1419 u8 core_od, core_r; 1420 u32 corepll_val; 1421 u16 core_f; 1422 1423 pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1424 1425 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1426 1427 /* Get Core PLL configuration bits. */ 1428 core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) & 1429 MLXBF_I2C_COREPLL_CORE_F_TYU_MASK; 1430 core_od = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT) & 1431 MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK; 1432 core_r = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT) & 1433 MLXBF_I2C_COREPLL_CORE_R_TYU_MASK; 1434 1435 /* 1436 * Compute PLL output frequency as follow: 1437 * 1438 * CORE_F + 1 1439 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1440 * (CORE_R + 1) * (CORE_OD + 1) 1441 * 1442 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1443 * and PadFrequency, respectively. 1444 */ 1445 core_frequency = pad_frequency * (++core_f); 1446 core_frequency /= (++core_r) * (++core_od); 1447 1448 return core_frequency; 1449 } 1450 1451 static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1452 { 1453 u32 corepll_reg1_val, corepll_reg2_val; 1454 u64 corepll_frequency, pad_frequency; 1455 u8 core_od, core_r; 1456 u32 core_f; 1457 1458 pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1459 1460 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1461 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1462 1463 /* Get Core PLL configuration bits */ 1464 core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) & 1465 MLXBF_I2C_COREPLL_CORE_F_YU_MASK; 1466 core_r = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT) & 1467 MLXBF_I2C_COREPLL_CORE_R_YU_MASK; 1468 core_od = rol32(corepll_reg2_val, MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT) & 1469 MLXBF_I2C_COREPLL_CORE_OD_YU_MASK; 1470 1471 /* 1472 * Compute PLL output frequency as follow: 1473 * 1474 * CORE_F / 16384 1475 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1476 * (CORE_R + 1) * (CORE_OD + 1) 1477 * 1478 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1479 * and PadFrequency, respectively. 1480 */ 1481 corepll_frequency = (pad_frequency * core_f) / MLNXBF_I2C_COREPLL_CONST; 1482 corepll_frequency /= (++core_r) * (++core_od); 1483 1484 return corepll_frequency; 1485 } 1486 1487 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1488 struct mlxbf_i2c_priv *priv) 1489 { 1490 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1491 struct mlxbf_i2c_resource *corepll_res; 1492 struct device *dev = &pdev->dev; 1493 u64 *freq = &priv->frequency; 1494 int ret; 1495 1496 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1497 MLXBF_I2C_COREPLL_RES); 1498 if (!corepll_res) 1499 return -EPERM; 1500 1501 /* 1502 * First, check whether the TYU core Clock frequency is set. 1503 * The TYU core frequency is the same for all I2C busses; when 1504 * the first device gets probed the frequency is determined and 1505 * stored into a globally visible variable. So, first of all, 1506 * check whether the frequency is already set. Here, we assume 1507 * that the frequency is expected to be greater than 0. 1508 */ 1509 mutex_lock(corepll_res->lock); 1510 if (!mlxbf_i2c_corepll_frequency) { 1511 if (!chip->calculate_freq) { 1512 mutex_unlock(corepll_res->lock); 1513 return -EPERM; 1514 } 1515 1516 ret = mlxbf_i2c_get_corepll(pdev, priv); 1517 if (ret < 0) { 1518 dev_err(dev, "Failed to get corePLL resource"); 1519 mutex_unlock(corepll_res->lock); 1520 return ret; 1521 } 1522 1523 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1524 } 1525 mutex_unlock(corepll_res->lock); 1526 1527 *freq = mlxbf_i2c_corepll_frequency; 1528 1529 return 0; 1530 } 1531 1532 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) 1533 { 1534 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; 1535 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; 1536 bool avail, disabled; 1537 1538 disabled = false; 1539 avail = false; 1540 1541 if (!priv) 1542 return -EPERM; 1543 1544 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1545 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1546 1547 /* 1548 * Read the slave registers. There are 4 * 32-bit slave registers. 1549 * Each slave register can hold up to 4 * 8-bit slave configuration 1550 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1551 */ 1552 for (reg = 0; reg < reg_cnt; reg++) { 1553 slave_reg = readl(priv->smbus->io + 1554 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1555 /* 1556 * Each register holds 4 slave addresses. So, we have to keep 1557 * the byte order consistent with the value read in order to 1558 * update the register correctly, if needed. 1559 */ 1560 slave_reg_tmp = slave_reg; 1561 for (byte = 0; byte < 4; byte++) { 1562 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1563 1564 /* 1565 * Mark the first available slave address slot, i.e. its 1566 * enabled bit should be unset. This slot might be used 1567 * later on to register our slave. 1568 */ 1569 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { 1570 avail = true; 1571 reg_avail = reg; 1572 byte_avail = byte; 1573 slave_reg_avail = slave_reg; 1574 } 1575 1576 /* 1577 * Parse slave address bytes and check whether the 1578 * slave address already exists and it's enabled, 1579 * i.e. most significant bit is set. 1580 */ 1581 if ((addr_tmp & slave_addr_mask) == addr) { 1582 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) 1583 return 0; 1584 disabled = true; 1585 break; 1586 } 1587 1588 /* Parse next byte. */ 1589 slave_reg_tmp >>= 8; 1590 } 1591 1592 /* Exit the loop if the slave address is found. */ 1593 if (disabled) 1594 break; 1595 } 1596 1597 if (!avail && !disabled) 1598 return -EINVAL; /* No room for a new slave address. */ 1599 1600 if (avail && !disabled) { 1601 reg = reg_avail; 1602 byte = byte_avail; 1603 /* Set the slave address. */ 1604 slave_reg_avail &= ~(slave_addr_mask << (byte * 8)); 1605 slave_reg_avail |= addr << (byte * 8); 1606 slave_reg = slave_reg_avail; 1607 } 1608 1609 /* Enable the slave address and update the register. */ 1610 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1611 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1612 reg * 0x4); 1613 1614 return 0; 1615 } 1616 1617 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) 1618 { 1619 u32 slave_reg, slave_reg_tmp, slave_addr_mask; 1620 u8 addr, addr_tmp, reg, reg_cnt, slave_byte; 1621 struct i2c_client *client = priv->slave; 1622 bool exist; 1623 1624 exist = false; 1625 1626 addr = client->addr; 1627 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1628 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1629 1630 /* 1631 * Read the slave registers. There are 4 * 32-bit slave registers. 1632 * Each slave register can hold up to 4 * 8-bit slave configuration 1633 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1634 */ 1635 for (reg = 0; reg < reg_cnt; reg++) { 1636 slave_reg = readl(priv->smbus->io + 1637 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1638 1639 /* Check whether the address slots are empty. */ 1640 if (slave_reg == 0) 1641 continue; 1642 1643 /* 1644 * Each register holds 4 slave addresses. So, we have to keep 1645 * the byte order consistent with the value read in order to 1646 * update the register correctly, if needed. 1647 */ 1648 slave_reg_tmp = slave_reg; 1649 slave_byte = 0; 1650 while (slave_reg_tmp != 0) { 1651 addr_tmp = slave_reg_tmp & slave_addr_mask; 1652 /* 1653 * Parse slave address bytes and check whether the 1654 * slave address already exists. 1655 */ 1656 if (addr_tmp == addr) { 1657 exist = true; 1658 break; 1659 } 1660 1661 /* Parse next byte. */ 1662 slave_reg_tmp >>= 8; 1663 slave_byte += 1; 1664 } 1665 1666 /* Exit the loop if the slave address is found. */ 1667 if (exist) 1668 break; 1669 } 1670 1671 if (!exist) 1672 return 0; /* Slave is not registered, nothing to do. */ 1673 1674 /* Cleanup the slave address slot. */ 1675 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1676 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1677 reg * 0x4); 1678 1679 return 0; 1680 } 1681 1682 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1683 struct mlxbf_i2c_priv *priv) 1684 { 1685 struct mlxbf_i2c_resource *coalesce_res; 1686 struct resource *params; 1687 resource_size_t size; 1688 int ret = 0; 1689 1690 /* 1691 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1692 * resource in the next generations of BlueField. 1693 */ 1694 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1695 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1696 MLXBF_I2C_COALESCE_RES); 1697 if (!coalesce_res) 1698 return -EPERM; 1699 1700 /* 1701 * The Cause Coalesce group in TYU space is shared among 1702 * I2C busses. This function MUST be serialized to avoid 1703 * racing when claiming the memory region. 1704 */ 1705 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1706 1707 /* Check whether the memory map exist. */ 1708 if (coalesce_res->io) { 1709 priv->coalesce = coalesce_res; 1710 return 0; 1711 } 1712 1713 params = coalesce_res->params; 1714 size = resource_size(params); 1715 1716 if (!request_mem_region(params->start, size, params->name)) 1717 return -EFAULT; 1718 1719 coalesce_res->io = ioremap(params->start, size); 1720 if (IS_ERR(coalesce_res->io)) { 1721 release_mem_region(params->start, size); 1722 return PTR_ERR(coalesce_res->io); 1723 } 1724 1725 priv->coalesce = coalesce_res; 1726 1727 } else { 1728 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1729 MLXBF_I2C_COALESCE_RES); 1730 } 1731 1732 return ret; 1733 } 1734 1735 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1736 struct mlxbf_i2c_priv *priv) 1737 { 1738 struct mlxbf_i2c_resource *coalesce_res; 1739 struct device *dev = &pdev->dev; 1740 struct resource *params; 1741 resource_size_t size; 1742 1743 coalesce_res = priv->coalesce; 1744 1745 if (coalesce_res->io) { 1746 params = coalesce_res->params; 1747 size = resource_size(params); 1748 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1749 mutex_lock(coalesce_res->lock); 1750 iounmap(coalesce_res->io); 1751 release_mem_region(params->start, size); 1752 mutex_unlock(coalesce_res->lock); 1753 } else { 1754 devm_release_mem_region(dev, params->start, size); 1755 } 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1762 struct mlxbf_i2c_priv *priv) 1763 { 1764 struct device *dev = &pdev->dev; 1765 u32 int_reg; 1766 int ret; 1767 1768 /* Reset FSM. */ 1769 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1770 1771 /* 1772 * Enable slave cause interrupt bits. Drive 1773 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1774 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1775 * masters issue a Read and Write, respectively. But, clear all 1776 * interrupts first. 1777 */ 1778 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1779 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1780 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1781 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1782 1783 /* Finally, set the 'ready' bit to start handling transactions. */ 1784 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1785 1786 /* Initialize the cause coalesce resource. */ 1787 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1788 if (ret < 0) { 1789 dev_err(dev, "failed to initialize cause coalesce\n"); 1790 return ret; 1791 } 1792 1793 return 0; 1794 } 1795 1796 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1797 bool *write) 1798 { 1799 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1800 u32 coalesce0_reg, cause_reg; 1801 u8 slave_shift, is_set; 1802 1803 *write = false; 1804 *read = false; 1805 1806 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1807 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1808 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1809 1810 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1811 is_set = coalesce0_reg & (1 << slave_shift); 1812 1813 if (!is_set) 1814 return false; 1815 1816 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1817 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1818 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1819 *read = true; 1820 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1821 *write = true; 1822 1823 /* Clear cause bits. */ 1824 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1825 1826 return true; 1827 } 1828 1829 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, 1830 u32 timeout) 1831 { 1832 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL; 1833 u32 addr = MLXBF_I2C_CAUSE_ARBITER; 1834 1835 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout)) 1836 return true; 1837 1838 return false; 1839 } 1840 1841 /* Send byte to 'external' smbus master. */ 1842 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1843 { 1844 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1845 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size; 1846 struct i2c_client *slave = priv->slave; 1847 u32 control32, data32; 1848 int ret; 1849 1850 if (!slave) 1851 return -EINVAL; 1852 1853 addr = 0; 1854 byte = 0; 1855 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; 1856 1857 /* 1858 * Read bytes received from the external master. These bytes should 1859 * be located in the first data descriptor register of the slave GW. 1860 * These bytes are the slave address byte and the internal register 1861 * address, if supplied. 1862 */ 1863 if (recv_bytes > 0) { 1864 data32 = ioread32be(priv->smbus->io + 1865 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1866 1867 /* Parse the received bytes. */ 1868 switch (recv_bytes) { 1869 case 2: 1870 byte = (data32 >> 8) & GENMASK(7, 0); 1871 fallthrough; 1872 case 1: 1873 addr = (data32 & GENMASK(7, 0)) >> 1; 1874 } 1875 1876 /* Check whether it's our slave address. */ 1877 if (slave->addr != addr) 1878 return -EINVAL; 1879 } 1880 1881 /* 1882 * I2C read transactions may start by a WRITE followed by a READ. 1883 * Indeed, most slave devices would expect the internal address 1884 * following the slave address byte. So, write that byte first, 1885 * and then, send the requested data bytes to the master. 1886 */ 1887 if (recv_bytes > 1) { 1888 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1889 value = byte; 1890 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1891 &value); 1892 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1893 1894 if (ret < 0) 1895 return ret; 1896 } 1897 1898 /* 1899 * Now, send data to the master; currently, the driver supports 1900 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the 1901 * hardware can send up to 128 bytes per transfer. That is the 1902 * size of its data registers. 1903 */ 1904 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1905 1906 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { 1907 data_desc[byte_cnt] = value; 1908 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1909 } 1910 1911 /* Send a stop condition to the backend. */ 1912 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1913 1914 /* Handle the actual transfer. */ 1915 1916 /* Set the number of bytes to write to master. */ 1917 write_size = (byte_cnt - 1) & 0x7f; 1918 1919 /* Write data to Slave GW data descriptor. */ 1920 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1921 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1922 1923 pec_en = 0; /* Disable PEC since it is not supported. */ 1924 1925 /* Prepare control word. */ 1926 control32 = MLXBF_I2C_SLAVE_ENABLE; 1927 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1928 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1929 1930 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1931 1932 /* 1933 * Wait until the transfer is completed; the driver will wait 1934 * until the GW is idle, a cause will rise on fall of GW busy. 1935 */ 1936 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1937 1938 /* Release the Slave GW. */ 1939 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1940 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1941 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1942 1943 return 0; 1944 } 1945 1946 /* Receive bytes from 'external' smbus master. */ 1947 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1948 { 1949 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1950 struct i2c_client *slave = priv->slave; 1951 u8 value, byte, addr; 1952 int ret = 0; 1953 1954 if (!slave) 1955 return -EINVAL; 1956 1957 /* Read data from Slave GW data descriptor. */ 1958 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1959 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1960 1961 /* Check whether its our slave address. */ 1962 addr = data_desc[0] >> 1; 1963 if (slave->addr != addr) 1964 return -EINVAL; 1965 1966 /* 1967 * Notify the slave backend; another I2C master wants to write data 1968 * to us. This event is sent once the slave address and the write bit 1969 * is detected. 1970 */ 1971 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1972 1973 /* Send the received data to the slave backend. */ 1974 for (byte = 1; byte < recv_bytes; byte++) { 1975 value = data_desc[byte]; 1976 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1977 &value); 1978 if (ret < 0) 1979 break; 1980 } 1981 1982 /* Send a stop condition to the backend. */ 1983 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1984 1985 /* Release the Slave GW. */ 1986 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1987 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1988 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1989 1990 return ret; 1991 } 1992 1993 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) 1994 { 1995 struct mlxbf_i2c_priv *priv = ptr; 1996 bool read, write, irq_is_set; 1997 u32 rw_bytes_reg; 1998 u8 recv_bytes; 1999 2000 /* 2001 * Read TYU interrupt register and determine the source of the 2002 * interrupt. Based on the source of the interrupt one of the 2003 * following actions are performed: 2004 * - Receive data and send response to master. 2005 * - Send data and release slave GW. 2006 * 2007 * Handle read/write transaction only. CRmaster and Iarp requests 2008 * are ignored for now. 2009 */ 2010 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 2011 if (!irq_is_set || (!read && !write)) { 2012 /* Nothing to do here, interrupt was not from this device. */ 2013 return IRQ_NONE; 2014 } 2015 2016 /* 2017 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 2018 * bytes from/to master. These are defined by 8-bits each. If the lower 2019 * 8 bits are set, then the master expect to read N bytes from the 2020 * slave, if the higher 8 bits are sent then the slave expect N bytes 2021 * from the master. 2022 */ 2023 rw_bytes_reg = readl(priv->smbus->io + 2024 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2025 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2026 2027 /* 2028 * For now, the slave supports 128 bytes transfer. Discard remaining 2029 * data bytes if the master wrote more than 2030 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2031 * data descriptor. 2032 * 2033 * Note that we will never expect to transfer more than 128 bytes; as 2034 * specified in the SMBus standard, block transactions cannot exceed 2035 * 32 bytes. 2036 */ 2037 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2038 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2039 2040 if (read) 2041 mlxbf_smbus_irq_send(priv, recv_bytes); 2042 else 2043 mlxbf_smbus_irq_recv(priv, recv_bytes); 2044 2045 return IRQ_HANDLED; 2046 } 2047 2048 /* Return negative errno on error. */ 2049 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2050 unsigned short flags, char read_write, 2051 u8 command, int size, 2052 union i2c_smbus_data *data) 2053 { 2054 struct mlxbf_i2c_smbus_request request = { 0 }; 2055 struct mlxbf_i2c_priv *priv; 2056 bool read, pec; 2057 u8 byte_cnt; 2058 2059 request.slave = addr; 2060 2061 read = (read_write == I2C_SMBUS_READ); 2062 pec = flags & I2C_FUNC_SMBUS_PEC; 2063 2064 switch (size) { 2065 case I2C_SMBUS_QUICK: 2066 mlxbf_i2c_smbus_quick_command(&request, read); 2067 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2068 break; 2069 2070 case I2C_SMBUS_BYTE: 2071 mlxbf_i2c_smbus_byte_func(&request, 2072 read ? &data->byte : &command, read, 2073 pec); 2074 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2075 read ? "read" : "write", addr); 2076 break; 2077 2078 case I2C_SMBUS_BYTE_DATA: 2079 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2080 read, pec); 2081 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2082 read ? "read" : "write", command, addr); 2083 break; 2084 2085 case I2C_SMBUS_WORD_DATA: 2086 mlxbf_i2c_smbus_data_word_func(&request, &command, 2087 (u8 *)&data->word, read, pec); 2088 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2089 read ? "read" : "write", command, addr); 2090 break; 2091 2092 case I2C_SMBUS_I2C_BLOCK_DATA: 2093 byte_cnt = data->block[0]; 2094 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2095 &byte_cnt, read, pec); 2096 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2097 read ? "read" : "write", byte_cnt, command, addr); 2098 break; 2099 2100 case I2C_SMBUS_BLOCK_DATA: 2101 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2102 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2103 &byte_cnt, read, pec); 2104 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2105 read ? "read" : "write", byte_cnt, command, addr); 2106 break; 2107 2108 case I2C_FUNC_SMBUS_PROC_CALL: 2109 mlxbf_i2c_smbus_process_call_func(&request, &command, 2110 (u8 *)&data->word, pec); 2111 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2112 command, addr); 2113 break; 2114 2115 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2116 byte_cnt = data->block[0]; 2117 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2118 data->block, &byte_cnt, 2119 pec); 2120 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2121 byte_cnt, addr); 2122 break; 2123 2124 default: 2125 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2126 size); 2127 return -EOPNOTSUPP; 2128 } 2129 2130 priv = i2c_get_adapdata(adap); 2131 2132 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2133 } 2134 2135 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2136 { 2137 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2138 int ret; 2139 2140 if (priv->slave) 2141 return -EBUSY; 2142 2143 /* 2144 * Do not support ten bit chip address and do not use Packet Error 2145 * Checking (PEC). 2146 */ 2147 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) 2148 return -EAFNOSUPPORT; 2149 2150 ret = mlxbf_slave_enable(priv, slave->addr); 2151 if (ret < 0) 2152 return ret; 2153 2154 priv->slave = slave; 2155 2156 return 0; 2157 } 2158 2159 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2160 { 2161 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2162 int ret; 2163 2164 WARN_ON(!priv->slave); 2165 2166 /* Unregister slave, i.e. disable the slave address in hardware. */ 2167 ret = mlxbf_slave_disable(priv); 2168 if (ret < 0) 2169 return ret; 2170 2171 priv->slave = NULL; 2172 2173 return 0; 2174 } 2175 2176 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2177 { 2178 return MLXBF_I2C_FUNC_ALL; 2179 } 2180 2181 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2182 [MLXBF_I2C_CHIP_TYPE_1] = { 2183 .type = MLXBF_I2C_CHIP_TYPE_1, 2184 .shared_res = { 2185 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2186 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2187 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2188 }, 2189 .calculate_freq = mlxbf_calculate_freq_from_tyu 2190 }, 2191 [MLXBF_I2C_CHIP_TYPE_2] = { 2192 .type = MLXBF_I2C_CHIP_TYPE_2, 2193 .shared_res = { 2194 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2195 }, 2196 .calculate_freq = mlxbf_calculate_freq_from_yu 2197 } 2198 }; 2199 2200 static const struct i2c_algorithm mlxbf_i2c_algo = { 2201 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2202 .functionality = mlxbf_i2c_functionality, 2203 .reg_slave = mlxbf_i2c_reg_slave, 2204 .unreg_slave = mlxbf_i2c_unreg_slave, 2205 }; 2206 2207 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2208 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2209 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2210 }; 2211 2212 static const struct of_device_id mlxbf_i2c_dt_ids[] = { 2213 { 2214 .compatible = "mellanox,i2c-mlxbf1", 2215 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] 2216 }, 2217 { 2218 .compatible = "mellanox,i2c-mlxbf2", 2219 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] 2220 }, 2221 {}, 2222 }; 2223 2224 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2225 2226 #ifdef CONFIG_ACPI 2227 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2228 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2229 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2230 {}, 2231 }; 2232 2233 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2234 2235 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2236 { 2237 const struct acpi_device_id *aid; 2238 struct acpi_device *adev; 2239 unsigned long bus_id = 0; 2240 const char *uid; 2241 int ret; 2242 2243 if (acpi_disabled) 2244 return -ENOENT; 2245 2246 adev = ACPI_COMPANION(dev); 2247 if (!adev) 2248 return -ENXIO; 2249 2250 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2251 if (!aid) 2252 return -ENODEV; 2253 2254 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2255 2256 uid = acpi_device_uid(adev); 2257 if (!uid || !(*uid)) { 2258 dev_err(dev, "Cannot retrieve UID\n"); 2259 return -ENODEV; 2260 } 2261 2262 ret = kstrtoul(uid, 0, &bus_id); 2263 if (!ret) 2264 priv->bus = bus_id; 2265 2266 return ret; 2267 } 2268 #else 2269 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2270 { 2271 return -ENOENT; 2272 } 2273 #endif /* CONFIG_ACPI */ 2274 2275 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2276 { 2277 const struct of_device_id *oid; 2278 int bus_id = -1; 2279 2280 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 2281 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node); 2282 if (!oid) 2283 return -ENODEV; 2284 2285 priv->chip = oid->data; 2286 2287 bus_id = of_alias_get_id(dev->of_node, "i2c"); 2288 if (bus_id >= 0) 2289 priv->bus = bus_id; 2290 } 2291 2292 if (bus_id < 0) { 2293 dev_err(dev, "Cannot get bus id"); 2294 return bus_id; 2295 } 2296 2297 return 0; 2298 } 2299 2300 static int mlxbf_i2c_probe(struct platform_device *pdev) 2301 { 2302 struct device *dev = &pdev->dev; 2303 struct mlxbf_i2c_priv *priv; 2304 struct i2c_adapter *adap; 2305 int irq, ret; 2306 2307 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2308 if (!priv) 2309 return -ENOMEM; 2310 2311 ret = mlxbf_i2c_acpi_probe(dev, priv); 2312 if (ret < 0 && ret != -ENOENT && ret != -ENXIO) 2313 ret = mlxbf_i2c_of_probe(dev, priv); 2314 2315 if (ret < 0) 2316 return ret; 2317 2318 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2319 MLXBF_I2C_SMBUS_RES); 2320 if (ret < 0) { 2321 dev_err(dev, "Cannot fetch smbus resource info"); 2322 return ret; 2323 } 2324 2325 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2326 MLXBF_I2C_MST_CAUSE_RES); 2327 if (ret < 0) { 2328 dev_err(dev, "Cannot fetch cause master resource info"); 2329 return ret; 2330 } 2331 2332 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2333 MLXBF_I2C_SLV_CAUSE_RES); 2334 if (ret < 0) { 2335 dev_err(dev, "Cannot fetch cause slave resource info"); 2336 return ret; 2337 } 2338 2339 adap = &priv->adap; 2340 adap->owner = THIS_MODULE; 2341 adap->class = I2C_CLASS_HWMON; 2342 adap->algo = &mlxbf_i2c_algo; 2343 adap->quirks = &mlxbf_i2c_quirks; 2344 adap->dev.parent = dev; 2345 adap->dev.of_node = dev->of_node; 2346 adap->nr = priv->bus; 2347 2348 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2349 i2c_set_adapdata(adap, priv); 2350 2351 /* Read Core PLL frequency. */ 2352 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2353 if (ret < 0) { 2354 dev_err(dev, "cannot get core clock frequency\n"); 2355 /* Set to default value. */ 2356 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2357 } 2358 2359 /* 2360 * Initialize master. 2361 * Note that a physical bus might be shared among Linux and firmware 2362 * (e.g., ATF). Thus, the bus should be initialized and ready and 2363 * bus initialization would be unnecessary. This requires additional 2364 * knowledge about physical busses. But, since an extra initialization 2365 * does not really hurt, then keep the code as is. 2366 */ 2367 ret = mlxbf_i2c_init_master(pdev, priv); 2368 if (ret < 0) { 2369 dev_err(dev, "failed to initialize smbus master %d", 2370 priv->bus); 2371 return ret; 2372 } 2373 2374 mlxbf_i2c_init_timings(pdev, priv); 2375 2376 mlxbf_i2c_init_slave(pdev, priv); 2377 2378 irq = platform_get_irq(pdev, 0); 2379 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2380 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2381 dev_name(dev), priv); 2382 if (ret < 0) { 2383 dev_err(dev, "Cannot get irq %d\n", irq); 2384 return ret; 2385 } 2386 2387 priv->irq = irq; 2388 2389 platform_set_drvdata(pdev, priv); 2390 2391 ret = i2c_add_numbered_adapter(adap); 2392 if (ret < 0) 2393 return ret; 2394 2395 mutex_lock(&mlxbf_i2c_bus_lock); 2396 mlxbf_i2c_bus_count++; 2397 mutex_unlock(&mlxbf_i2c_bus_lock); 2398 2399 return 0; 2400 } 2401 2402 static int mlxbf_i2c_remove(struct platform_device *pdev) 2403 { 2404 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2405 struct device *dev = &pdev->dev; 2406 struct resource *params; 2407 2408 params = priv->smbus->params; 2409 devm_release_mem_region(dev, params->start, resource_size(params)); 2410 2411 params = priv->mst_cause->params; 2412 devm_release_mem_region(dev, params->start, resource_size(params)); 2413 2414 params = priv->slv_cause->params; 2415 devm_release_mem_region(dev, params->start, resource_size(params)); 2416 2417 /* 2418 * Release shared resources. This should be done when releasing 2419 * the I2C controller. 2420 */ 2421 mutex_lock(&mlxbf_i2c_bus_lock); 2422 if (--mlxbf_i2c_bus_count == 0) { 2423 mlxbf_i2c_release_coalesce(pdev, priv); 2424 mlxbf_i2c_release_corepll(pdev, priv); 2425 mlxbf_i2c_release_gpio(pdev, priv); 2426 } 2427 mutex_unlock(&mlxbf_i2c_bus_lock); 2428 2429 devm_free_irq(dev, priv->irq, priv); 2430 2431 i2c_del_adapter(&priv->adap); 2432 2433 return 0; 2434 } 2435 2436 static struct platform_driver mlxbf_i2c_driver = { 2437 .probe = mlxbf_i2c_probe, 2438 .remove = mlxbf_i2c_remove, 2439 .driver = { 2440 .name = "i2c-mlxbf", 2441 .of_match_table = mlxbf_i2c_dt_ids, 2442 #ifdef CONFIG_ACPI 2443 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2444 #endif /* CONFIG_ACPI */ 2445 }, 2446 }; 2447 2448 static int __init mlxbf_i2c_init(void) 2449 { 2450 mutex_init(&mlxbf_i2c_coalesce_lock); 2451 mutex_init(&mlxbf_i2c_corepll_lock); 2452 mutex_init(&mlxbf_i2c_gpio_lock); 2453 2454 mutex_init(&mlxbf_i2c_bus_lock); 2455 2456 return platform_driver_register(&mlxbf_i2c_driver); 2457 } 2458 module_init(mlxbf_i2c_init); 2459 2460 static void __exit mlxbf_i2c_exit(void) 2461 { 2462 platform_driver_unregister(&mlxbf_i2c_driver); 2463 2464 mutex_destroy(&mlxbf_i2c_bus_lock); 2465 2466 mutex_destroy(&mlxbf_i2c_gpio_lock); 2467 mutex_destroy(&mlxbf_i2c_corepll_lock); 2468 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2469 } 2470 module_exit(mlxbf_i2c_exit); 2471 2472 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2473 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2474 MODULE_LICENSE("GPL v2"); 2475