1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/i2c.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/string.h> 20 21 /* Defines what functionality is present. */ 22 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 23 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 24 25 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 26 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 27 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 28 I2C_FUNC_SMBUS_PROC_CALL) 29 30 #define MLXBF_I2C_FUNC_ALL \ 31 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 32 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 33 34 #define MLXBF_I2C_SMBUS_MAX 3 35 36 /* Shared resources info in BlueField platforms. */ 37 38 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 39 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 40 41 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 42 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 43 44 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 45 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 46 47 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 48 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 49 50 #define MLXBF_I2C_SHARED_RES_MAX 3 51 52 /* 53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 54 * refer to their respective offsets relative to the corresponding 55 * memory-mapped region whose addresses are specified in either the DT or 56 * the ACPI tables or above. 57 */ 58 59 /* 60 * SMBus Master core clock frequency. Timing configurations are 61 * strongly dependent on the core clock frequency of the SMBus 62 * Master. Default value is set to 400MHz. 63 */ 64 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 65 /* Reference clock for Bluefield - 156 MHz. */ 66 #define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000) 67 68 /* Constant used to determine the PLL frequency. */ 69 #define MLNXBF_I2C_COREPLL_CONST 16384 70 71 /* PLL registers. */ 72 #define MLXBF_I2C_CORE_PLL_REG0 0x0 73 #define MLXBF_I2C_CORE_PLL_REG1 0x4 74 #define MLXBF_I2C_CORE_PLL_REG2 0x8 75 76 /* OR cause register. */ 77 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 78 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 79 80 /* Arbiter Cause Register. */ 81 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 82 83 /* 84 * Cause Status flags. Note that those bits might be considered 85 * as interrupt enabled bits. 86 */ 87 88 /* Transaction ended with STOP. */ 89 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 90 /* Master arbitration lost. */ 91 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 92 /* Unexpected start detected. */ 93 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 94 /* Unexpected stop detected. */ 95 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 96 /* Wait for transfer continuation. */ 97 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 98 /* Failed to generate STOP. */ 99 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 100 /* Failed to generate START. */ 101 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 102 /* Clock toggle completed. */ 103 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 104 /* Transfer timeout occurred. */ 105 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 106 /* Master busy bit reset. */ 107 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 108 109 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 110 111 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 112 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 113 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 114 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 115 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 116 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 117 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 118 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 119 120 /* 121 * Slave cause status flags. Note that those bits might be considered 122 * as interrupt enabled bits. 123 */ 124 125 /* Write transaction received successfully. */ 126 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 127 /* Read transaction received, waiting for response. */ 128 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 129 /* Slave busy bit reset. */ 130 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 131 132 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0) 133 134 /* Cause coalesce registers. */ 135 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 136 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04 137 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08 138 139 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX 140 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 141 142 /* Functional enable register. */ 143 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 144 /* Force OE enable register. */ 145 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 146 /* 147 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 148 * SDA/SCL lines: 149 * 150 * SMBUS GW0 -> bits[26:25] 151 * SMBUS GW1 -> bits[28:27] 152 * SMBUS GW2 -> bits[30:29] 153 */ 154 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 155 156 /* Note that gw_id can be 0,1 or 2. */ 157 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 158 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 159 160 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 161 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 162 163 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 164 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 165 166 /* SMBus timing parameters. */ 167 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 168 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 169 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 170 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 171 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 172 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 173 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 174 175 /* 176 * Defines SMBus operating frequency and core clock frequency. 177 * According to ADB files, default values are compliant to 100KHz SMBus 178 * @ 400MHz core clock. The driver should be able to calculate core 179 * frequency based on PLL parameters. 180 */ 181 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 182 183 /* Core PLL TYU configuration. */ 184 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(12, 0) 185 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(3, 0) 186 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(5, 0) 187 188 #define MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT 3 189 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT 16 190 #define MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT 20 191 192 /* Core PLL YU configuration. */ 193 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 194 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 195 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(5, 0) 196 197 #define MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT 0 198 #define MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT 1 199 #define MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT 26 200 201 /* Core PLL frequency. */ 202 static u64 mlxbf_i2c_corepll_frequency; 203 204 /* SMBus Master GW. */ 205 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200 206 /* Number of bytes received and sent. */ 207 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300 208 /* Packet error check (PEC) value. */ 209 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304 210 /* Status bits (ACK/NACK/FW Timeout). */ 211 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308 212 /* SMbus Master Finite State Machine. */ 213 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310 214 215 /* 216 * When enabled, the master will issue a stop condition in case of 217 * timeout while waiting for FW response. 218 */ 219 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c 220 221 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 222 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 223 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 224 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 225 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 226 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 227 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 228 229 #define MLXBF_I2C_MASTER_ENABLE \ 230 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 231 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 232 233 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 234 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 235 236 #define MLXBF_I2C_MASTER_ENABLE_READ \ 237 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 238 239 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */ 240 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */ 241 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */ 242 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */ 243 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */ 244 245 /* SMBus master GW Data descriptor. */ 246 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280 247 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 248 249 /* Maximum bytes to read/write per SMBus transaction. */ 250 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 251 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 252 253 /* All bytes were transmitted. */ 254 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 255 /* NACK received. */ 256 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 257 /* Slave's byte count >128 bytes. */ 258 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 259 /* Timeout occurred. */ 260 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 261 262 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 263 264 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 265 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 266 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 267 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 268 269 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 270 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 271 272 /* SMBus slave GW. */ 273 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400 274 /* Number of bytes received and sent from/to master. */ 275 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500 276 /* Packet error check (PEC) value. */ 277 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504 278 /* SMBus slave Finite State Machine (FSM). */ 279 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510 280 /* 281 * Should be set when all raised causes handled, and cleared by HW on 282 * every new cause. 283 */ 284 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c 285 286 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 287 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 288 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 289 290 #define MLXBF_I2C_SLAVE_ENABLE \ 291 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 292 293 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 294 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 295 296 /* SMBus slave GW Data descriptor. */ 297 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480 298 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 299 300 /* SMbus slave configuration registers. */ 301 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514 302 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 303 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 304 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 305 306 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \ 307 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) 308 309 /* 310 * Timeout is given in microsends. Note also that timeout handling is not 311 * exact. 312 */ 313 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 314 315 /* Encapsulates timing parameters. */ 316 struct mlxbf_i2c_timings { 317 u16 scl_high; /* Clock high period. */ 318 u16 scl_low; /* Clock low period. */ 319 u8 sda_rise; /* Data rise time. */ 320 u8 sda_fall; /* Data fall time. */ 321 u8 scl_rise; /* Clock rise time. */ 322 u8 scl_fall; /* Clock fall time. */ 323 u16 hold_start; /* Hold time after (REPEATED) START. */ 324 u16 hold_data; /* Data hold time. */ 325 u16 setup_start; /* REPEATED START condition setup time. */ 326 u16 setup_stop; /* STOP condition setup time. */ 327 u16 setup_data; /* Data setup time. */ 328 u16 pad; /* Padding. */ 329 u16 buf; /* Bus free time between STOP and START. */ 330 u16 thigh_max; /* Thigh max. */ 331 u32 timeout; /* Detect clock low timeout. */ 332 }; 333 334 enum { 335 MLXBF_I2C_F_READ = BIT(0), 336 MLXBF_I2C_F_WRITE = BIT(1), 337 MLXBF_I2C_F_NORESTART = BIT(3), 338 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 339 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 340 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 341 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 342 }; 343 344 struct mlxbf_i2c_smbus_operation { 345 u32 flags; 346 u32 length; /* Buffer length in bytes. */ 347 u8 *buffer; 348 }; 349 350 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 351 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 352 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 353 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 354 355 struct mlxbf_i2c_smbus_request { 356 u8 slave; 357 u8 operation_cnt; 358 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 359 }; 360 361 struct mlxbf_i2c_resource { 362 void __iomem *io; 363 struct resource *params; 364 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 365 u8 type; 366 }; 367 368 /* List of chip resources that are being accessed by the driver. */ 369 enum { 370 MLXBF_I2C_SMBUS_RES, 371 MLXBF_I2C_MST_CAUSE_RES, 372 MLXBF_I2C_SLV_CAUSE_RES, 373 MLXBF_I2C_COALESCE_RES, 374 MLXBF_I2C_COREPLL_RES, 375 MLXBF_I2C_GPIO_RES, 376 MLXBF_I2C_END_RES, 377 }; 378 379 /* Helper macro to define an I2C resource parameters. */ 380 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 381 { \ 382 .start = (addr), \ 383 .end = (addr) + (size) - 1, \ 384 .name = (str) \ 385 } 386 387 static struct resource mlxbf_i2c_coalesce_tyu_params = 388 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 389 MLXBF_I2C_COALESCE_TYU_SIZE, 390 "COALESCE_MEM"); 391 static struct resource mlxbf_i2c_corepll_tyu_params = 392 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 393 MLXBF_I2C_COREPLL_TYU_SIZE, 394 "COREPLL_MEM"); 395 static struct resource mlxbf_i2c_corepll_yu_params = 396 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 397 MLXBF_I2C_COREPLL_YU_SIZE, 398 "COREPLL_MEM"); 399 static struct resource mlxbf_i2c_gpio_tyu_params = 400 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 401 MLXBF_I2C_GPIO_TYU_SIZE, 402 "GPIO_MEM"); 403 404 static struct mutex mlxbf_i2c_coalesce_lock; 405 static struct mutex mlxbf_i2c_corepll_lock; 406 static struct mutex mlxbf_i2c_gpio_lock; 407 408 /* Mellanox BlueField chip type. */ 409 enum mlxbf_i2c_chip_type { 410 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 411 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */ 412 }; 413 414 struct mlxbf_i2c_chip_info { 415 enum mlxbf_i2c_chip_type type; 416 /* Chip shared resources that are being used by the I2C controller. */ 417 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 418 419 /* Callback to calculate the core PLL frequency. */ 420 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 421 }; 422 423 struct mlxbf_i2c_priv { 424 const struct mlxbf_i2c_chip_info *chip; 425 struct i2c_adapter adap; 426 struct mlxbf_i2c_resource *smbus; 427 struct mlxbf_i2c_resource *mst_cause; 428 struct mlxbf_i2c_resource *slv_cause; 429 struct mlxbf_i2c_resource *coalesce; 430 u64 frequency; /* Core frequency in Hz. */ 431 int bus; /* Physical bus identifier. */ 432 int irq; 433 struct i2c_client *slave; 434 }; 435 436 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 437 [MLXBF_I2C_CHIP_TYPE_1] = { 438 .params = &mlxbf_i2c_coalesce_tyu_params, 439 .lock = &mlxbf_i2c_coalesce_lock, 440 .type = MLXBF_I2C_COALESCE_RES 441 }, 442 {} 443 }; 444 445 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 446 [MLXBF_I2C_CHIP_TYPE_1] = { 447 .params = &mlxbf_i2c_corepll_tyu_params, 448 .lock = &mlxbf_i2c_corepll_lock, 449 .type = MLXBF_I2C_COREPLL_RES 450 }, 451 [MLXBF_I2C_CHIP_TYPE_2] = { 452 .params = &mlxbf_i2c_corepll_yu_params, 453 .lock = &mlxbf_i2c_corepll_lock, 454 .type = MLXBF_I2C_COREPLL_RES, 455 } 456 }; 457 458 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 459 [MLXBF_I2C_CHIP_TYPE_1] = { 460 .params = &mlxbf_i2c_gpio_tyu_params, 461 .lock = &mlxbf_i2c_gpio_lock, 462 .type = MLXBF_I2C_GPIO_RES 463 }, 464 {} 465 }; 466 467 static u8 mlxbf_i2c_bus_count; 468 469 static struct mutex mlxbf_i2c_bus_lock; 470 471 /* Polling frequency in microseconds. */ 472 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 473 474 #define MLXBF_I2C_SHIFT_0 0 475 #define MLXBF_I2C_SHIFT_8 8 476 #define MLXBF_I2C_SHIFT_16 16 477 #define MLXBF_I2C_SHIFT_24 24 478 479 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 480 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 481 482 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000 483 484 /* 485 * Function to poll a set of bits at a specific address; it checks whether 486 * the bits are equal to zero when eq_zero is set to 'true', and not equal 487 * to zero when eq_zero is set to 'false'. 488 * Note that the timeout is given in microseconds. 489 */ 490 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask, 491 bool eq_zero, u32 timeout) 492 { 493 u32 bits; 494 495 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 496 497 do { 498 bits = readl(io + addr) & mask; 499 if (eq_zero ? bits == 0 : bits != 0) 500 return eq_zero ? 1 : bits; 501 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); 502 } while (timeout-- != 0); 503 504 return 0; 505 } 506 507 /* 508 * SW must make sure that the SMBus Master GW is idle before starting 509 * a transaction. Accordingly, this function polls the Master FSM stop 510 * bit; it returns false when the bit is asserted, true if not. 511 */ 512 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) 513 { 514 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK; 515 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM; 516 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT; 517 518 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout)) 519 return true; 520 521 return false; 522 } 523 524 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 525 u32 cause_status) 526 { 527 /* 528 * When transaction ended with STOP, all bytes were transmitted, 529 * and no NACK received, then the transaction ended successfully. 530 * On the other hand, when the GW is configured with the stop bit 531 * de-asserted then the SMBus expects the following GW configuration 532 * for transfer continuation. 533 */ 534 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 535 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 536 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 537 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 538 return true; 539 540 return false; 541 } 542 543 /* 544 * Poll SMBus master status and return transaction status, 545 * i.e. whether succeeded or failed. I2C and SMBus fault codes 546 * are returned as negative numbers from most calls, with zero 547 * or some positive number indicating a non-fault return. 548 */ 549 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 550 { 551 u32 master_status_bits; 552 u32 cause_status_bits; 553 554 /* 555 * GW busy bit is raised by the driver and cleared by the HW 556 * when the transaction is completed. The busy bit is a good 557 * indicator of transaction status. So poll the busy bit, and 558 * then read the cause and master status bits to determine if 559 * errors occurred during the transaction. 560 */ 561 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 562 MLXBF_I2C_MASTER_BUSY_BIT, true, 563 MLXBF_I2C_SMBUS_TIMEOUT); 564 565 /* Read cause status bits. */ 566 cause_status_bits = readl(priv->mst_cause->io + 567 MLXBF_I2C_CAUSE_ARBITER); 568 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 569 570 /* 571 * Parse both Cause and Master GW bits, then return transaction status. 572 */ 573 574 master_status_bits = readl(priv->smbus->io + 575 MLXBF_I2C_SMBUS_MASTER_STATUS); 576 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 577 578 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 579 cause_status_bits)) 580 return 0; 581 582 /* 583 * In case of timeout on GW busy, the ISR will clear busy bit but 584 * transaction ended bits cause will not be set so the transaction 585 * fails. Then, we must check Master GW status bits. 586 */ 587 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 588 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 589 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 590 return -EIO; 591 592 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 593 return -EAGAIN; 594 595 return -ETIMEDOUT; 596 } 597 598 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 599 const u8 *data, u8 length, u32 addr) 600 { 601 u8 offset, aligned_length; 602 u32 data32; 603 604 aligned_length = round_up(length, 4); 605 606 /* 607 * Copy data bytes from 4-byte aligned source buffer. 608 * Data copied to the Master GW Data Descriptor MUST be shifted 609 * left so the data starts at the MSB of the descriptor registers 610 * as required by the underlying hardware. Enable byte swapping 611 * when writing data bytes to the 32 * 32-bit HW Data registers 612 * a.k.a Master GW Data Descriptor. 613 */ 614 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 615 data32 = *((u32 *)(data + offset)); 616 iowrite32be(data32, priv->smbus->io + addr + offset); 617 } 618 } 619 620 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 621 u8 *data, u8 length, u32 addr) 622 { 623 u32 data32, mask; 624 u8 byte, offset; 625 626 mask = sizeof(u32) - 1; 627 628 /* 629 * Data bytes in the Master GW Data Descriptor are shifted left 630 * so the data starts at the MSB of the descriptor registers as 631 * set by the underlying hardware. Enable byte swapping while 632 * reading data bytes from the 32 * 32-bit HW Data registers 633 * a.k.a Master GW Data Descriptor. 634 */ 635 636 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 637 data32 = ioread32be(priv->smbus->io + addr + offset); 638 *((u32 *)(data + offset)) = data32; 639 } 640 641 if (!(length & mask)) 642 return; 643 644 data32 = ioread32be(priv->smbus->io + addr + offset); 645 646 for (byte = 0; byte < (length & mask); byte++) { 647 data[offset + byte] = data32 & GENMASK(7, 0); 648 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 649 } 650 } 651 652 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 653 u8 len, u8 block_en, u8 pec_en, bool read) 654 { 655 u32 command; 656 657 /* Set Master GW control word. */ 658 if (read) { 659 command = MLXBF_I2C_MASTER_ENABLE_READ; 660 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 661 } else { 662 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 663 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 664 } 665 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 666 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 667 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 668 669 /* Clear status bits. */ 670 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 671 /* Set the cause data. */ 672 writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR); 673 /* Zero PEC byte. */ 674 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC); 675 /* Zero byte count. */ 676 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES); 677 678 /* GW activation. */ 679 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 680 681 /* 682 * Poll master status and check status bits. An ACK is sent when 683 * completing writing data to the bus (Master 'byte_count_done' bit 684 * is set to 1). 685 */ 686 return mlxbf_i2c_smbus_check_status(priv); 687 } 688 689 static int 690 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 691 struct mlxbf_i2c_smbus_request *request) 692 { 693 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 694 u8 op_idx, data_idx, data_len, write_len, read_len; 695 struct mlxbf_i2c_smbus_operation *operation; 696 u8 read_en, write_en, block_en, pec_en; 697 u8 slave, flags, addr; 698 u8 *read_buf; 699 int ret = 0; 700 701 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 702 return -EINVAL; 703 704 read_buf = NULL; 705 data_idx = 0; 706 read_en = 0; 707 write_en = 0; 708 write_len = 0; 709 read_len = 0; 710 block_en = 0; 711 pec_en = 0; 712 slave = request->slave & GENMASK(6, 0); 713 addr = slave << 1; 714 715 /* First of all, check whether the HW is idle. */ 716 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) 717 return -EBUSY; 718 719 /* Set first byte. */ 720 data_desc[data_idx++] = addr; 721 722 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 723 operation = &request->operation[op_idx]; 724 flags = operation->flags; 725 726 /* 727 * Note that read and write operations might be handled by a 728 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 729 * then write command byte and set the optional SMBus specific 730 * bits such as block_en and pec_en. These bits MUST be 731 * submitted by the first operation only. 732 */ 733 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 734 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 735 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 736 } 737 738 if (flags & MLXBF_I2C_F_WRITE) { 739 write_en = 1; 740 write_len += operation->length; 741 memcpy(data_desc + data_idx, 742 operation->buffer, operation->length); 743 data_idx += operation->length; 744 } 745 /* 746 * We assume that read operations are performed only once per 747 * SMBus transaction. *TBD* protect this statement so it won't 748 * be executed twice? or return an error if we try to read more 749 * than once? 750 */ 751 if (flags & MLXBF_I2C_F_READ) { 752 read_en = 1; 753 /* Subtract 1 as required by HW. */ 754 read_len = operation->length - 1; 755 read_buf = operation->buffer; 756 } 757 } 758 759 /* Set Master GW data descriptor. */ 760 data_len = write_len + 1; /* Add one byte of the slave address. */ 761 /* 762 * Note that data_len cannot be 0. Indeed, the slave address byte 763 * must be written to the data registers. 764 */ 765 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 766 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 767 768 if (write_en) { 769 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 770 pec_en, 0); 771 if (ret) 772 return ret; 773 } 774 775 if (read_en) { 776 /* Write slave address to Master GW data descriptor. */ 777 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 778 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 779 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 780 pec_en, 1); 781 if (!ret) { 782 /* Get Master GW data descriptor. */ 783 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 784 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 785 786 /* Get data from Master GW data descriptor. */ 787 memcpy(read_buf, data_desc, read_len + 1); 788 } 789 790 /* 791 * After a read operation the SMBus FSM ps (present state) 792 * needs to be 'manually' reset. This should be removed in 793 * next tag integration. 794 */ 795 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 796 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); 797 } 798 799 return ret; 800 } 801 802 /* I2C SMBus protocols. */ 803 804 static void 805 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 806 u8 read) 807 { 808 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 809 810 request->operation[0].length = 0; 811 request->operation[0].flags = MLXBF_I2C_F_WRITE; 812 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 813 } 814 815 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 816 u8 *data, bool read, bool pec_check) 817 { 818 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 819 820 request->operation[0].length = 1; 821 request->operation[0].length += pec_check; 822 823 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 824 request->operation[0].flags |= read ? 825 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 826 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 827 828 request->operation[0].buffer = data; 829 } 830 831 static void 832 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 833 u8 *command, u8 *data, bool read, bool pec_check) 834 { 835 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 836 837 request->operation[0].length = 1; 838 request->operation[0].flags = 839 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 840 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 841 request->operation[0].buffer = command; 842 843 request->operation[1].length = 1; 844 request->operation[1].length += pec_check; 845 request->operation[1].flags = read ? 846 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 847 request->operation[1].buffer = data; 848 } 849 850 static void 851 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 852 u8 *command, u8 *data, bool read, bool pec_check) 853 { 854 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 855 856 request->operation[0].length = 1; 857 request->operation[0].flags = 858 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 859 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 860 request->operation[0].buffer = command; 861 862 request->operation[1].length = 2; 863 request->operation[1].length += pec_check; 864 request->operation[1].flags = read ? 865 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 866 request->operation[1].buffer = data; 867 } 868 869 static void 870 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 871 u8 *command, u8 *data, u8 *data_len, bool read, 872 bool pec_check) 873 { 874 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 875 876 request->operation[0].length = 1; 877 request->operation[0].flags = 878 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 879 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 880 request->operation[0].buffer = command; 881 882 /* 883 * As specified in the standard, the max number of bytes to read/write 884 * per block operation is 32 bytes. In Golan code, the controller can 885 * read up to 128 bytes and write up to 127 bytes. 886 */ 887 request->operation[1].length = 888 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 889 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 890 request->operation[1].flags = read ? 891 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 892 /* 893 * Skip the first data byte, which corresponds to the number of bytes 894 * to read/write. 895 */ 896 request->operation[1].buffer = data + 1; 897 898 *data_len = request->operation[1].length; 899 900 /* Set the number of byte to read. This will be used by userspace. */ 901 if (read) 902 data[0] = *data_len; 903 } 904 905 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 906 u8 *command, u8 *data, u8 *data_len, 907 bool read, bool pec_check) 908 { 909 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 910 911 request->operation[0].length = 1; 912 request->operation[0].flags = 913 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 914 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 915 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 916 request->operation[0].buffer = command; 917 918 request->operation[1].length = 919 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 920 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 921 request->operation[1].flags = read ? 922 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 923 request->operation[1].buffer = data + 1; 924 925 *data_len = request->operation[1].length; 926 927 /* Set the number of bytes to read. This will be used by userspace. */ 928 if (read) 929 data[0] = *data_len; 930 } 931 932 static void 933 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 934 u8 *command, u8 *data, bool pec_check) 935 { 936 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 937 938 request->operation[0].length = 1; 939 request->operation[0].flags = 940 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 941 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 942 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 943 request->operation[0].buffer = command; 944 945 request->operation[1].length = 2; 946 request->operation[1].flags = MLXBF_I2C_F_WRITE; 947 request->operation[1].buffer = data; 948 949 request->operation[2].length = 3; 950 request->operation[2].flags = MLXBF_I2C_F_READ; 951 request->operation[2].buffer = data; 952 } 953 954 static void 955 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 956 u8 *command, u8 *data, u8 *data_len, 957 bool pec_check) 958 { 959 u32 length; 960 961 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 962 963 request->operation[0].length = 1; 964 request->operation[0].flags = 965 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 966 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 967 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 968 request->operation[0].buffer = command; 969 970 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 971 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 972 973 request->operation[1].length = length - pec_check; 974 request->operation[1].flags = MLXBF_I2C_F_WRITE; 975 request->operation[1].buffer = data; 976 977 request->operation[2].length = length; 978 request->operation[2].flags = MLXBF_I2C_F_READ; 979 request->operation[2].buffer = data; 980 981 *data_len = length; /* including PEC byte. */ 982 } 983 984 /* Initialization functions. */ 985 986 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 987 { 988 return priv->chip->type == type; 989 } 990 991 static struct mlxbf_i2c_resource * 992 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 993 { 994 const struct mlxbf_i2c_chip_info *chip = priv->chip; 995 struct mlxbf_i2c_resource *res; 996 u8 res_idx = 0; 997 998 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 999 res = chip->shared_res[res_idx]; 1000 if (res && res->type == type) 1001 return res; 1002 } 1003 1004 return NULL; 1005 } 1006 1007 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1008 struct mlxbf_i2c_resource **res, 1009 u8 type) 1010 { 1011 struct mlxbf_i2c_resource *tmp_res; 1012 struct device *dev = &pdev->dev; 1013 1014 if (!res || *res || type >= MLXBF_I2C_END_RES) 1015 return -EINVAL; 1016 1017 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1018 GFP_KERNEL); 1019 if (!tmp_res) 1020 return -ENOMEM; 1021 1022 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type); 1023 if (!tmp_res->params) { 1024 devm_kfree(dev, tmp_res); 1025 return -EIO; 1026 } 1027 1028 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params); 1029 if (IS_ERR(tmp_res->io)) { 1030 devm_kfree(dev, tmp_res); 1031 return PTR_ERR(tmp_res->io); 1032 } 1033 1034 tmp_res->type = type; 1035 1036 *res = tmp_res; 1037 1038 return 0; 1039 } 1040 1041 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1042 bool minimum) 1043 { 1044 u64 frequency; 1045 u32 ticks; 1046 1047 /* 1048 * Compute ticks as follow: 1049 * 1050 * Ticks 1051 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1052 * Frequency 1053 */ 1054 frequency = priv->frequency; 1055 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1056 /* 1057 * The number of ticks is rounded down and if minimum is equal to 1 1058 * then add one tick. 1059 */ 1060 if (minimum) 1061 ticks++; 1062 1063 return ticks; 1064 } 1065 1066 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1067 u32 mask, u8 shift) 1068 { 1069 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1070 1071 return val; 1072 } 1073 1074 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1075 const struct mlxbf_i2c_timings *timings) 1076 { 1077 u32 timer; 1078 1079 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1080 false, MLXBF_I2C_MASK_16, 1081 MLXBF_I2C_SHIFT_0); 1082 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1083 false, MLXBF_I2C_MASK_16, 1084 MLXBF_I2C_SHIFT_16); 1085 writel(timer, priv->smbus->io + 1086 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1087 1088 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1089 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1090 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1091 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1092 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1093 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1094 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1095 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1096 writel(timer, priv->smbus->io + 1097 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1098 1099 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1100 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1101 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1102 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1103 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1104 1105 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1106 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1107 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1108 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1109 writel(timer, priv->smbus->io + 1110 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1111 1112 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1113 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1114 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1115 1116 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1117 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1118 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1119 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1120 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1121 1122 timer = timings->timeout; 1123 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1124 } 1125 1126 enum mlxbf_i2c_timings_config { 1127 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1128 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1129 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1130 }; 1131 1132 /* 1133 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1134 * bus frequency, it is impacted by the time it takes the driver to 1135 * complete data transmission before transaction abort. 1136 */ 1137 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1138 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1139 .scl_high = 4810, 1140 .scl_low = 5000, 1141 .hold_start = 4000, 1142 .setup_start = 4800, 1143 .setup_stop = 4000, 1144 .setup_data = 250, 1145 .sda_rise = 50, 1146 .sda_fall = 50, 1147 .scl_rise = 50, 1148 .scl_fall = 50, 1149 .hold_data = 300, 1150 .buf = 20000, 1151 .thigh_max = 5000, 1152 .timeout = 106500 1153 }, 1154 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1155 .scl_high = 1011, 1156 .scl_low = 1300, 1157 .hold_start = 600, 1158 .setup_start = 700, 1159 .setup_stop = 600, 1160 .setup_data = 100, 1161 .sda_rise = 50, 1162 .sda_fall = 50, 1163 .scl_rise = 50, 1164 .scl_fall = 50, 1165 .hold_data = 300, 1166 .buf = 20000, 1167 .thigh_max = 5000, 1168 .timeout = 106500 1169 }, 1170 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1171 .scl_high = 600, 1172 .scl_low = 1300, 1173 .hold_start = 600, 1174 .setup_start = 600, 1175 .setup_stop = 600, 1176 .setup_data = 100, 1177 .sda_rise = 50, 1178 .sda_fall = 50, 1179 .scl_rise = 50, 1180 .scl_fall = 50, 1181 .hold_data = 300, 1182 .buf = 20000, 1183 .thigh_max = 5000, 1184 .timeout = 106500 1185 } 1186 }; 1187 1188 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1189 struct mlxbf_i2c_priv *priv) 1190 { 1191 enum mlxbf_i2c_timings_config config_idx; 1192 struct device *dev = &pdev->dev; 1193 u32 config_khz; 1194 1195 int ret; 1196 1197 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1198 if (ret < 0) 1199 config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1200 1201 switch (config_khz) { 1202 default: 1203 /* Default settings is 100 KHz. */ 1204 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1205 config_khz); 1206 fallthrough; 1207 case I2C_MAX_STANDARD_MODE_FREQ: 1208 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1209 break; 1210 1211 case I2C_MAX_FAST_MODE_FREQ: 1212 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1213 break; 1214 1215 case I2C_MAX_FAST_MODE_PLUS_FREQ: 1216 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1217 break; 1218 } 1219 1220 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1221 1222 return 0; 1223 } 1224 1225 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1226 struct mlxbf_i2c_priv *priv) 1227 { 1228 struct mlxbf_i2c_resource *gpio_res; 1229 struct device *dev = &pdev->dev; 1230 struct resource *params; 1231 resource_size_t size; 1232 1233 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1234 if (!gpio_res) 1235 return -EPERM; 1236 1237 /* 1238 * The GPIO region in TYU space is shared among I2C busses. 1239 * This function MUST be serialized to avoid racing when 1240 * claiming the memory region and/or setting up the GPIO. 1241 */ 1242 lockdep_assert_held(gpio_res->lock); 1243 1244 /* Check whether the memory map exist. */ 1245 if (gpio_res->io) 1246 return 0; 1247 1248 params = gpio_res->params; 1249 size = resource_size(params); 1250 1251 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1252 return -EFAULT; 1253 1254 gpio_res->io = devm_ioremap(dev, params->start, size); 1255 if (!gpio_res->io) { 1256 devm_release_mem_region(dev, params->start, size); 1257 return -ENOMEM; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1264 struct mlxbf_i2c_priv *priv) 1265 { 1266 struct mlxbf_i2c_resource *gpio_res; 1267 struct device *dev = &pdev->dev; 1268 struct resource *params; 1269 1270 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1271 if (!gpio_res) 1272 return 0; 1273 1274 mutex_lock(gpio_res->lock); 1275 1276 if (gpio_res->io) { 1277 /* Release the GPIO resource. */ 1278 params = gpio_res->params; 1279 devm_iounmap(dev, gpio_res->io); 1280 devm_release_mem_region(dev, params->start, 1281 resource_size(params)); 1282 } 1283 1284 mutex_unlock(gpio_res->lock); 1285 1286 return 0; 1287 } 1288 1289 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1290 struct mlxbf_i2c_priv *priv) 1291 { 1292 struct mlxbf_i2c_resource *corepll_res; 1293 struct device *dev = &pdev->dev; 1294 struct resource *params; 1295 resource_size_t size; 1296 1297 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1298 MLXBF_I2C_COREPLL_RES); 1299 if (!corepll_res) 1300 return -EPERM; 1301 1302 /* 1303 * The COREPLL region in TYU space is shared among I2C busses. 1304 * This function MUST be serialized to avoid racing when 1305 * claiming the memory region. 1306 */ 1307 lockdep_assert_held(corepll_res->lock); 1308 1309 /* Check whether the memory map exist. */ 1310 if (corepll_res->io) 1311 return 0; 1312 1313 params = corepll_res->params; 1314 size = resource_size(params); 1315 1316 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1317 return -EFAULT; 1318 1319 corepll_res->io = devm_ioremap(dev, params->start, size); 1320 if (!corepll_res->io) { 1321 devm_release_mem_region(dev, params->start, size); 1322 return -ENOMEM; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1329 struct mlxbf_i2c_priv *priv) 1330 { 1331 struct mlxbf_i2c_resource *corepll_res; 1332 struct device *dev = &pdev->dev; 1333 struct resource *params; 1334 1335 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1336 MLXBF_I2C_COREPLL_RES); 1337 1338 mutex_lock(corepll_res->lock); 1339 1340 if (corepll_res->io) { 1341 /* Release the CorePLL resource. */ 1342 params = corepll_res->params; 1343 devm_iounmap(dev, corepll_res->io); 1344 devm_release_mem_region(dev, params->start, 1345 resource_size(params)); 1346 } 1347 1348 mutex_unlock(corepll_res->lock); 1349 1350 return 0; 1351 } 1352 1353 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1354 struct mlxbf_i2c_priv *priv) 1355 { 1356 struct mlxbf_i2c_resource *gpio_res; 1357 struct device *dev = &pdev->dev; 1358 u32 config_reg; 1359 int ret; 1360 1361 /* This configuration is only needed for BlueField 1. */ 1362 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1363 return 0; 1364 1365 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1366 if (!gpio_res) 1367 return -EPERM; 1368 1369 /* 1370 * The GPIO region in TYU space is shared among I2C busses. 1371 * This function MUST be serialized to avoid racing when 1372 * claiming the memory region and/or setting up the GPIO. 1373 */ 1374 1375 mutex_lock(gpio_res->lock); 1376 1377 ret = mlxbf_i2c_get_gpio(pdev, priv); 1378 if (ret < 0) { 1379 dev_err(dev, "Failed to get gpio resource"); 1380 mutex_unlock(gpio_res->lock); 1381 return ret; 1382 } 1383 1384 /* 1385 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1386 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1387 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1388 * instead of HW_OE. 1389 * For now, we do not reset the GPIO state when the driver is removed. 1390 * First, it is not necessary to disable the bus since we are using 1391 * the same busses. Then, some busses might be shared among Linux and 1392 * platform firmware; disabling the bus might compromise the system 1393 * functionality. 1394 */ 1395 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1396 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1397 config_reg); 1398 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1399 1400 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1401 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1402 config_reg); 1403 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1404 1405 mutex_unlock(gpio_res->lock); 1406 1407 return 0; 1408 } 1409 1410 static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1411 { 1412 u64 core_frequency, pad_frequency; 1413 u8 core_od, core_r; 1414 u32 corepll_val; 1415 u16 core_f; 1416 1417 pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1418 1419 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1420 1421 /* Get Core PLL configuration bits. */ 1422 core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) & 1423 MLXBF_I2C_COREPLL_CORE_F_TYU_MASK; 1424 core_od = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT) & 1425 MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK; 1426 core_r = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT) & 1427 MLXBF_I2C_COREPLL_CORE_R_TYU_MASK; 1428 1429 /* 1430 * Compute PLL output frequency as follow: 1431 * 1432 * CORE_F + 1 1433 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1434 * (CORE_R + 1) * (CORE_OD + 1) 1435 * 1436 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1437 * and PadFrequency, respectively. 1438 */ 1439 core_frequency = pad_frequency * (++core_f); 1440 core_frequency /= (++core_r) * (++core_od); 1441 1442 return core_frequency; 1443 } 1444 1445 static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1446 { 1447 u32 corepll_reg1_val, corepll_reg2_val; 1448 u64 corepll_frequency, pad_frequency; 1449 u8 core_od, core_r; 1450 u32 core_f; 1451 1452 pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1453 1454 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1455 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1456 1457 /* Get Core PLL configuration bits */ 1458 core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) & 1459 MLXBF_I2C_COREPLL_CORE_F_YU_MASK; 1460 core_r = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT) & 1461 MLXBF_I2C_COREPLL_CORE_R_YU_MASK; 1462 core_od = rol32(corepll_reg2_val, MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT) & 1463 MLXBF_I2C_COREPLL_CORE_OD_YU_MASK; 1464 1465 /* 1466 * Compute PLL output frequency as follow: 1467 * 1468 * CORE_F / 16384 1469 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1470 * (CORE_R + 1) * (CORE_OD + 1) 1471 * 1472 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1473 * and PadFrequency, respectively. 1474 */ 1475 corepll_frequency = (pad_frequency * core_f) / MLNXBF_I2C_COREPLL_CONST; 1476 corepll_frequency /= (++core_r) * (++core_od); 1477 1478 return corepll_frequency; 1479 } 1480 1481 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1482 struct mlxbf_i2c_priv *priv) 1483 { 1484 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1485 struct mlxbf_i2c_resource *corepll_res; 1486 struct device *dev = &pdev->dev; 1487 u64 *freq = &priv->frequency; 1488 int ret; 1489 1490 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1491 MLXBF_I2C_COREPLL_RES); 1492 if (!corepll_res) 1493 return -EPERM; 1494 1495 /* 1496 * First, check whether the TYU core Clock frequency is set. 1497 * The TYU core frequency is the same for all I2C busses; when 1498 * the first device gets probed the frequency is determined and 1499 * stored into a globally visible variable. So, first of all, 1500 * check whether the frequency is already set. Here, we assume 1501 * that the frequency is expected to be greater than 0. 1502 */ 1503 mutex_lock(corepll_res->lock); 1504 if (!mlxbf_i2c_corepll_frequency) { 1505 if (!chip->calculate_freq) { 1506 mutex_unlock(corepll_res->lock); 1507 return -EPERM; 1508 } 1509 1510 ret = mlxbf_i2c_get_corepll(pdev, priv); 1511 if (ret < 0) { 1512 dev_err(dev, "Failed to get corePLL resource"); 1513 mutex_unlock(corepll_res->lock); 1514 return ret; 1515 } 1516 1517 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1518 } 1519 mutex_unlock(corepll_res->lock); 1520 1521 *freq = mlxbf_i2c_corepll_frequency; 1522 1523 return 0; 1524 } 1525 1526 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) 1527 { 1528 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; 1529 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; 1530 bool avail, disabled; 1531 1532 disabled = false; 1533 avail = false; 1534 1535 if (!priv) 1536 return -EPERM; 1537 1538 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1539 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1540 1541 /* 1542 * Read the slave registers. There are 4 * 32-bit slave registers. 1543 * Each slave register can hold up to 4 * 8-bit slave configuration 1544 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1545 */ 1546 for (reg = 0; reg < reg_cnt; reg++) { 1547 slave_reg = readl(priv->smbus->io + 1548 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1549 /* 1550 * Each register holds 4 slave addresses. So, we have to keep 1551 * the byte order consistent with the value read in order to 1552 * update the register correctly, if needed. 1553 */ 1554 slave_reg_tmp = slave_reg; 1555 for (byte = 0; byte < 4; byte++) { 1556 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1557 1558 /* 1559 * Mark the first available slave address slot, i.e. its 1560 * enabled bit should be unset. This slot might be used 1561 * later on to register our slave. 1562 */ 1563 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { 1564 avail = true; 1565 reg_avail = reg; 1566 byte_avail = byte; 1567 slave_reg_avail = slave_reg; 1568 } 1569 1570 /* 1571 * Parse slave address bytes and check whether the 1572 * slave address already exists and it's enabled, 1573 * i.e. most significant bit is set. 1574 */ 1575 if ((addr_tmp & slave_addr_mask) == addr) { 1576 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) 1577 return 0; 1578 disabled = true; 1579 break; 1580 } 1581 1582 /* Parse next byte. */ 1583 slave_reg_tmp >>= 8; 1584 } 1585 1586 /* Exit the loop if the slave address is found. */ 1587 if (disabled) 1588 break; 1589 } 1590 1591 if (!avail && !disabled) 1592 return -EINVAL; /* No room for a new slave address. */ 1593 1594 if (avail && !disabled) { 1595 reg = reg_avail; 1596 byte = byte_avail; 1597 /* Set the slave address. */ 1598 slave_reg_avail &= ~(slave_addr_mask << (byte * 8)); 1599 slave_reg_avail |= addr << (byte * 8); 1600 slave_reg = slave_reg_avail; 1601 } 1602 1603 /* Enable the slave address and update the register. */ 1604 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1605 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1606 reg * 0x4); 1607 1608 return 0; 1609 } 1610 1611 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) 1612 { 1613 u32 slave_reg, slave_reg_tmp, slave_addr_mask; 1614 u8 addr, addr_tmp, reg, reg_cnt, slave_byte; 1615 struct i2c_client *client = priv->slave; 1616 bool exist; 1617 1618 exist = false; 1619 1620 addr = client->addr; 1621 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1622 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1623 1624 /* 1625 * Read the slave registers. There are 4 * 32-bit slave registers. 1626 * Each slave register can hold up to 4 * 8-bit slave configuration 1627 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1628 */ 1629 for (reg = 0; reg < reg_cnt; reg++) { 1630 slave_reg = readl(priv->smbus->io + 1631 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1632 1633 /* Check whether the address slots are empty. */ 1634 if (slave_reg == 0) 1635 continue; 1636 1637 /* 1638 * Each register holds 4 slave addresses. So, we have to keep 1639 * the byte order consistent with the value read in order to 1640 * update the register correctly, if needed. 1641 */ 1642 slave_reg_tmp = slave_reg; 1643 slave_byte = 0; 1644 while (slave_reg_tmp != 0) { 1645 addr_tmp = slave_reg_tmp & slave_addr_mask; 1646 /* 1647 * Parse slave address bytes and check whether the 1648 * slave address already exists. 1649 */ 1650 if (addr_tmp == addr) { 1651 exist = true; 1652 break; 1653 } 1654 1655 /* Parse next byte. */ 1656 slave_reg_tmp >>= 8; 1657 slave_byte += 1; 1658 } 1659 1660 /* Exit the loop if the slave address is found. */ 1661 if (exist) 1662 break; 1663 } 1664 1665 if (!exist) 1666 return 0; /* Slave is not registered, nothing to do. */ 1667 1668 /* Cleanup the slave address slot. */ 1669 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1670 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1671 reg * 0x4); 1672 1673 return 0; 1674 } 1675 1676 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1677 struct mlxbf_i2c_priv *priv) 1678 { 1679 struct mlxbf_i2c_resource *coalesce_res; 1680 struct resource *params; 1681 resource_size_t size; 1682 int ret = 0; 1683 1684 /* 1685 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1686 * resource in the next generations of BlueField. 1687 */ 1688 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1689 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1690 MLXBF_I2C_COALESCE_RES); 1691 if (!coalesce_res) 1692 return -EPERM; 1693 1694 /* 1695 * The Cause Coalesce group in TYU space is shared among 1696 * I2C busses. This function MUST be serialized to avoid 1697 * racing when claiming the memory region. 1698 */ 1699 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1700 1701 /* Check whether the memory map exist. */ 1702 if (coalesce_res->io) { 1703 priv->coalesce = coalesce_res; 1704 return 0; 1705 } 1706 1707 params = coalesce_res->params; 1708 size = resource_size(params); 1709 1710 if (!request_mem_region(params->start, size, params->name)) 1711 return -EFAULT; 1712 1713 coalesce_res->io = ioremap(params->start, size); 1714 if (!coalesce_res->io) { 1715 release_mem_region(params->start, size); 1716 return -ENOMEM; 1717 } 1718 1719 priv->coalesce = coalesce_res; 1720 1721 } else { 1722 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1723 MLXBF_I2C_COALESCE_RES); 1724 } 1725 1726 return ret; 1727 } 1728 1729 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1730 struct mlxbf_i2c_priv *priv) 1731 { 1732 struct mlxbf_i2c_resource *coalesce_res; 1733 struct device *dev = &pdev->dev; 1734 struct resource *params; 1735 resource_size_t size; 1736 1737 coalesce_res = priv->coalesce; 1738 1739 if (coalesce_res->io) { 1740 params = coalesce_res->params; 1741 size = resource_size(params); 1742 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1743 mutex_lock(coalesce_res->lock); 1744 iounmap(coalesce_res->io); 1745 release_mem_region(params->start, size); 1746 mutex_unlock(coalesce_res->lock); 1747 } else { 1748 devm_release_mem_region(dev, params->start, size); 1749 } 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1756 struct mlxbf_i2c_priv *priv) 1757 { 1758 struct device *dev = &pdev->dev; 1759 u32 int_reg; 1760 int ret; 1761 1762 /* Reset FSM. */ 1763 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1764 1765 /* 1766 * Enable slave cause interrupt bits. Drive 1767 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1768 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1769 * masters issue a Read and Write, respectively. But, clear all 1770 * interrupts first. 1771 */ 1772 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1773 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1774 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1775 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1776 1777 /* Finally, set the 'ready' bit to start handling transactions. */ 1778 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1779 1780 /* Initialize the cause coalesce resource. */ 1781 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1782 if (ret < 0) { 1783 dev_err(dev, "failed to initialize cause coalesce\n"); 1784 return ret; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1791 bool *write) 1792 { 1793 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1794 u32 coalesce0_reg, cause_reg; 1795 u8 slave_shift, is_set; 1796 1797 *write = false; 1798 *read = false; 1799 1800 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1801 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1802 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1803 1804 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1805 is_set = coalesce0_reg & (1 << slave_shift); 1806 1807 if (!is_set) 1808 return false; 1809 1810 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1811 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1812 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1813 *read = true; 1814 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1815 *write = true; 1816 1817 /* Clear cause bits. */ 1818 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1819 1820 return true; 1821 } 1822 1823 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, 1824 u32 timeout) 1825 { 1826 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL; 1827 u32 addr = MLXBF_I2C_CAUSE_ARBITER; 1828 1829 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout)) 1830 return true; 1831 1832 return false; 1833 } 1834 1835 /* Send byte to 'external' smbus master. */ 1836 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1837 { 1838 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1839 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size; 1840 struct i2c_client *slave = priv->slave; 1841 u32 control32, data32; 1842 int ret; 1843 1844 if (!slave) 1845 return -EINVAL; 1846 1847 addr = 0; 1848 byte = 0; 1849 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; 1850 1851 /* 1852 * Read bytes received from the external master. These bytes should 1853 * be located in the first data descriptor register of the slave GW. 1854 * These bytes are the slave address byte and the internal register 1855 * address, if supplied. 1856 */ 1857 if (recv_bytes > 0) { 1858 data32 = ioread32be(priv->smbus->io + 1859 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1860 1861 /* Parse the received bytes. */ 1862 switch (recv_bytes) { 1863 case 2: 1864 byte = (data32 >> 8) & GENMASK(7, 0); 1865 fallthrough; 1866 case 1: 1867 addr = (data32 & GENMASK(7, 0)) >> 1; 1868 } 1869 1870 /* Check whether it's our slave address. */ 1871 if (slave->addr != addr) 1872 return -EINVAL; 1873 } 1874 1875 /* 1876 * I2C read transactions may start by a WRITE followed by a READ. 1877 * Indeed, most slave devices would expect the internal address 1878 * following the slave address byte. So, write that byte first, 1879 * and then, send the requested data bytes to the master. 1880 */ 1881 if (recv_bytes > 1) { 1882 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1883 value = byte; 1884 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1885 &value); 1886 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1887 1888 if (ret < 0) 1889 return ret; 1890 } 1891 1892 /* 1893 * Now, send data to the master; currently, the driver supports 1894 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the 1895 * hardware can send up to 128 bytes per transfer. That is the 1896 * size of its data registers. 1897 */ 1898 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1899 1900 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { 1901 data_desc[byte_cnt] = value; 1902 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1903 } 1904 1905 /* Send a stop condition to the backend. */ 1906 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1907 1908 /* Handle the actual transfer. */ 1909 1910 /* Set the number of bytes to write to master. */ 1911 write_size = (byte_cnt - 1) & 0x7f; 1912 1913 /* Write data to Slave GW data descriptor. */ 1914 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1915 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1916 1917 pec_en = 0; /* Disable PEC since it is not supported. */ 1918 1919 /* Prepare control word. */ 1920 control32 = MLXBF_I2C_SLAVE_ENABLE; 1921 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1922 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1923 1924 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1925 1926 /* 1927 * Wait until the transfer is completed; the driver will wait 1928 * until the GW is idle, a cause will rise on fall of GW busy. 1929 */ 1930 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1931 1932 /* Release the Slave GW. */ 1933 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1934 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1935 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1936 1937 return 0; 1938 } 1939 1940 /* Receive bytes from 'external' smbus master. */ 1941 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1942 { 1943 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1944 struct i2c_client *slave = priv->slave; 1945 u8 value, byte, addr; 1946 int ret = 0; 1947 1948 if (!slave) 1949 return -EINVAL; 1950 1951 /* Read data from Slave GW data descriptor. */ 1952 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1953 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1954 1955 /* Check whether its our slave address. */ 1956 addr = data_desc[0] >> 1; 1957 if (slave->addr != addr) 1958 return -EINVAL; 1959 1960 /* 1961 * Notify the slave backend; another I2C master wants to write data 1962 * to us. This event is sent once the slave address and the write bit 1963 * is detected. 1964 */ 1965 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1966 1967 /* Send the received data to the slave backend. */ 1968 for (byte = 1; byte < recv_bytes; byte++) { 1969 value = data_desc[byte]; 1970 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1971 &value); 1972 if (ret < 0) 1973 break; 1974 } 1975 1976 /* Send a stop condition to the backend. */ 1977 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1978 1979 /* Release the Slave GW. */ 1980 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1981 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1982 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1983 1984 return ret; 1985 } 1986 1987 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) 1988 { 1989 struct mlxbf_i2c_priv *priv = ptr; 1990 bool read, write, irq_is_set; 1991 u32 rw_bytes_reg; 1992 u8 recv_bytes; 1993 1994 /* 1995 * Read TYU interrupt register and determine the source of the 1996 * interrupt. Based on the source of the interrupt one of the 1997 * following actions are performed: 1998 * - Receive data and send response to master. 1999 * - Send data and release slave GW. 2000 * 2001 * Handle read/write transaction only. CRmaster and Iarp requests 2002 * are ignored for now. 2003 */ 2004 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 2005 if (!irq_is_set || (!read && !write)) { 2006 /* Nothing to do here, interrupt was not from this device. */ 2007 return IRQ_NONE; 2008 } 2009 2010 /* 2011 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 2012 * bytes from/to master. These are defined by 8-bits each. If the lower 2013 * 8 bits are set, then the master expect to read N bytes from the 2014 * slave, if the higher 8 bits are sent then the slave expect N bytes 2015 * from the master. 2016 */ 2017 rw_bytes_reg = readl(priv->smbus->io + 2018 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2019 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2020 2021 /* 2022 * For now, the slave supports 128 bytes transfer. Discard remaining 2023 * data bytes if the master wrote more than 2024 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2025 * data descriptor. 2026 * 2027 * Note that we will never expect to transfer more than 128 bytes; as 2028 * specified in the SMBus standard, block transactions cannot exceed 2029 * 32 bytes. 2030 */ 2031 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2032 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2033 2034 if (read) 2035 mlxbf_smbus_irq_send(priv, recv_bytes); 2036 else 2037 mlxbf_smbus_irq_recv(priv, recv_bytes); 2038 2039 return IRQ_HANDLED; 2040 } 2041 2042 /* Return negative errno on error. */ 2043 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2044 unsigned short flags, char read_write, 2045 u8 command, int size, 2046 union i2c_smbus_data *data) 2047 { 2048 struct mlxbf_i2c_smbus_request request = { 0 }; 2049 struct mlxbf_i2c_priv *priv; 2050 bool read, pec; 2051 u8 byte_cnt; 2052 2053 request.slave = addr; 2054 2055 read = (read_write == I2C_SMBUS_READ); 2056 pec = flags & I2C_FUNC_SMBUS_PEC; 2057 2058 switch (size) { 2059 case I2C_SMBUS_QUICK: 2060 mlxbf_i2c_smbus_quick_command(&request, read); 2061 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2062 break; 2063 2064 case I2C_SMBUS_BYTE: 2065 mlxbf_i2c_smbus_byte_func(&request, 2066 read ? &data->byte : &command, read, 2067 pec); 2068 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2069 read ? "read" : "write", addr); 2070 break; 2071 2072 case I2C_SMBUS_BYTE_DATA: 2073 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2074 read, pec); 2075 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2076 read ? "read" : "write", command, addr); 2077 break; 2078 2079 case I2C_SMBUS_WORD_DATA: 2080 mlxbf_i2c_smbus_data_word_func(&request, &command, 2081 (u8 *)&data->word, read, pec); 2082 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2083 read ? "read" : "write", command, addr); 2084 break; 2085 2086 case I2C_SMBUS_I2C_BLOCK_DATA: 2087 byte_cnt = data->block[0]; 2088 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2089 &byte_cnt, read, pec); 2090 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2091 read ? "read" : "write", byte_cnt, command, addr); 2092 break; 2093 2094 case I2C_SMBUS_BLOCK_DATA: 2095 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2096 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2097 &byte_cnt, read, pec); 2098 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2099 read ? "read" : "write", byte_cnt, command, addr); 2100 break; 2101 2102 case I2C_FUNC_SMBUS_PROC_CALL: 2103 mlxbf_i2c_smbus_process_call_func(&request, &command, 2104 (u8 *)&data->word, pec); 2105 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2106 command, addr); 2107 break; 2108 2109 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2110 byte_cnt = data->block[0]; 2111 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2112 data->block, &byte_cnt, 2113 pec); 2114 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2115 byte_cnt, addr); 2116 break; 2117 2118 default: 2119 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2120 size); 2121 return -EOPNOTSUPP; 2122 } 2123 2124 priv = i2c_get_adapdata(adap); 2125 2126 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2127 } 2128 2129 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2130 { 2131 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2132 int ret; 2133 2134 if (priv->slave) 2135 return -EBUSY; 2136 2137 /* 2138 * Do not support ten bit chip address and do not use Packet Error 2139 * Checking (PEC). 2140 */ 2141 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) 2142 return -EAFNOSUPPORT; 2143 2144 ret = mlxbf_slave_enable(priv, slave->addr); 2145 if (ret < 0) 2146 return ret; 2147 2148 priv->slave = slave; 2149 2150 return 0; 2151 } 2152 2153 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2154 { 2155 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2156 int ret; 2157 2158 WARN_ON(!priv->slave); 2159 2160 /* Unregister slave, i.e. disable the slave address in hardware. */ 2161 ret = mlxbf_slave_disable(priv); 2162 if (ret < 0) 2163 return ret; 2164 2165 priv->slave = NULL; 2166 2167 return 0; 2168 } 2169 2170 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2171 { 2172 return MLXBF_I2C_FUNC_ALL; 2173 } 2174 2175 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2176 [MLXBF_I2C_CHIP_TYPE_1] = { 2177 .type = MLXBF_I2C_CHIP_TYPE_1, 2178 .shared_res = { 2179 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2180 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2181 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2182 }, 2183 .calculate_freq = mlxbf_calculate_freq_from_tyu 2184 }, 2185 [MLXBF_I2C_CHIP_TYPE_2] = { 2186 .type = MLXBF_I2C_CHIP_TYPE_2, 2187 .shared_res = { 2188 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2189 }, 2190 .calculate_freq = mlxbf_calculate_freq_from_yu 2191 } 2192 }; 2193 2194 static const struct i2c_algorithm mlxbf_i2c_algo = { 2195 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2196 .functionality = mlxbf_i2c_functionality, 2197 .reg_slave = mlxbf_i2c_reg_slave, 2198 .unreg_slave = mlxbf_i2c_unreg_slave, 2199 }; 2200 2201 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2202 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2203 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2204 }; 2205 2206 static const struct of_device_id mlxbf_i2c_dt_ids[] = { 2207 { 2208 .compatible = "mellanox,i2c-mlxbf1", 2209 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] 2210 }, 2211 { 2212 .compatible = "mellanox,i2c-mlxbf2", 2213 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] 2214 }, 2215 {}, 2216 }; 2217 2218 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2219 2220 #ifdef CONFIG_ACPI 2221 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2222 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2223 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2224 {}, 2225 }; 2226 2227 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2228 2229 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2230 { 2231 const struct acpi_device_id *aid; 2232 struct acpi_device *adev; 2233 unsigned long bus_id = 0; 2234 const char *uid; 2235 int ret; 2236 2237 if (acpi_disabled) 2238 return -ENOENT; 2239 2240 adev = ACPI_COMPANION(dev); 2241 if (!adev) 2242 return -ENXIO; 2243 2244 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2245 if (!aid) 2246 return -ENODEV; 2247 2248 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2249 2250 uid = acpi_device_uid(adev); 2251 if (!uid || !(*uid)) { 2252 dev_err(dev, "Cannot retrieve UID\n"); 2253 return -ENODEV; 2254 } 2255 2256 ret = kstrtoul(uid, 0, &bus_id); 2257 if (!ret) 2258 priv->bus = bus_id; 2259 2260 return ret; 2261 } 2262 #else 2263 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2264 { 2265 return -ENOENT; 2266 } 2267 #endif /* CONFIG_ACPI */ 2268 2269 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2270 { 2271 const struct of_device_id *oid; 2272 int bus_id = -1; 2273 2274 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 2275 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node); 2276 if (!oid) 2277 return -ENODEV; 2278 2279 priv->chip = oid->data; 2280 2281 bus_id = of_alias_get_id(dev->of_node, "i2c"); 2282 if (bus_id >= 0) 2283 priv->bus = bus_id; 2284 } 2285 2286 if (bus_id < 0) { 2287 dev_err(dev, "Cannot get bus id"); 2288 return bus_id; 2289 } 2290 2291 return 0; 2292 } 2293 2294 static int mlxbf_i2c_probe(struct platform_device *pdev) 2295 { 2296 struct device *dev = &pdev->dev; 2297 struct mlxbf_i2c_priv *priv; 2298 struct i2c_adapter *adap; 2299 int irq, ret; 2300 2301 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2302 if (!priv) 2303 return -ENOMEM; 2304 2305 ret = mlxbf_i2c_acpi_probe(dev, priv); 2306 if (ret < 0 && ret != -ENOENT && ret != -ENXIO) 2307 ret = mlxbf_i2c_of_probe(dev, priv); 2308 2309 if (ret < 0) 2310 return ret; 2311 2312 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2313 MLXBF_I2C_SMBUS_RES); 2314 if (ret < 0) { 2315 dev_err(dev, "Cannot fetch smbus resource info"); 2316 return ret; 2317 } 2318 2319 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2320 MLXBF_I2C_MST_CAUSE_RES); 2321 if (ret < 0) { 2322 dev_err(dev, "Cannot fetch cause master resource info"); 2323 return ret; 2324 } 2325 2326 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2327 MLXBF_I2C_SLV_CAUSE_RES); 2328 if (ret < 0) { 2329 dev_err(dev, "Cannot fetch cause slave resource info"); 2330 return ret; 2331 } 2332 2333 adap = &priv->adap; 2334 adap->owner = THIS_MODULE; 2335 adap->class = I2C_CLASS_HWMON; 2336 adap->algo = &mlxbf_i2c_algo; 2337 adap->quirks = &mlxbf_i2c_quirks; 2338 adap->dev.parent = dev; 2339 adap->dev.of_node = dev->of_node; 2340 adap->nr = priv->bus; 2341 2342 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2343 i2c_set_adapdata(adap, priv); 2344 2345 /* Read Core PLL frequency. */ 2346 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2347 if (ret < 0) { 2348 dev_err(dev, "cannot get core clock frequency\n"); 2349 /* Set to default value. */ 2350 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2351 } 2352 2353 /* 2354 * Initialize master. 2355 * Note that a physical bus might be shared among Linux and firmware 2356 * (e.g., ATF). Thus, the bus should be initialized and ready and 2357 * bus initialization would be unnecessary. This requires additional 2358 * knowledge about physical busses. But, since an extra initialization 2359 * does not really hurt, then keep the code as is. 2360 */ 2361 ret = mlxbf_i2c_init_master(pdev, priv); 2362 if (ret < 0) { 2363 dev_err(dev, "failed to initialize smbus master %d", 2364 priv->bus); 2365 return ret; 2366 } 2367 2368 mlxbf_i2c_init_timings(pdev, priv); 2369 2370 mlxbf_i2c_init_slave(pdev, priv); 2371 2372 irq = platform_get_irq(pdev, 0); 2373 if (irq < 0) 2374 return irq; 2375 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2376 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2377 dev_name(dev), priv); 2378 if (ret < 0) { 2379 dev_err(dev, "Cannot get irq %d\n", irq); 2380 return ret; 2381 } 2382 2383 priv->irq = irq; 2384 2385 platform_set_drvdata(pdev, priv); 2386 2387 ret = i2c_add_numbered_adapter(adap); 2388 if (ret < 0) 2389 return ret; 2390 2391 mutex_lock(&mlxbf_i2c_bus_lock); 2392 mlxbf_i2c_bus_count++; 2393 mutex_unlock(&mlxbf_i2c_bus_lock); 2394 2395 return 0; 2396 } 2397 2398 static int mlxbf_i2c_remove(struct platform_device *pdev) 2399 { 2400 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2401 struct device *dev = &pdev->dev; 2402 struct resource *params; 2403 2404 params = priv->smbus->params; 2405 devm_release_mem_region(dev, params->start, resource_size(params)); 2406 2407 params = priv->mst_cause->params; 2408 devm_release_mem_region(dev, params->start, resource_size(params)); 2409 2410 params = priv->slv_cause->params; 2411 devm_release_mem_region(dev, params->start, resource_size(params)); 2412 2413 /* 2414 * Release shared resources. This should be done when releasing 2415 * the I2C controller. 2416 */ 2417 mutex_lock(&mlxbf_i2c_bus_lock); 2418 if (--mlxbf_i2c_bus_count == 0) { 2419 mlxbf_i2c_release_coalesce(pdev, priv); 2420 mlxbf_i2c_release_corepll(pdev, priv); 2421 mlxbf_i2c_release_gpio(pdev, priv); 2422 } 2423 mutex_unlock(&mlxbf_i2c_bus_lock); 2424 2425 devm_free_irq(dev, priv->irq, priv); 2426 2427 i2c_del_adapter(&priv->adap); 2428 2429 return 0; 2430 } 2431 2432 static struct platform_driver mlxbf_i2c_driver = { 2433 .probe = mlxbf_i2c_probe, 2434 .remove = mlxbf_i2c_remove, 2435 .driver = { 2436 .name = "i2c-mlxbf", 2437 .of_match_table = mlxbf_i2c_dt_ids, 2438 #ifdef CONFIG_ACPI 2439 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2440 #endif /* CONFIG_ACPI */ 2441 }, 2442 }; 2443 2444 static int __init mlxbf_i2c_init(void) 2445 { 2446 mutex_init(&mlxbf_i2c_coalesce_lock); 2447 mutex_init(&mlxbf_i2c_corepll_lock); 2448 mutex_init(&mlxbf_i2c_gpio_lock); 2449 2450 mutex_init(&mlxbf_i2c_bus_lock); 2451 2452 return platform_driver_register(&mlxbf_i2c_driver); 2453 } 2454 module_init(mlxbf_i2c_init); 2455 2456 static void __exit mlxbf_i2c_exit(void) 2457 { 2458 platform_driver_unregister(&mlxbf_i2c_driver); 2459 2460 mutex_destroy(&mlxbf_i2c_bus_lock); 2461 2462 mutex_destroy(&mlxbf_i2c_gpio_lock); 2463 mutex_destroy(&mlxbf_i2c_corepll_lock); 2464 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2465 } 2466 module_exit(mlxbf_i2c_exit); 2467 2468 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2469 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2470 MODULE_LICENSE("GPL v2"); 2471