1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/string.h> 21 22 /* Defines what functionality is present. */ 23 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 24 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 25 26 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 27 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 28 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 29 I2C_FUNC_SMBUS_PROC_CALL) 30 31 #define MLXBF_I2C_FUNC_ALL \ 32 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 33 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 34 35 #define MLXBF_I2C_SMBUS_MAX 3 36 37 /* Shared resources info in BlueField platforms. */ 38 39 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 40 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 41 42 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 43 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 44 45 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 46 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 47 48 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 49 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 50 51 #define MLXBF_I2C_SHARED_RES_MAX 3 52 53 /* 54 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 55 * refer to their respective offsets relative to the corresponding 56 * memory-mapped region whose addresses are specified in either the DT or 57 * the ACPI tables or above. 58 */ 59 60 /* 61 * SMBus Master core clock frequency. Timing configurations are 62 * strongly dependent on the core clock frequency of the SMBus 63 * Master. Default value is set to 400MHz. 64 */ 65 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 66 /* Reference clock for Bluefield - 156 MHz. */ 67 #define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 68 69 /* Constant used to determine the PLL frequency. */ 70 #define MLNXBF_I2C_COREPLL_CONST 16384ULL 71 72 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL 73 74 /* PLL registers. */ 75 #define MLXBF_I2C_CORE_PLL_REG1 0x4 76 #define MLXBF_I2C_CORE_PLL_REG2 0x8 77 78 /* OR cause register. */ 79 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 80 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 81 82 /* Arbiter Cause Register. */ 83 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 84 85 /* 86 * Cause Status flags. Note that those bits might be considered 87 * as interrupt enabled bits. 88 */ 89 90 /* Transaction ended with STOP. */ 91 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 92 /* Master arbitration lost. */ 93 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 94 /* Unexpected start detected. */ 95 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 96 /* Unexpected stop detected. */ 97 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 98 /* Wait for transfer continuation. */ 99 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 100 /* Failed to generate STOP. */ 101 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 102 /* Failed to generate START. */ 103 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 104 /* Clock toggle completed. */ 105 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 106 /* Transfer timeout occurred. */ 107 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 108 /* Master busy bit reset. */ 109 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 110 111 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 112 113 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 114 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 115 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 116 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 117 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 118 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 119 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 120 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 121 122 /* 123 * Slave cause status flags. Note that those bits might be considered 124 * as interrupt enabled bits. 125 */ 126 127 /* Write transaction received successfully. */ 128 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 129 /* Read transaction received, waiting for response. */ 130 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 131 /* Slave busy bit reset. */ 132 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 133 134 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0) 135 136 /* Cause coalesce registers. */ 137 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 138 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04 139 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08 140 141 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX 142 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 143 144 /* Functional enable register. */ 145 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 146 /* Force OE enable register. */ 147 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 148 /* 149 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 150 * SDA/SCL lines: 151 * 152 * SMBUS GW0 -> bits[26:25] 153 * SMBUS GW1 -> bits[28:27] 154 * SMBUS GW2 -> bits[30:29] 155 */ 156 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 157 158 /* Note that gw_id can be 0,1 or 2. */ 159 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 160 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 161 162 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 163 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 164 165 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 166 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 167 168 /* SMBus timing parameters. */ 169 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 170 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 171 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 172 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 173 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 174 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 175 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 176 177 /* 178 * Defines SMBus operating frequency and core clock frequency. 179 * According to ADB files, default values are compliant to 100KHz SMBus 180 * @ 400MHz core clock. The driver should be able to calculate core 181 * frequency based on PLL parameters. 182 */ 183 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 184 185 /* Core PLL TYU configuration. */ 186 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3) 187 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16) 188 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20) 189 190 /* Core PLL YU configuration. */ 191 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 192 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 193 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26) 194 195 196 /* Core PLL frequency. */ 197 static u64 mlxbf_i2c_corepll_frequency; 198 199 /* SMBus Master GW. */ 200 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200 201 /* Number of bytes received and sent. */ 202 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300 203 /* Packet error check (PEC) value. */ 204 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304 205 /* Status bits (ACK/NACK/FW Timeout). */ 206 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308 207 /* SMbus Master Finite State Machine. */ 208 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310 209 210 /* 211 * When enabled, the master will issue a stop condition in case of 212 * timeout while waiting for FW response. 213 */ 214 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c 215 216 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 217 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 218 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 219 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 220 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 221 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 222 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 223 224 #define MLXBF_I2C_MASTER_ENABLE \ 225 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 226 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 227 228 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 229 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 230 231 #define MLXBF_I2C_MASTER_ENABLE_READ \ 232 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 233 234 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */ 235 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */ 236 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */ 237 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */ 238 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */ 239 240 /* SMBus master GW Data descriptor. */ 241 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280 242 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 243 244 /* Maximum bytes to read/write per SMBus transaction. */ 245 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 246 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 247 248 /* All bytes were transmitted. */ 249 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 250 /* NACK received. */ 251 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 252 /* Slave's byte count >128 bytes. */ 253 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 254 /* Timeout occurred. */ 255 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 256 257 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 258 259 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 260 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 261 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 262 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 263 264 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 265 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 266 267 /* SMBus slave GW. */ 268 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400 269 /* Number of bytes received and sent from/to master. */ 270 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500 271 /* Packet error check (PEC) value. */ 272 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504 273 /* SMBus slave Finite State Machine (FSM). */ 274 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510 275 /* 276 * Should be set when all raised causes handled, and cleared by HW on 277 * every new cause. 278 */ 279 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c 280 281 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 282 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 283 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 284 285 #define MLXBF_I2C_SLAVE_ENABLE \ 286 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 287 288 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 289 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 290 291 /* SMBus slave GW Data descriptor. */ 292 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480 293 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 294 295 /* SMbus slave configuration registers. */ 296 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514 297 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 298 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7 299 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 300 301 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \ 302 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) 303 304 /* 305 * Timeout is given in microsends. Note also that timeout handling is not 306 * exact. 307 */ 308 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 309 310 /* Encapsulates timing parameters. */ 311 struct mlxbf_i2c_timings { 312 u16 scl_high; /* Clock high period. */ 313 u16 scl_low; /* Clock low period. */ 314 u8 sda_rise; /* Data rise time. */ 315 u8 sda_fall; /* Data fall time. */ 316 u8 scl_rise; /* Clock rise time. */ 317 u8 scl_fall; /* Clock fall time. */ 318 u16 hold_start; /* Hold time after (REPEATED) START. */ 319 u16 hold_data; /* Data hold time. */ 320 u16 setup_start; /* REPEATED START condition setup time. */ 321 u16 setup_stop; /* STOP condition setup time. */ 322 u16 setup_data; /* Data setup time. */ 323 u16 pad; /* Padding. */ 324 u16 buf; /* Bus free time between STOP and START. */ 325 u16 thigh_max; /* Thigh max. */ 326 u32 timeout; /* Detect clock low timeout. */ 327 }; 328 329 enum { 330 MLXBF_I2C_F_READ = BIT(0), 331 MLXBF_I2C_F_WRITE = BIT(1), 332 MLXBF_I2C_F_NORESTART = BIT(3), 333 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 334 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 335 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 336 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 337 }; 338 339 struct mlxbf_i2c_smbus_operation { 340 u32 flags; 341 u32 length; /* Buffer length in bytes. */ 342 u8 *buffer; 343 }; 344 345 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 346 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 347 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 348 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 349 350 struct mlxbf_i2c_smbus_request { 351 u8 slave; 352 u8 operation_cnt; 353 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 354 }; 355 356 struct mlxbf_i2c_resource { 357 void __iomem *io; 358 struct resource *params; 359 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 360 u8 type; 361 }; 362 363 /* List of chip resources that are being accessed by the driver. */ 364 enum { 365 MLXBF_I2C_SMBUS_RES, 366 MLXBF_I2C_MST_CAUSE_RES, 367 MLXBF_I2C_SLV_CAUSE_RES, 368 MLXBF_I2C_COALESCE_RES, 369 MLXBF_I2C_COREPLL_RES, 370 MLXBF_I2C_GPIO_RES, 371 MLXBF_I2C_END_RES, 372 }; 373 374 /* Helper macro to define an I2C resource parameters. */ 375 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 376 { \ 377 .start = (addr), \ 378 .end = (addr) + (size) - 1, \ 379 .name = (str) \ 380 } 381 382 static struct resource mlxbf_i2c_coalesce_tyu_params = 383 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 384 MLXBF_I2C_COALESCE_TYU_SIZE, 385 "COALESCE_MEM"); 386 static struct resource mlxbf_i2c_corepll_tyu_params = 387 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 388 MLXBF_I2C_COREPLL_TYU_SIZE, 389 "COREPLL_MEM"); 390 static struct resource mlxbf_i2c_corepll_yu_params = 391 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 392 MLXBF_I2C_COREPLL_YU_SIZE, 393 "COREPLL_MEM"); 394 static struct resource mlxbf_i2c_gpio_tyu_params = 395 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 396 MLXBF_I2C_GPIO_TYU_SIZE, 397 "GPIO_MEM"); 398 399 static struct mutex mlxbf_i2c_coalesce_lock; 400 static struct mutex mlxbf_i2c_corepll_lock; 401 static struct mutex mlxbf_i2c_gpio_lock; 402 403 /* Mellanox BlueField chip type. */ 404 enum mlxbf_i2c_chip_type { 405 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 406 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */ 407 }; 408 409 struct mlxbf_i2c_chip_info { 410 enum mlxbf_i2c_chip_type type; 411 /* Chip shared resources that are being used by the I2C controller. */ 412 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 413 414 /* Callback to calculate the core PLL frequency. */ 415 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 416 }; 417 418 struct mlxbf_i2c_priv { 419 const struct mlxbf_i2c_chip_info *chip; 420 struct i2c_adapter adap; 421 struct mlxbf_i2c_resource *smbus; 422 struct mlxbf_i2c_resource *mst_cause; 423 struct mlxbf_i2c_resource *slv_cause; 424 struct mlxbf_i2c_resource *coalesce; 425 u64 frequency; /* Core frequency in Hz. */ 426 int bus; /* Physical bus identifier. */ 427 int irq; 428 struct i2c_client *slave; 429 }; 430 431 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 432 [MLXBF_I2C_CHIP_TYPE_1] = { 433 .params = &mlxbf_i2c_coalesce_tyu_params, 434 .lock = &mlxbf_i2c_coalesce_lock, 435 .type = MLXBF_I2C_COALESCE_RES 436 }, 437 {} 438 }; 439 440 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 441 [MLXBF_I2C_CHIP_TYPE_1] = { 442 .params = &mlxbf_i2c_corepll_tyu_params, 443 .lock = &mlxbf_i2c_corepll_lock, 444 .type = MLXBF_I2C_COREPLL_RES 445 }, 446 [MLXBF_I2C_CHIP_TYPE_2] = { 447 .params = &mlxbf_i2c_corepll_yu_params, 448 .lock = &mlxbf_i2c_corepll_lock, 449 .type = MLXBF_I2C_COREPLL_RES, 450 } 451 }; 452 453 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 454 [MLXBF_I2C_CHIP_TYPE_1] = { 455 .params = &mlxbf_i2c_gpio_tyu_params, 456 .lock = &mlxbf_i2c_gpio_lock, 457 .type = MLXBF_I2C_GPIO_RES 458 }, 459 {} 460 }; 461 462 static u8 mlxbf_i2c_bus_count; 463 464 static struct mutex mlxbf_i2c_bus_lock; 465 466 /* Polling frequency in microseconds. */ 467 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 468 469 #define MLXBF_I2C_SHIFT_0 0 470 #define MLXBF_I2C_SHIFT_8 8 471 #define MLXBF_I2C_SHIFT_16 16 472 #define MLXBF_I2C_SHIFT_24 24 473 474 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 475 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 476 477 /* 478 * Function to poll a set of bits at a specific address; it checks whether 479 * the bits are equal to zero when eq_zero is set to 'true', and not equal 480 * to zero when eq_zero is set to 'false'. 481 * Note that the timeout is given in microseconds. 482 */ 483 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask, 484 bool eq_zero, u32 timeout) 485 { 486 u32 bits; 487 488 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 489 490 do { 491 bits = readl(io + addr) & mask; 492 if (eq_zero ? bits == 0 : bits != 0) 493 return eq_zero ? 1 : bits; 494 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); 495 } while (timeout-- != 0); 496 497 return 0; 498 } 499 500 /* 501 * SW must make sure that the SMBus Master GW is idle before starting 502 * a transaction. Accordingly, this function polls the Master FSM stop 503 * bit; it returns false when the bit is asserted, true if not. 504 */ 505 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) 506 { 507 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK; 508 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM; 509 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT; 510 511 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout)) 512 return true; 513 514 return false; 515 } 516 517 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 518 u32 cause_status) 519 { 520 /* 521 * When transaction ended with STOP, all bytes were transmitted, 522 * and no NACK received, then the transaction ended successfully. 523 * On the other hand, when the GW is configured with the stop bit 524 * de-asserted then the SMBus expects the following GW configuration 525 * for transfer continuation. 526 */ 527 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 528 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 529 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 530 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 531 return true; 532 533 return false; 534 } 535 536 /* 537 * Poll SMBus master status and return transaction status, 538 * i.e. whether succeeded or failed. I2C and SMBus fault codes 539 * are returned as negative numbers from most calls, with zero 540 * or some positive number indicating a non-fault return. 541 */ 542 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 543 { 544 u32 master_status_bits; 545 u32 cause_status_bits; 546 547 /* 548 * GW busy bit is raised by the driver and cleared by the HW 549 * when the transaction is completed. The busy bit is a good 550 * indicator of transaction status. So poll the busy bit, and 551 * then read the cause and master status bits to determine if 552 * errors occurred during the transaction. 553 */ 554 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, 555 MLXBF_I2C_MASTER_BUSY_BIT, true, 556 MLXBF_I2C_SMBUS_TIMEOUT); 557 558 /* Read cause status bits. */ 559 cause_status_bits = readl(priv->mst_cause->io + 560 MLXBF_I2C_CAUSE_ARBITER); 561 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 562 563 /* 564 * Parse both Cause and Master GW bits, then return transaction status. 565 */ 566 567 master_status_bits = readl(priv->smbus->io + 568 MLXBF_I2C_SMBUS_MASTER_STATUS); 569 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 570 571 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 572 cause_status_bits)) 573 return 0; 574 575 /* 576 * In case of timeout on GW busy, the ISR will clear busy bit but 577 * transaction ended bits cause will not be set so the transaction 578 * fails. Then, we must check Master GW status bits. 579 */ 580 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 581 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 582 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 583 return -EIO; 584 585 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 586 return -EAGAIN; 587 588 return -ETIMEDOUT; 589 } 590 591 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 592 const u8 *data, u8 length, u32 addr) 593 { 594 u8 offset, aligned_length; 595 u32 data32; 596 597 aligned_length = round_up(length, 4); 598 599 /* 600 * Copy data bytes from 4-byte aligned source buffer. 601 * Data copied to the Master GW Data Descriptor MUST be shifted 602 * left so the data starts at the MSB of the descriptor registers 603 * as required by the underlying hardware. Enable byte swapping 604 * when writing data bytes to the 32 * 32-bit HW Data registers 605 * a.k.a Master GW Data Descriptor. 606 */ 607 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 608 data32 = *((u32 *)(data + offset)); 609 iowrite32be(data32, priv->smbus->io + addr + offset); 610 } 611 } 612 613 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 614 u8 *data, u8 length, u32 addr) 615 { 616 u32 data32, mask; 617 u8 byte, offset; 618 619 mask = sizeof(u32) - 1; 620 621 /* 622 * Data bytes in the Master GW Data Descriptor are shifted left 623 * so the data starts at the MSB of the descriptor registers as 624 * set by the underlying hardware. Enable byte swapping while 625 * reading data bytes from the 32 * 32-bit HW Data registers 626 * a.k.a Master GW Data Descriptor. 627 */ 628 629 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 630 data32 = ioread32be(priv->smbus->io + addr + offset); 631 *((u32 *)(data + offset)) = data32; 632 } 633 634 if (!(length & mask)) 635 return; 636 637 data32 = ioread32be(priv->smbus->io + addr + offset); 638 639 for (byte = 0; byte < (length & mask); byte++) { 640 data[offset + byte] = data32 & GENMASK(7, 0); 641 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 642 } 643 } 644 645 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 646 u8 len, u8 block_en, u8 pec_en, bool read) 647 { 648 u32 command; 649 650 /* Set Master GW control word. */ 651 if (read) { 652 command = MLXBF_I2C_MASTER_ENABLE_READ; 653 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 654 } else { 655 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 656 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 657 } 658 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 659 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 660 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 661 662 /* Clear status bits. */ 663 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 664 /* Set the cause data. */ 665 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 666 /* Zero PEC byte. */ 667 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC); 668 /* Zero byte count. */ 669 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES); 670 671 /* GW activation. */ 672 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 673 674 /* 675 * Poll master status and check status bits. An ACK is sent when 676 * completing writing data to the bus (Master 'byte_count_done' bit 677 * is set to 1). 678 */ 679 return mlxbf_i2c_smbus_check_status(priv); 680 } 681 682 static int 683 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 684 struct mlxbf_i2c_smbus_request *request) 685 { 686 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 687 u8 op_idx, data_idx, data_len, write_len, read_len; 688 struct mlxbf_i2c_smbus_operation *operation; 689 u8 read_en, write_en, block_en, pec_en; 690 u8 slave, flags, addr; 691 u8 *read_buf; 692 int ret = 0; 693 694 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 695 return -EINVAL; 696 697 read_buf = NULL; 698 data_idx = 0; 699 read_en = 0; 700 write_en = 0; 701 write_len = 0; 702 read_len = 0; 703 block_en = 0; 704 pec_en = 0; 705 slave = request->slave & GENMASK(6, 0); 706 addr = slave << 1; 707 708 /* First of all, check whether the HW is idle. */ 709 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) 710 return -EBUSY; 711 712 /* Set first byte. */ 713 data_desc[data_idx++] = addr; 714 715 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 716 operation = &request->operation[op_idx]; 717 flags = operation->flags; 718 719 /* 720 * Note that read and write operations might be handled by a 721 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 722 * then write command byte and set the optional SMBus specific 723 * bits such as block_en and pec_en. These bits MUST be 724 * submitted by the first operation only. 725 */ 726 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 727 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 728 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 729 } 730 731 if (flags & MLXBF_I2C_F_WRITE) { 732 write_en = 1; 733 write_len += operation->length; 734 if (data_idx + operation->length > 735 MLXBF_I2C_MASTER_DATA_DESC_SIZE) 736 return -ENOBUFS; 737 memcpy(data_desc + data_idx, 738 operation->buffer, operation->length); 739 data_idx += operation->length; 740 } 741 /* 742 * We assume that read operations are performed only once per 743 * SMBus transaction. *TBD* protect this statement so it won't 744 * be executed twice? or return an error if we try to read more 745 * than once? 746 */ 747 if (flags & MLXBF_I2C_F_READ) { 748 read_en = 1; 749 /* Subtract 1 as required by HW. */ 750 read_len = operation->length - 1; 751 read_buf = operation->buffer; 752 } 753 } 754 755 /* Set Master GW data descriptor. */ 756 data_len = write_len + 1; /* Add one byte of the slave address. */ 757 /* 758 * Note that data_len cannot be 0. Indeed, the slave address byte 759 * must be written to the data registers. 760 */ 761 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 762 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 763 764 if (write_en) { 765 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 766 pec_en, 0); 767 if (ret) 768 return ret; 769 } 770 771 if (read_en) { 772 /* Write slave address to Master GW data descriptor. */ 773 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 774 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 775 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 776 pec_en, 1); 777 if (!ret) { 778 /* Get Master GW data descriptor. */ 779 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 780 MLXBF_I2C_MASTER_DATA_DESC_ADDR); 781 782 /* Get data from Master GW data descriptor. */ 783 memcpy(read_buf, data_desc, read_len + 1); 784 } 785 786 /* 787 * After a read operation the SMBus FSM ps (present state) 788 * needs to be 'manually' reset. This should be removed in 789 * next tag integration. 790 */ 791 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 792 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); 793 } 794 795 return ret; 796 } 797 798 /* I2C SMBus protocols. */ 799 800 static void 801 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 802 u8 read) 803 { 804 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 805 806 request->operation[0].length = 0; 807 request->operation[0].flags = MLXBF_I2C_F_WRITE; 808 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 809 } 810 811 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 812 u8 *data, bool read, bool pec_check) 813 { 814 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 815 816 request->operation[0].length = 1; 817 request->operation[0].length += pec_check; 818 819 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 820 request->operation[0].flags |= read ? 821 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 822 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 823 824 request->operation[0].buffer = data; 825 } 826 827 static void 828 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 829 u8 *command, u8 *data, bool read, bool pec_check) 830 { 831 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 832 833 request->operation[0].length = 1; 834 request->operation[0].flags = 835 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 836 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 837 request->operation[0].buffer = command; 838 839 request->operation[1].length = 1; 840 request->operation[1].length += pec_check; 841 request->operation[1].flags = read ? 842 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 843 request->operation[1].buffer = data; 844 } 845 846 static void 847 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 848 u8 *command, u8 *data, bool read, bool pec_check) 849 { 850 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 851 852 request->operation[0].length = 1; 853 request->operation[0].flags = 854 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 855 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 856 request->operation[0].buffer = command; 857 858 request->operation[1].length = 2; 859 request->operation[1].length += pec_check; 860 request->operation[1].flags = read ? 861 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 862 request->operation[1].buffer = data; 863 } 864 865 static void 866 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 867 u8 *command, u8 *data, u8 *data_len, bool read, 868 bool pec_check) 869 { 870 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 871 872 request->operation[0].length = 1; 873 request->operation[0].flags = 874 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 875 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 876 request->operation[0].buffer = command; 877 878 /* 879 * As specified in the standard, the max number of bytes to read/write 880 * per block operation is 32 bytes. In Golan code, the controller can 881 * read up to 128 bytes and write up to 127 bytes. 882 */ 883 request->operation[1].length = 884 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 885 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 886 request->operation[1].flags = read ? 887 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 888 /* 889 * Skip the first data byte, which corresponds to the number of bytes 890 * to read/write. 891 */ 892 request->operation[1].buffer = data + 1; 893 894 *data_len = request->operation[1].length; 895 896 /* Set the number of byte to read. This will be used by userspace. */ 897 if (read) 898 data[0] = *data_len; 899 } 900 901 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 902 u8 *command, u8 *data, u8 *data_len, 903 bool read, bool pec_check) 904 { 905 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 906 907 request->operation[0].length = 1; 908 request->operation[0].flags = 909 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 910 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 911 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 912 request->operation[0].buffer = command; 913 914 request->operation[1].length = 915 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 916 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 917 request->operation[1].flags = read ? 918 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 919 request->operation[1].buffer = data + 1; 920 921 *data_len = request->operation[1].length; 922 923 /* Set the number of bytes to read. This will be used by userspace. */ 924 if (read) 925 data[0] = *data_len; 926 } 927 928 static void 929 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 930 u8 *command, u8 *data, bool pec_check) 931 { 932 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 933 934 request->operation[0].length = 1; 935 request->operation[0].flags = 936 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 937 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 938 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 939 request->operation[0].buffer = command; 940 941 request->operation[1].length = 2; 942 request->operation[1].flags = MLXBF_I2C_F_WRITE; 943 request->operation[1].buffer = data; 944 945 request->operation[2].length = 3; 946 request->operation[2].flags = MLXBF_I2C_F_READ; 947 request->operation[2].buffer = data; 948 } 949 950 static void 951 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 952 u8 *command, u8 *data, u8 *data_len, 953 bool pec_check) 954 { 955 u32 length; 956 957 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 958 959 request->operation[0].length = 1; 960 request->operation[0].flags = 961 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 962 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 963 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 964 request->operation[0].buffer = command; 965 966 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 967 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 968 969 request->operation[1].length = length - pec_check; 970 request->operation[1].flags = MLXBF_I2C_F_WRITE; 971 request->operation[1].buffer = data; 972 973 request->operation[2].length = length; 974 request->operation[2].flags = MLXBF_I2C_F_READ; 975 request->operation[2].buffer = data; 976 977 *data_len = length; /* including PEC byte. */ 978 } 979 980 /* Initialization functions. */ 981 982 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 983 { 984 return priv->chip->type == type; 985 } 986 987 static struct mlxbf_i2c_resource * 988 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 989 { 990 const struct mlxbf_i2c_chip_info *chip = priv->chip; 991 struct mlxbf_i2c_resource *res; 992 u8 res_idx = 0; 993 994 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 995 res = chip->shared_res[res_idx]; 996 if (res && res->type == type) 997 return res; 998 } 999 1000 return NULL; 1001 } 1002 1003 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1004 struct mlxbf_i2c_resource **res, 1005 u8 type) 1006 { 1007 struct mlxbf_i2c_resource *tmp_res; 1008 struct device *dev = &pdev->dev; 1009 1010 if (!res || *res || type >= MLXBF_I2C_END_RES) 1011 return -EINVAL; 1012 1013 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1014 GFP_KERNEL); 1015 if (!tmp_res) 1016 return -ENOMEM; 1017 1018 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type); 1019 if (!tmp_res->params) { 1020 devm_kfree(dev, tmp_res); 1021 return -EIO; 1022 } 1023 1024 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params); 1025 if (IS_ERR(tmp_res->io)) { 1026 devm_kfree(dev, tmp_res); 1027 return PTR_ERR(tmp_res->io); 1028 } 1029 1030 tmp_res->type = type; 1031 1032 *res = tmp_res; 1033 1034 return 0; 1035 } 1036 1037 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1038 bool minimum) 1039 { 1040 u64 frequency; 1041 u32 ticks; 1042 1043 /* 1044 * Compute ticks as follow: 1045 * 1046 * Ticks 1047 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1048 * Frequency 1049 */ 1050 frequency = priv->frequency; 1051 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1052 /* 1053 * The number of ticks is rounded down and if minimum is equal to 1 1054 * then add one tick. 1055 */ 1056 if (minimum) 1057 ticks++; 1058 1059 return ticks; 1060 } 1061 1062 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1063 u32 mask, u8 shift) 1064 { 1065 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1066 1067 return val; 1068 } 1069 1070 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1071 const struct mlxbf_i2c_timings *timings) 1072 { 1073 u32 timer; 1074 1075 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1076 false, MLXBF_I2C_MASK_16, 1077 MLXBF_I2C_SHIFT_0); 1078 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1079 false, MLXBF_I2C_MASK_16, 1080 MLXBF_I2C_SHIFT_16); 1081 writel(timer, priv->smbus->io + 1082 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1083 1084 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1085 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1086 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1087 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1088 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1089 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1090 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1091 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1092 writel(timer, priv->smbus->io + 1093 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1094 1095 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1096 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1097 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1098 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1099 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1100 1101 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1102 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1103 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1104 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1105 writel(timer, priv->smbus->io + 1106 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1107 1108 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1109 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1110 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1111 1112 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1113 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1114 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1115 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1116 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1117 1118 timer = timings->timeout; 1119 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1120 } 1121 1122 enum mlxbf_i2c_timings_config { 1123 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1124 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1125 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1126 }; 1127 1128 /* 1129 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1130 * bus frequency, it is impacted by the time it takes the driver to 1131 * complete data transmission before transaction abort. 1132 */ 1133 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1134 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1135 .scl_high = 4810, 1136 .scl_low = 5000, 1137 .hold_start = 4000, 1138 .setup_start = 4800, 1139 .setup_stop = 4000, 1140 .setup_data = 250, 1141 .sda_rise = 50, 1142 .sda_fall = 50, 1143 .scl_rise = 50, 1144 .scl_fall = 50, 1145 .hold_data = 300, 1146 .buf = 20000, 1147 .thigh_max = 5000, 1148 .timeout = 106500 1149 }, 1150 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1151 .scl_high = 1011, 1152 .scl_low = 1300, 1153 .hold_start = 600, 1154 .setup_start = 700, 1155 .setup_stop = 600, 1156 .setup_data = 100, 1157 .sda_rise = 50, 1158 .sda_fall = 50, 1159 .scl_rise = 50, 1160 .scl_fall = 50, 1161 .hold_data = 300, 1162 .buf = 20000, 1163 .thigh_max = 5000, 1164 .timeout = 106500 1165 }, 1166 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1167 .scl_high = 600, 1168 .scl_low = 1300, 1169 .hold_start = 600, 1170 .setup_start = 600, 1171 .setup_stop = 600, 1172 .setup_data = 100, 1173 .sda_rise = 50, 1174 .sda_fall = 50, 1175 .scl_rise = 50, 1176 .scl_fall = 50, 1177 .hold_data = 300, 1178 .buf = 20000, 1179 .thigh_max = 5000, 1180 .timeout = 106500 1181 } 1182 }; 1183 1184 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1185 struct mlxbf_i2c_priv *priv) 1186 { 1187 enum mlxbf_i2c_timings_config config_idx; 1188 struct device *dev = &pdev->dev; 1189 u32 config_khz; 1190 1191 int ret; 1192 1193 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1194 if (ret < 0) 1195 config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1196 1197 switch (config_khz) { 1198 default: 1199 /* Default settings is 100 KHz. */ 1200 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1201 config_khz); 1202 fallthrough; 1203 case I2C_MAX_STANDARD_MODE_FREQ: 1204 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1205 break; 1206 1207 case I2C_MAX_FAST_MODE_FREQ: 1208 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1209 break; 1210 1211 case I2C_MAX_FAST_MODE_PLUS_FREQ: 1212 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1213 break; 1214 } 1215 1216 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1217 1218 return 0; 1219 } 1220 1221 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1222 struct mlxbf_i2c_priv *priv) 1223 { 1224 struct mlxbf_i2c_resource *gpio_res; 1225 struct device *dev = &pdev->dev; 1226 struct resource *params; 1227 resource_size_t size; 1228 1229 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1230 if (!gpio_res) 1231 return -EPERM; 1232 1233 /* 1234 * The GPIO region in TYU space is shared among I2C busses. 1235 * This function MUST be serialized to avoid racing when 1236 * claiming the memory region and/or setting up the GPIO. 1237 */ 1238 lockdep_assert_held(gpio_res->lock); 1239 1240 /* Check whether the memory map exist. */ 1241 if (gpio_res->io) 1242 return 0; 1243 1244 params = gpio_res->params; 1245 size = resource_size(params); 1246 1247 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1248 return -EFAULT; 1249 1250 gpio_res->io = devm_ioremap(dev, params->start, size); 1251 if (!gpio_res->io) { 1252 devm_release_mem_region(dev, params->start, size); 1253 return -ENOMEM; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1260 struct mlxbf_i2c_priv *priv) 1261 { 1262 struct mlxbf_i2c_resource *gpio_res; 1263 struct device *dev = &pdev->dev; 1264 struct resource *params; 1265 1266 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1267 if (!gpio_res) 1268 return 0; 1269 1270 mutex_lock(gpio_res->lock); 1271 1272 if (gpio_res->io) { 1273 /* Release the GPIO resource. */ 1274 params = gpio_res->params; 1275 devm_iounmap(dev, gpio_res->io); 1276 devm_release_mem_region(dev, params->start, 1277 resource_size(params)); 1278 } 1279 1280 mutex_unlock(gpio_res->lock); 1281 1282 return 0; 1283 } 1284 1285 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1286 struct mlxbf_i2c_priv *priv) 1287 { 1288 struct mlxbf_i2c_resource *corepll_res; 1289 struct device *dev = &pdev->dev; 1290 struct resource *params; 1291 resource_size_t size; 1292 1293 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1294 MLXBF_I2C_COREPLL_RES); 1295 if (!corepll_res) 1296 return -EPERM; 1297 1298 /* 1299 * The COREPLL region in TYU space is shared among I2C busses. 1300 * This function MUST be serialized to avoid racing when 1301 * claiming the memory region. 1302 */ 1303 lockdep_assert_held(corepll_res->lock); 1304 1305 /* Check whether the memory map exist. */ 1306 if (corepll_res->io) 1307 return 0; 1308 1309 params = corepll_res->params; 1310 size = resource_size(params); 1311 1312 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1313 return -EFAULT; 1314 1315 corepll_res->io = devm_ioremap(dev, params->start, size); 1316 if (!corepll_res->io) { 1317 devm_release_mem_region(dev, params->start, size); 1318 return -ENOMEM; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1325 struct mlxbf_i2c_priv *priv) 1326 { 1327 struct mlxbf_i2c_resource *corepll_res; 1328 struct device *dev = &pdev->dev; 1329 struct resource *params; 1330 1331 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1332 MLXBF_I2C_COREPLL_RES); 1333 1334 mutex_lock(corepll_res->lock); 1335 1336 if (corepll_res->io) { 1337 /* Release the CorePLL resource. */ 1338 params = corepll_res->params; 1339 devm_iounmap(dev, corepll_res->io); 1340 devm_release_mem_region(dev, params->start, 1341 resource_size(params)); 1342 } 1343 1344 mutex_unlock(corepll_res->lock); 1345 1346 return 0; 1347 } 1348 1349 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1350 struct mlxbf_i2c_priv *priv) 1351 { 1352 struct mlxbf_i2c_resource *gpio_res; 1353 struct device *dev = &pdev->dev; 1354 u32 config_reg; 1355 int ret; 1356 1357 /* This configuration is only needed for BlueField 1. */ 1358 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1359 return 0; 1360 1361 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1362 if (!gpio_res) 1363 return -EPERM; 1364 1365 /* 1366 * The GPIO region in TYU space is shared among I2C busses. 1367 * This function MUST be serialized to avoid racing when 1368 * claiming the memory region and/or setting up the GPIO. 1369 */ 1370 1371 mutex_lock(gpio_res->lock); 1372 1373 ret = mlxbf_i2c_get_gpio(pdev, priv); 1374 if (ret < 0) { 1375 dev_err(dev, "Failed to get gpio resource"); 1376 mutex_unlock(gpio_res->lock); 1377 return ret; 1378 } 1379 1380 /* 1381 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1382 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1383 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1384 * instead of HW_OE. 1385 * For now, we do not reset the GPIO state when the driver is removed. 1386 * First, it is not necessary to disable the bus since we are using 1387 * the same busses. Then, some busses might be shared among Linux and 1388 * platform firmware; disabling the bus might compromise the system 1389 * functionality. 1390 */ 1391 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1392 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1393 config_reg); 1394 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1395 1396 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1397 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1398 config_reg); 1399 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1400 1401 mutex_unlock(gpio_res->lock); 1402 1403 return 0; 1404 } 1405 1406 static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1407 { 1408 u64 core_frequency; 1409 u8 core_od, core_r; 1410 u32 corepll_val; 1411 u16 core_f; 1412 1413 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1414 1415 /* Get Core PLL configuration bits. */ 1416 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val); 1417 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val); 1418 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val); 1419 1420 /* 1421 * Compute PLL output frequency as follow: 1422 * 1423 * CORE_F + 1 1424 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1425 * (CORE_R + 1) * (CORE_OD + 1) 1426 * 1427 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1428 * and PadFrequency, respectively. 1429 */ 1430 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f); 1431 core_frequency /= (++core_r) * (++core_od); 1432 1433 return core_frequency; 1434 } 1435 1436 static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1437 { 1438 u32 corepll_reg1_val, corepll_reg2_val; 1439 u64 corepll_frequency; 1440 u8 core_od, core_r; 1441 u32 core_f; 1442 1443 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1444 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1445 1446 /* Get Core PLL configuration bits */ 1447 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val); 1448 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val); 1449 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val); 1450 1451 /* 1452 * Compute PLL output frequency as follow: 1453 * 1454 * CORE_F / 16384 1455 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1456 * (CORE_R + 1) * (CORE_OD + 1) 1457 * 1458 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1459 * and PadFrequency, respectively. 1460 */ 1461 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST; 1462 corepll_frequency /= (++core_r) * (++core_od); 1463 1464 return corepll_frequency; 1465 } 1466 1467 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1468 struct mlxbf_i2c_priv *priv) 1469 { 1470 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1471 struct mlxbf_i2c_resource *corepll_res; 1472 struct device *dev = &pdev->dev; 1473 u64 *freq = &priv->frequency; 1474 int ret; 1475 1476 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1477 MLXBF_I2C_COREPLL_RES); 1478 if (!corepll_res) 1479 return -EPERM; 1480 1481 /* 1482 * First, check whether the TYU core Clock frequency is set. 1483 * The TYU core frequency is the same for all I2C busses; when 1484 * the first device gets probed the frequency is determined and 1485 * stored into a globally visible variable. So, first of all, 1486 * check whether the frequency is already set. Here, we assume 1487 * that the frequency is expected to be greater than 0. 1488 */ 1489 mutex_lock(corepll_res->lock); 1490 if (!mlxbf_i2c_corepll_frequency) { 1491 if (!chip->calculate_freq) { 1492 mutex_unlock(corepll_res->lock); 1493 return -EPERM; 1494 } 1495 1496 ret = mlxbf_i2c_get_corepll(pdev, priv); 1497 if (ret < 0) { 1498 dev_err(dev, "Failed to get corePLL resource"); 1499 mutex_unlock(corepll_res->lock); 1500 return ret; 1501 } 1502 1503 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1504 } 1505 mutex_unlock(corepll_res->lock); 1506 1507 *freq = mlxbf_i2c_corepll_frequency; 1508 1509 return 0; 1510 } 1511 1512 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr) 1513 { 1514 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask; 1515 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail; 1516 bool avail, disabled; 1517 1518 disabled = false; 1519 avail = false; 1520 1521 if (!priv) 1522 return -EPERM; 1523 1524 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1525 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1526 1527 /* 1528 * Read the slave registers. There are 4 * 32-bit slave registers. 1529 * Each slave register can hold up to 4 * 8-bit slave configuration 1530 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1531 */ 1532 for (reg = 0; reg < reg_cnt; reg++) { 1533 slave_reg = readl(priv->smbus->io + 1534 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1535 /* 1536 * Each register holds 4 slave addresses. So, we have to keep 1537 * the byte order consistent with the value read in order to 1538 * update the register correctly, if needed. 1539 */ 1540 slave_reg_tmp = slave_reg; 1541 for (byte = 0; byte < 4; byte++) { 1542 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1543 1544 /* 1545 * Mark the first available slave address slot, i.e. its 1546 * enabled bit should be unset. This slot might be used 1547 * later on to register our slave. 1548 */ 1549 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) { 1550 avail = true; 1551 reg_avail = reg; 1552 byte_avail = byte; 1553 slave_reg_avail = slave_reg; 1554 } 1555 1556 /* 1557 * Parse slave address bytes and check whether the 1558 * slave address already exists and it's enabled, 1559 * i.e. most significant bit is set. 1560 */ 1561 if ((addr_tmp & slave_addr_mask) == addr) { 1562 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) 1563 return 0; 1564 disabled = true; 1565 break; 1566 } 1567 1568 /* Parse next byte. */ 1569 slave_reg_tmp >>= 8; 1570 } 1571 1572 /* Exit the loop if the slave address is found. */ 1573 if (disabled) 1574 break; 1575 } 1576 1577 if (!avail && !disabled) 1578 return -EINVAL; /* No room for a new slave address. */ 1579 1580 if (avail && !disabled) { 1581 reg = reg_avail; 1582 byte = byte_avail; 1583 /* Set the slave address. */ 1584 slave_reg_avail &= ~(slave_addr_mask << (byte * 8)); 1585 slave_reg_avail |= addr << (byte * 8); 1586 slave_reg = slave_reg_avail; 1587 } 1588 1589 /* Enable the slave address and update the register. */ 1590 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1591 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1592 reg * 0x4); 1593 1594 return 0; 1595 } 1596 1597 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv) 1598 { 1599 u32 slave_reg, slave_reg_tmp, slave_addr_mask; 1600 u8 addr, addr_tmp, reg, reg_cnt, slave_byte; 1601 struct i2c_client *client = priv->slave; 1602 bool exist; 1603 1604 exist = false; 1605 1606 addr = client->addr; 1607 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1608 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1609 1610 /* 1611 * Read the slave registers. There are 4 * 32-bit slave registers. 1612 * Each slave register can hold up to 4 * 8-bit slave configuration 1613 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1614 */ 1615 for (reg = 0; reg < reg_cnt; reg++) { 1616 slave_reg = readl(priv->smbus->io + 1617 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1618 1619 /* Check whether the address slots are empty. */ 1620 if (slave_reg == 0) 1621 continue; 1622 1623 /* 1624 * Each register holds 4 slave addresses. So, we have to keep 1625 * the byte order consistent with the value read in order to 1626 * update the register correctly, if needed. 1627 */ 1628 slave_reg_tmp = slave_reg; 1629 slave_byte = 0; 1630 while (slave_reg_tmp != 0) { 1631 addr_tmp = slave_reg_tmp & slave_addr_mask; 1632 /* 1633 * Parse slave address bytes and check whether the 1634 * slave address already exists. 1635 */ 1636 if (addr_tmp == addr) { 1637 exist = true; 1638 break; 1639 } 1640 1641 /* Parse next byte. */ 1642 slave_reg_tmp >>= 8; 1643 slave_byte += 1; 1644 } 1645 1646 /* Exit the loop if the slave address is found. */ 1647 if (exist) 1648 break; 1649 } 1650 1651 if (!exist) 1652 return 0; /* Slave is not registered, nothing to do. */ 1653 1654 /* Cleanup the slave address slot. */ 1655 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1656 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1657 reg * 0x4); 1658 1659 return 0; 1660 } 1661 1662 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1663 struct mlxbf_i2c_priv *priv) 1664 { 1665 struct mlxbf_i2c_resource *coalesce_res; 1666 struct resource *params; 1667 resource_size_t size; 1668 int ret = 0; 1669 1670 /* 1671 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1672 * resource in the next generations of BlueField. 1673 */ 1674 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1675 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1676 MLXBF_I2C_COALESCE_RES); 1677 if (!coalesce_res) 1678 return -EPERM; 1679 1680 /* 1681 * The Cause Coalesce group in TYU space is shared among 1682 * I2C busses. This function MUST be serialized to avoid 1683 * racing when claiming the memory region. 1684 */ 1685 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1686 1687 /* Check whether the memory map exist. */ 1688 if (coalesce_res->io) { 1689 priv->coalesce = coalesce_res; 1690 return 0; 1691 } 1692 1693 params = coalesce_res->params; 1694 size = resource_size(params); 1695 1696 if (!request_mem_region(params->start, size, params->name)) 1697 return -EFAULT; 1698 1699 coalesce_res->io = ioremap(params->start, size); 1700 if (!coalesce_res->io) { 1701 release_mem_region(params->start, size); 1702 return -ENOMEM; 1703 } 1704 1705 priv->coalesce = coalesce_res; 1706 1707 } else { 1708 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1709 MLXBF_I2C_COALESCE_RES); 1710 } 1711 1712 return ret; 1713 } 1714 1715 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1716 struct mlxbf_i2c_priv *priv) 1717 { 1718 struct mlxbf_i2c_resource *coalesce_res; 1719 struct device *dev = &pdev->dev; 1720 struct resource *params; 1721 resource_size_t size; 1722 1723 coalesce_res = priv->coalesce; 1724 1725 if (coalesce_res->io) { 1726 params = coalesce_res->params; 1727 size = resource_size(params); 1728 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1729 mutex_lock(coalesce_res->lock); 1730 iounmap(coalesce_res->io); 1731 release_mem_region(params->start, size); 1732 mutex_unlock(coalesce_res->lock); 1733 } else { 1734 devm_release_mem_region(dev, params->start, size); 1735 } 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1742 struct mlxbf_i2c_priv *priv) 1743 { 1744 struct device *dev = &pdev->dev; 1745 u32 int_reg; 1746 int ret; 1747 1748 /* Reset FSM. */ 1749 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1750 1751 /* 1752 * Enable slave cause interrupt bits. Drive 1753 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1754 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1755 * masters issue a Read and Write, respectively. But, clear all 1756 * interrupts first. 1757 */ 1758 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1759 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1760 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1761 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1762 1763 /* Finally, set the 'ready' bit to start handling transactions. */ 1764 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1765 1766 /* Initialize the cause coalesce resource. */ 1767 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1768 if (ret < 0) { 1769 dev_err(dev, "failed to initialize cause coalesce\n"); 1770 return ret; 1771 } 1772 1773 return 0; 1774 } 1775 1776 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1777 bool *write) 1778 { 1779 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1780 u32 coalesce0_reg, cause_reg; 1781 u8 slave_shift, is_set; 1782 1783 *write = false; 1784 *read = false; 1785 1786 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1787 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1788 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1789 1790 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1791 is_set = coalesce0_reg & (1 << slave_shift); 1792 1793 if (!is_set) 1794 return false; 1795 1796 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1797 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1798 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1799 *read = true; 1800 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1801 *write = true; 1802 1803 /* Clear cause bits. */ 1804 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1805 1806 return true; 1807 } 1808 1809 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv, 1810 u32 timeout) 1811 { 1812 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL; 1813 u32 addr = MLXBF_I2C_CAUSE_ARBITER; 1814 1815 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout)) 1816 return true; 1817 1818 return false; 1819 } 1820 1821 /* Send byte to 'external' smbus master. */ 1822 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1823 { 1824 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1825 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size; 1826 struct i2c_client *slave = priv->slave; 1827 u32 control32, data32; 1828 int ret; 1829 1830 if (!slave) 1831 return -EINVAL; 1832 1833 addr = 0; 1834 byte = 0; 1835 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE; 1836 1837 /* 1838 * Read bytes received from the external master. These bytes should 1839 * be located in the first data descriptor register of the slave GW. 1840 * These bytes are the slave address byte and the internal register 1841 * address, if supplied. 1842 */ 1843 if (recv_bytes > 0) { 1844 data32 = ioread32be(priv->smbus->io + 1845 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1846 1847 /* Parse the received bytes. */ 1848 switch (recv_bytes) { 1849 case 2: 1850 byte = (data32 >> 8) & GENMASK(7, 0); 1851 fallthrough; 1852 case 1: 1853 addr = (data32 & GENMASK(7, 0)) >> 1; 1854 } 1855 1856 /* Check whether it's our slave address. */ 1857 if (slave->addr != addr) 1858 return -EINVAL; 1859 } 1860 1861 /* 1862 * I2C read transactions may start by a WRITE followed by a READ. 1863 * Indeed, most slave devices would expect the internal address 1864 * following the slave address byte. So, write that byte first, 1865 * and then, send the requested data bytes to the master. 1866 */ 1867 if (recv_bytes > 1) { 1868 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1869 value = byte; 1870 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1871 &value); 1872 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1873 1874 if (ret < 0) 1875 return ret; 1876 } 1877 1878 /* 1879 * Now, send data to the master; currently, the driver supports 1880 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the 1881 * hardware can send up to 128 bytes per transfer. That is the 1882 * size of its data registers. 1883 */ 1884 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1885 1886 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) { 1887 data_desc[byte_cnt] = value; 1888 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1889 } 1890 1891 /* Send a stop condition to the backend. */ 1892 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1893 1894 /* Handle the actual transfer. */ 1895 1896 /* Set the number of bytes to write to master. */ 1897 write_size = (byte_cnt - 1) & 0x7f; 1898 1899 /* Write data to Slave GW data descriptor. */ 1900 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1901 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1902 1903 pec_en = 0; /* Disable PEC since it is not supported. */ 1904 1905 /* Prepare control word. */ 1906 control32 = MLXBF_I2C_SLAVE_ENABLE; 1907 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1908 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1909 1910 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1911 1912 /* 1913 * Wait until the transfer is completed; the driver will wait 1914 * until the GW is idle, a cause will rise on fall of GW busy. 1915 */ 1916 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1917 1918 /* Release the Slave GW. */ 1919 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1920 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1921 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1922 1923 return 0; 1924 } 1925 1926 /* Receive bytes from 'external' smbus master. */ 1927 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1928 { 1929 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1930 struct i2c_client *slave = priv->slave; 1931 u8 value, byte, addr; 1932 int ret = 0; 1933 1934 if (!slave) 1935 return -EINVAL; 1936 1937 /* Read data from Slave GW data descriptor. */ 1938 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1939 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1940 1941 /* Check whether its our slave address. */ 1942 addr = data_desc[0] >> 1; 1943 if (slave->addr != addr) 1944 return -EINVAL; 1945 1946 /* 1947 * Notify the slave backend; another I2C master wants to write data 1948 * to us. This event is sent once the slave address and the write bit 1949 * is detected. 1950 */ 1951 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1952 1953 /* Send the received data to the slave backend. */ 1954 for (byte = 1; byte < recv_bytes; byte++) { 1955 value = data_desc[byte]; 1956 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1957 &value); 1958 if (ret < 0) 1959 break; 1960 } 1961 1962 /* Send a stop condition to the backend. */ 1963 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1964 1965 /* Release the Slave GW. */ 1966 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1967 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1968 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1969 1970 return ret; 1971 } 1972 1973 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr) 1974 { 1975 struct mlxbf_i2c_priv *priv = ptr; 1976 bool read, write, irq_is_set; 1977 u32 rw_bytes_reg; 1978 u8 recv_bytes; 1979 1980 /* 1981 * Read TYU interrupt register and determine the source of the 1982 * interrupt. Based on the source of the interrupt one of the 1983 * following actions are performed: 1984 * - Receive data and send response to master. 1985 * - Send data and release slave GW. 1986 * 1987 * Handle read/write transaction only. CRmaster and Iarp requests 1988 * are ignored for now. 1989 */ 1990 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 1991 if (!irq_is_set || (!read && !write)) { 1992 /* Nothing to do here, interrupt was not from this device. */ 1993 return IRQ_NONE; 1994 } 1995 1996 /* 1997 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 1998 * bytes from/to master. These are defined by 8-bits each. If the lower 1999 * 8 bits are set, then the master expect to read N bytes from the 2000 * slave, if the higher 8 bits are sent then the slave expect N bytes 2001 * from the master. 2002 */ 2003 rw_bytes_reg = readl(priv->smbus->io + 2004 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2005 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2006 2007 /* 2008 * For now, the slave supports 128 bytes transfer. Discard remaining 2009 * data bytes if the master wrote more than 2010 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2011 * data descriptor. 2012 * 2013 * Note that we will never expect to transfer more than 128 bytes; as 2014 * specified in the SMBus standard, block transactions cannot exceed 2015 * 32 bytes. 2016 */ 2017 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2018 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2019 2020 if (read) 2021 mlxbf_smbus_irq_send(priv, recv_bytes); 2022 else 2023 mlxbf_smbus_irq_recv(priv, recv_bytes); 2024 2025 return IRQ_HANDLED; 2026 } 2027 2028 /* Return negative errno on error. */ 2029 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2030 unsigned short flags, char read_write, 2031 u8 command, int size, 2032 union i2c_smbus_data *data) 2033 { 2034 struct mlxbf_i2c_smbus_request request = { 0 }; 2035 struct mlxbf_i2c_priv *priv; 2036 bool read, pec; 2037 u8 byte_cnt; 2038 2039 request.slave = addr; 2040 2041 read = (read_write == I2C_SMBUS_READ); 2042 pec = flags & I2C_FUNC_SMBUS_PEC; 2043 2044 switch (size) { 2045 case I2C_SMBUS_QUICK: 2046 mlxbf_i2c_smbus_quick_command(&request, read); 2047 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2048 break; 2049 2050 case I2C_SMBUS_BYTE: 2051 mlxbf_i2c_smbus_byte_func(&request, 2052 read ? &data->byte : &command, read, 2053 pec); 2054 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2055 read ? "read" : "write", addr); 2056 break; 2057 2058 case I2C_SMBUS_BYTE_DATA: 2059 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2060 read, pec); 2061 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2062 read ? "read" : "write", command, addr); 2063 break; 2064 2065 case I2C_SMBUS_WORD_DATA: 2066 mlxbf_i2c_smbus_data_word_func(&request, &command, 2067 (u8 *)&data->word, read, pec); 2068 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2069 read ? "read" : "write", command, addr); 2070 break; 2071 2072 case I2C_SMBUS_I2C_BLOCK_DATA: 2073 byte_cnt = data->block[0]; 2074 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2075 &byte_cnt, read, pec); 2076 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2077 read ? "read" : "write", byte_cnt, command, addr); 2078 break; 2079 2080 case I2C_SMBUS_BLOCK_DATA: 2081 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2082 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2083 &byte_cnt, read, pec); 2084 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2085 read ? "read" : "write", byte_cnt, command, addr); 2086 break; 2087 2088 case I2C_FUNC_SMBUS_PROC_CALL: 2089 mlxbf_i2c_smbus_process_call_func(&request, &command, 2090 (u8 *)&data->word, pec); 2091 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2092 command, addr); 2093 break; 2094 2095 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2096 byte_cnt = data->block[0]; 2097 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2098 data->block, &byte_cnt, 2099 pec); 2100 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2101 byte_cnt, addr); 2102 break; 2103 2104 default: 2105 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2106 size); 2107 return -EOPNOTSUPP; 2108 } 2109 2110 priv = i2c_get_adapdata(adap); 2111 2112 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2113 } 2114 2115 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2116 { 2117 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2118 int ret; 2119 2120 if (priv->slave) 2121 return -EBUSY; 2122 2123 /* 2124 * Do not support ten bit chip address and do not use Packet Error 2125 * Checking (PEC). 2126 */ 2127 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) 2128 return -EAFNOSUPPORT; 2129 2130 ret = mlxbf_slave_enable(priv, slave->addr); 2131 if (ret < 0) 2132 return ret; 2133 2134 priv->slave = slave; 2135 2136 return 0; 2137 } 2138 2139 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2140 { 2141 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2142 int ret; 2143 2144 WARN_ON(!priv->slave); 2145 2146 /* Unregister slave, i.e. disable the slave address in hardware. */ 2147 ret = mlxbf_slave_disable(priv); 2148 if (ret < 0) 2149 return ret; 2150 2151 priv->slave = NULL; 2152 2153 return 0; 2154 } 2155 2156 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2157 { 2158 return MLXBF_I2C_FUNC_ALL; 2159 } 2160 2161 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2162 [MLXBF_I2C_CHIP_TYPE_1] = { 2163 .type = MLXBF_I2C_CHIP_TYPE_1, 2164 .shared_res = { 2165 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2166 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2167 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2168 }, 2169 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu 2170 }, 2171 [MLXBF_I2C_CHIP_TYPE_2] = { 2172 .type = MLXBF_I2C_CHIP_TYPE_2, 2173 .shared_res = { 2174 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2175 }, 2176 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu 2177 } 2178 }; 2179 2180 static const struct i2c_algorithm mlxbf_i2c_algo = { 2181 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2182 .functionality = mlxbf_i2c_functionality, 2183 .reg_slave = mlxbf_i2c_reg_slave, 2184 .unreg_slave = mlxbf_i2c_unreg_slave, 2185 }; 2186 2187 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2188 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2189 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2190 }; 2191 2192 static const struct of_device_id mlxbf_i2c_dt_ids[] = { 2193 { 2194 .compatible = "mellanox,i2c-mlxbf1", 2195 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] 2196 }, 2197 { 2198 .compatible = "mellanox,i2c-mlxbf2", 2199 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] 2200 }, 2201 {}, 2202 }; 2203 2204 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2205 2206 #ifdef CONFIG_ACPI 2207 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2208 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2209 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2210 {}, 2211 }; 2212 2213 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2214 2215 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2216 { 2217 const struct acpi_device_id *aid; 2218 u64 bus_id; 2219 int ret; 2220 2221 if (acpi_disabled) 2222 return -ENOENT; 2223 2224 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2225 if (!aid) 2226 return -ENODEV; 2227 2228 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2229 2230 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id); 2231 if (ret) { 2232 dev_err(dev, "Cannot retrieve UID\n"); 2233 return ret; 2234 } 2235 2236 priv->bus = bus_id; 2237 2238 return 0; 2239 } 2240 #else 2241 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2242 { 2243 return -ENOENT; 2244 } 2245 #endif /* CONFIG_ACPI */ 2246 2247 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2248 { 2249 const struct of_device_id *oid; 2250 int bus_id = -1; 2251 2252 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 2253 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node); 2254 if (!oid) 2255 return -ENODEV; 2256 2257 priv->chip = oid->data; 2258 2259 bus_id = of_alias_get_id(dev->of_node, "i2c"); 2260 if (bus_id >= 0) 2261 priv->bus = bus_id; 2262 } 2263 2264 if (bus_id < 0) { 2265 dev_err(dev, "Cannot get bus id"); 2266 return bus_id; 2267 } 2268 2269 return 0; 2270 } 2271 2272 static int mlxbf_i2c_probe(struct platform_device *pdev) 2273 { 2274 struct device *dev = &pdev->dev; 2275 struct mlxbf_i2c_priv *priv; 2276 struct i2c_adapter *adap; 2277 int irq, ret; 2278 2279 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2280 if (!priv) 2281 return -ENOMEM; 2282 2283 ret = mlxbf_i2c_acpi_probe(dev, priv); 2284 if (ret < 0 && ret != -ENOENT && ret != -ENXIO) 2285 ret = mlxbf_i2c_of_probe(dev, priv); 2286 2287 if (ret < 0) 2288 return ret; 2289 2290 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2291 MLXBF_I2C_SMBUS_RES); 2292 if (ret < 0) { 2293 dev_err(dev, "Cannot fetch smbus resource info"); 2294 return ret; 2295 } 2296 2297 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2298 MLXBF_I2C_MST_CAUSE_RES); 2299 if (ret < 0) { 2300 dev_err(dev, "Cannot fetch cause master resource info"); 2301 return ret; 2302 } 2303 2304 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2305 MLXBF_I2C_SLV_CAUSE_RES); 2306 if (ret < 0) { 2307 dev_err(dev, "Cannot fetch cause slave resource info"); 2308 return ret; 2309 } 2310 2311 adap = &priv->adap; 2312 adap->owner = THIS_MODULE; 2313 adap->class = I2C_CLASS_HWMON; 2314 adap->algo = &mlxbf_i2c_algo; 2315 adap->quirks = &mlxbf_i2c_quirks; 2316 adap->dev.parent = dev; 2317 adap->dev.of_node = dev->of_node; 2318 adap->nr = priv->bus; 2319 2320 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2321 i2c_set_adapdata(adap, priv); 2322 2323 /* Read Core PLL frequency. */ 2324 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2325 if (ret < 0) { 2326 dev_err(dev, "cannot get core clock frequency\n"); 2327 /* Set to default value. */ 2328 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2329 } 2330 2331 /* 2332 * Initialize master. 2333 * Note that a physical bus might be shared among Linux and firmware 2334 * (e.g., ATF). Thus, the bus should be initialized and ready and 2335 * bus initialization would be unnecessary. This requires additional 2336 * knowledge about physical busses. But, since an extra initialization 2337 * does not really hurt, then keep the code as is. 2338 */ 2339 ret = mlxbf_i2c_init_master(pdev, priv); 2340 if (ret < 0) { 2341 dev_err(dev, "failed to initialize smbus master %d", 2342 priv->bus); 2343 return ret; 2344 } 2345 2346 mlxbf_i2c_init_timings(pdev, priv); 2347 2348 mlxbf_i2c_init_slave(pdev, priv); 2349 2350 irq = platform_get_irq(pdev, 0); 2351 if (irq < 0) 2352 return irq; 2353 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2354 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2355 dev_name(dev), priv); 2356 if (ret < 0) { 2357 dev_err(dev, "Cannot get irq %d\n", irq); 2358 return ret; 2359 } 2360 2361 priv->irq = irq; 2362 2363 platform_set_drvdata(pdev, priv); 2364 2365 ret = i2c_add_numbered_adapter(adap); 2366 if (ret < 0) 2367 return ret; 2368 2369 mutex_lock(&mlxbf_i2c_bus_lock); 2370 mlxbf_i2c_bus_count++; 2371 mutex_unlock(&mlxbf_i2c_bus_lock); 2372 2373 return 0; 2374 } 2375 2376 static int mlxbf_i2c_remove(struct platform_device *pdev) 2377 { 2378 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2379 struct device *dev = &pdev->dev; 2380 struct resource *params; 2381 2382 params = priv->smbus->params; 2383 devm_release_mem_region(dev, params->start, resource_size(params)); 2384 2385 params = priv->mst_cause->params; 2386 devm_release_mem_region(dev, params->start, resource_size(params)); 2387 2388 params = priv->slv_cause->params; 2389 devm_release_mem_region(dev, params->start, resource_size(params)); 2390 2391 /* 2392 * Release shared resources. This should be done when releasing 2393 * the I2C controller. 2394 */ 2395 mutex_lock(&mlxbf_i2c_bus_lock); 2396 if (--mlxbf_i2c_bus_count == 0) { 2397 mlxbf_i2c_release_coalesce(pdev, priv); 2398 mlxbf_i2c_release_corepll(pdev, priv); 2399 mlxbf_i2c_release_gpio(pdev, priv); 2400 } 2401 mutex_unlock(&mlxbf_i2c_bus_lock); 2402 2403 devm_free_irq(dev, priv->irq, priv); 2404 2405 i2c_del_adapter(&priv->adap); 2406 2407 return 0; 2408 } 2409 2410 static struct platform_driver mlxbf_i2c_driver = { 2411 .probe = mlxbf_i2c_probe, 2412 .remove = mlxbf_i2c_remove, 2413 .driver = { 2414 .name = "i2c-mlxbf", 2415 .of_match_table = mlxbf_i2c_dt_ids, 2416 #ifdef CONFIG_ACPI 2417 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2418 #endif /* CONFIG_ACPI */ 2419 }, 2420 }; 2421 2422 static int __init mlxbf_i2c_init(void) 2423 { 2424 mutex_init(&mlxbf_i2c_coalesce_lock); 2425 mutex_init(&mlxbf_i2c_corepll_lock); 2426 mutex_init(&mlxbf_i2c_gpio_lock); 2427 2428 mutex_init(&mlxbf_i2c_bus_lock); 2429 2430 return platform_driver_register(&mlxbf_i2c_driver); 2431 } 2432 module_init(mlxbf_i2c_init); 2433 2434 static void __exit mlxbf_i2c_exit(void) 2435 { 2436 platform_driver_unregister(&mlxbf_i2c_driver); 2437 2438 mutex_destroy(&mlxbf_i2c_bus_lock); 2439 2440 mutex_destroy(&mlxbf_i2c_gpio_lock); 2441 mutex_destroy(&mlxbf_i2c_corepll_lock); 2442 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2443 } 2444 module_exit(mlxbf_i2c_exit); 2445 2446 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2447 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2448 MODULE_LICENSE("GPL v2"); 2449