1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * I2C bus driver for Amlogic Meson SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/types.h> 21 22 /* Meson I2C register map */ 23 #define REG_CTRL 0x00 24 #define REG_SLAVE_ADDR 0x04 25 #define REG_TOK_LIST0 0x08 26 #define REG_TOK_LIST1 0x0c 27 #define REG_TOK_WDATA0 0x10 28 #define REG_TOK_WDATA1 0x14 29 #define REG_TOK_RDATA0 0x18 30 #define REG_TOK_RDATA1 0x1c 31 32 /* Control register fields */ 33 #define REG_CTRL_START BIT(0) 34 #define REG_CTRL_ACK_IGNORE BIT(1) 35 #define REG_CTRL_STATUS BIT(2) 36 #define REG_CTRL_ERROR BIT(3) 37 #define REG_CTRL_CLKDIV GENMASK(21, 12) 38 #define REG_CTRL_CLKDIVEXT GENMASK(29, 28) 39 40 #define REG_SLV_ADDR GENMASK(7, 0) 41 #define REG_SLV_SDA_FILTER GENMASK(10, 8) 42 #define REG_SLV_SCL_FILTER GENMASK(13, 11) 43 #define REG_SLV_SCL_LOW GENMASK(27, 16) 44 #define REG_SLV_SCL_LOW_EN BIT(28) 45 46 #define I2C_TIMEOUT_MS 500 47 #define FILTER_DELAY 15 48 49 enum { 50 TOKEN_END = 0, 51 TOKEN_START, 52 TOKEN_SLAVE_ADDR_WRITE, 53 TOKEN_SLAVE_ADDR_READ, 54 TOKEN_DATA, 55 TOKEN_DATA_LAST, 56 TOKEN_STOP, 57 }; 58 59 enum { 60 STATE_IDLE, 61 STATE_READ, 62 STATE_WRITE, 63 }; 64 65 struct meson_i2c_data { 66 unsigned char div_factor; 67 }; 68 69 /** 70 * struct meson_i2c - Meson I2C device private data 71 * 72 * @adap: I2C adapter instance 73 * @dev: Pointer to device structure 74 * @regs: Base address of the device memory mapped registers 75 * @clk: Pointer to clock structure 76 * @msg: Pointer to the current I2C message 77 * @state: Current state in the driver state machine 78 * @last: Flag set for the last message in the transfer 79 * @count: Number of bytes to be sent/received in current transfer 80 * @pos: Current position in the send/receive buffer 81 * @error: Flag set when an error is received 82 * @lock: To avoid race conditions between irq handler and xfer code 83 * @done: Completion used to wait for transfer termination 84 * @tokens: Sequence of tokens to be written to the device 85 * @num_tokens: Number of tokens 86 * @data: Pointer to the controlller's platform data 87 */ 88 struct meson_i2c { 89 struct i2c_adapter adap; 90 struct device *dev; 91 void __iomem *regs; 92 struct clk *clk; 93 94 struct i2c_msg *msg; 95 int state; 96 bool last; 97 int count; 98 int pos; 99 int error; 100 101 spinlock_t lock; 102 struct completion done; 103 u32 tokens[2]; 104 int num_tokens; 105 106 const struct meson_i2c_data *data; 107 }; 108 109 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask, 110 u32 val) 111 { 112 u32 data; 113 114 data = readl(i2c->regs + reg); 115 data &= ~mask; 116 data |= val & mask; 117 writel(data, i2c->regs + reg); 118 } 119 120 static void meson_i2c_reset_tokens(struct meson_i2c *i2c) 121 { 122 i2c->tokens[0] = 0; 123 i2c->tokens[1] = 0; 124 i2c->num_tokens = 0; 125 } 126 127 static void meson_i2c_add_token(struct meson_i2c *i2c, int token) 128 { 129 if (i2c->num_tokens < 8) 130 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4); 131 else 132 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4); 133 134 i2c->num_tokens++; 135 } 136 137 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq) 138 { 139 unsigned long clk_rate = clk_get_rate(i2c->clk); 140 unsigned int div; 141 142 div = DIV_ROUND_UP(clk_rate, freq); 143 div -= FILTER_DELAY; 144 div = DIV_ROUND_UP(div, i2c->data->div_factor); 145 146 /* clock divider has 12 bits */ 147 if (div > GENMASK(11, 0)) { 148 dev_err(i2c->dev, "requested bus frequency too low\n"); 149 div = GENMASK(11, 0); 150 } 151 152 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV, 153 FIELD_PREP(REG_CTRL_CLKDIV, div & GENMASK(9, 0))); 154 155 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT, 156 FIELD_PREP(REG_CTRL_CLKDIVEXT, div >> 10)); 157 158 /* Disable HIGH/LOW mode */ 159 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0); 160 161 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__, 162 clk_rate, freq, div); 163 } 164 165 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len) 166 { 167 u32 rdata0, rdata1; 168 int i; 169 170 rdata0 = readl(i2c->regs + REG_TOK_RDATA0); 171 rdata1 = readl(i2c->regs + REG_TOK_RDATA1); 172 173 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__, 174 rdata0, rdata1, len); 175 176 for (i = 0; i < min(4, len); i++) 177 *buf++ = (rdata0 >> i * 8) & 0xff; 178 179 for (i = 4; i < min(8, len); i++) 180 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff; 181 } 182 183 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len) 184 { 185 u32 wdata0 = 0, wdata1 = 0; 186 int i; 187 188 for (i = 0; i < min(4, len); i++) 189 wdata0 |= *buf++ << (i * 8); 190 191 for (i = 4; i < min(8, len); i++) 192 wdata1 |= *buf++ << ((i - 4) * 8); 193 194 writel(wdata0, i2c->regs + REG_TOK_WDATA0); 195 writel(wdata1, i2c->regs + REG_TOK_WDATA1); 196 197 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__, 198 wdata0, wdata1, len); 199 } 200 201 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c) 202 { 203 bool write = !(i2c->msg->flags & I2C_M_RD); 204 int i; 205 206 i2c->count = min(i2c->msg->len - i2c->pos, 8); 207 208 for (i = 0; i < i2c->count - 1; i++) 209 meson_i2c_add_token(i2c, TOKEN_DATA); 210 211 if (i2c->count) { 212 if (write || i2c->pos + i2c->count < i2c->msg->len) 213 meson_i2c_add_token(i2c, TOKEN_DATA); 214 else 215 meson_i2c_add_token(i2c, TOKEN_DATA_LAST); 216 } 217 218 if (write) 219 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count); 220 221 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len) 222 meson_i2c_add_token(i2c, TOKEN_STOP); 223 224 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0); 225 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1); 226 } 227 228 static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl) 229 { 230 if (ctrl & REG_CTRL_ERROR) { 231 /* 232 * The bit is set when the IGNORE_NAK bit is cleared 233 * and the device didn't respond. In this case, the 234 * I2C controller automatically generates a STOP 235 * condition. 236 */ 237 dev_dbg(i2c->dev, "error bit set\n"); 238 i2c->error = -ENXIO; 239 i2c->state = STATE_IDLE; 240 } else { 241 if (i2c->state == STATE_READ && i2c->count) 242 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, 243 i2c->count); 244 245 i2c->pos += i2c->count; 246 247 if (i2c->pos >= i2c->msg->len) 248 i2c->state = STATE_IDLE; 249 } 250 } 251 252 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id) 253 { 254 struct meson_i2c *i2c = dev_id; 255 unsigned int ctrl; 256 257 spin_lock(&i2c->lock); 258 259 meson_i2c_reset_tokens(i2c); 260 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 261 ctrl = readl(i2c->regs + REG_CTRL); 262 263 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n", 264 i2c->state, i2c->pos, i2c->count, ctrl); 265 266 if (i2c->state == STATE_IDLE) { 267 spin_unlock(&i2c->lock); 268 return IRQ_NONE; 269 } 270 271 meson_i2c_transfer_complete(i2c, ctrl); 272 273 if (i2c->state == STATE_IDLE) { 274 complete(&i2c->done); 275 goto out; 276 } 277 278 /* Restart the processing */ 279 meson_i2c_prepare_xfer(i2c); 280 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START); 281 out: 282 spin_unlock(&i2c->lock); 283 284 return IRQ_HANDLED; 285 } 286 287 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg) 288 { 289 int token; 290 291 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ : 292 TOKEN_SLAVE_ADDR_WRITE; 293 294 295 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR, 296 FIELD_PREP(REG_SLV_ADDR, msg->addr << 1)); 297 298 meson_i2c_add_token(i2c, TOKEN_START); 299 meson_i2c_add_token(i2c, token); 300 } 301 302 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, 303 int last, bool atomic) 304 { 305 unsigned long time_left, flags; 306 int ret = 0; 307 u32 ctrl; 308 309 i2c->msg = msg; 310 i2c->last = last; 311 i2c->pos = 0; 312 i2c->count = 0; 313 i2c->error = 0; 314 315 meson_i2c_reset_tokens(i2c); 316 317 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0; 318 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags); 319 320 if (!(msg->flags & I2C_M_NOSTART)) 321 meson_i2c_do_start(i2c, msg); 322 323 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 324 meson_i2c_prepare_xfer(i2c); 325 326 if (!atomic) 327 reinit_completion(&i2c->done); 328 329 /* Start the transfer */ 330 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START); 331 332 if (atomic) { 333 ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl, 334 !(ctrl & REG_CTRL_STATUS), 335 10, I2C_TIMEOUT_MS * 1000); 336 } else { 337 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS); 338 time_left = wait_for_completion_timeout(&i2c->done, time_left); 339 340 if (!time_left) 341 ret = -ETIMEDOUT; 342 } 343 344 /* 345 * Protect access to i2c struct and registers from interrupt 346 * handlers triggered by a transfer terminated after the 347 * timeout period 348 */ 349 spin_lock_irqsave(&i2c->lock, flags); 350 351 if (atomic && !ret) 352 meson_i2c_transfer_complete(i2c, ctrl); 353 354 /* Abort any active operation */ 355 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 356 357 if (ret) 358 i2c->state = STATE_IDLE; 359 360 if (i2c->error) 361 ret = i2c->error; 362 363 spin_unlock_irqrestore(&i2c->lock, flags); 364 365 return ret; 366 } 367 368 static int meson_i2c_xfer_messages(struct i2c_adapter *adap, 369 struct i2c_msg *msgs, int num, bool atomic) 370 { 371 struct meson_i2c *i2c = adap->algo_data; 372 int i, ret = 0; 373 374 for (i = 0; i < num; i++) { 375 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic); 376 if (ret) 377 break; 378 } 379 380 return ret ?: i; 381 } 382 383 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 384 int num) 385 { 386 return meson_i2c_xfer_messages(adap, msgs, num, false); 387 } 388 389 static int meson_i2c_xfer_atomic(struct i2c_adapter *adap, 390 struct i2c_msg *msgs, int num) 391 { 392 return meson_i2c_xfer_messages(adap, msgs, num, true); 393 } 394 395 static u32 meson_i2c_func(struct i2c_adapter *adap) 396 { 397 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 398 } 399 400 static const struct i2c_algorithm meson_i2c_algorithm = { 401 .master_xfer = meson_i2c_xfer, 402 .master_xfer_atomic = meson_i2c_xfer_atomic, 403 .functionality = meson_i2c_func, 404 }; 405 406 static int meson_i2c_probe(struct platform_device *pdev) 407 { 408 struct device_node *np = pdev->dev.of_node; 409 struct meson_i2c *i2c; 410 struct i2c_timings timings; 411 int irq, ret = 0; 412 413 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL); 414 if (!i2c) 415 return -ENOMEM; 416 417 i2c_parse_fw_timings(&pdev->dev, &timings, true); 418 419 i2c->dev = &pdev->dev; 420 platform_set_drvdata(pdev, i2c); 421 422 spin_lock_init(&i2c->lock); 423 init_completion(&i2c->done); 424 425 i2c->data = (const struct meson_i2c_data *) 426 of_device_get_match_data(&pdev->dev); 427 428 i2c->clk = devm_clk_get(&pdev->dev, NULL); 429 if (IS_ERR(i2c->clk)) { 430 dev_err(&pdev->dev, "can't get device clock\n"); 431 return PTR_ERR(i2c->clk); 432 } 433 434 i2c->regs = devm_platform_ioremap_resource(pdev, 0); 435 if (IS_ERR(i2c->regs)) 436 return PTR_ERR(i2c->regs); 437 438 irq = platform_get_irq(pdev, 0); 439 if (irq < 0) 440 return irq; 441 442 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c); 443 if (ret < 0) { 444 dev_err(&pdev->dev, "can't request IRQ\n"); 445 return ret; 446 } 447 448 ret = clk_prepare_enable(i2c->clk); 449 if (ret < 0) { 450 dev_err(&pdev->dev, "can't prepare clock\n"); 451 return ret; 452 } 453 454 strlcpy(i2c->adap.name, "Meson I2C adapter", 455 sizeof(i2c->adap.name)); 456 i2c->adap.owner = THIS_MODULE; 457 i2c->adap.algo = &meson_i2c_algorithm; 458 i2c->adap.dev.parent = &pdev->dev; 459 i2c->adap.dev.of_node = np; 460 i2c->adap.algo_data = i2c; 461 462 /* 463 * A transfer is triggered when START bit changes from 0 to 1. 464 * Ensure that the bit is set to 0 after probe 465 */ 466 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 467 468 /* Disable filtering */ 469 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, 470 REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER, 0); 471 472 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz); 473 474 ret = i2c_add_adapter(&i2c->adap); 475 if (ret < 0) { 476 clk_disable_unprepare(i2c->clk); 477 return ret; 478 } 479 480 return 0; 481 } 482 483 static int meson_i2c_remove(struct platform_device *pdev) 484 { 485 struct meson_i2c *i2c = platform_get_drvdata(pdev); 486 487 i2c_del_adapter(&i2c->adap); 488 clk_disable_unprepare(i2c->clk); 489 490 return 0; 491 } 492 493 static const struct meson_i2c_data i2c_meson6_data = { 494 .div_factor = 4, 495 }; 496 497 static const struct meson_i2c_data i2c_gxbb_data = { 498 .div_factor = 4, 499 }; 500 501 static const struct meson_i2c_data i2c_axg_data = { 502 .div_factor = 3, 503 }; 504 505 static const struct of_device_id meson_i2c_match[] = { 506 { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data }, 507 { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data }, 508 { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data }, 509 {}, 510 }; 511 512 MODULE_DEVICE_TABLE(of, meson_i2c_match); 513 514 static struct platform_driver meson_i2c_driver = { 515 .probe = meson_i2c_probe, 516 .remove = meson_i2c_remove, 517 .driver = { 518 .name = "meson-i2c", 519 .of_match_table = meson_i2c_match, 520 }, 521 }; 522 523 module_platform_driver(meson_i2c_driver); 524 525 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver"); 526 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 527 MODULE_LICENSE("GPL v2"); 528