1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * I2C bus driver for Amlogic Meson SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/types.h> 20 21 /* Meson I2C register map */ 22 #define REG_CTRL 0x00 23 #define REG_SLAVE_ADDR 0x04 24 #define REG_TOK_LIST0 0x08 25 #define REG_TOK_LIST1 0x0c 26 #define REG_TOK_WDATA0 0x10 27 #define REG_TOK_WDATA1 0x14 28 #define REG_TOK_RDATA0 0x18 29 #define REG_TOK_RDATA1 0x1c 30 31 /* Control register fields */ 32 #define REG_CTRL_START BIT(0) 33 #define REG_CTRL_ACK_IGNORE BIT(1) 34 #define REG_CTRL_STATUS BIT(2) 35 #define REG_CTRL_ERROR BIT(3) 36 #define REG_CTRL_CLKDIV_SHIFT 12 37 #define REG_CTRL_CLKDIV_MASK GENMASK(21, 12) 38 #define REG_CTRL_CLKDIVEXT_SHIFT 28 39 #define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28) 40 41 #define I2C_TIMEOUT_MS 500 42 43 enum { 44 TOKEN_END = 0, 45 TOKEN_START, 46 TOKEN_SLAVE_ADDR_WRITE, 47 TOKEN_SLAVE_ADDR_READ, 48 TOKEN_DATA, 49 TOKEN_DATA_LAST, 50 TOKEN_STOP, 51 }; 52 53 enum { 54 STATE_IDLE, 55 STATE_READ, 56 STATE_WRITE, 57 }; 58 59 struct meson_i2c_data { 60 unsigned char div_factor; 61 }; 62 63 /** 64 * struct meson_i2c - Meson I2C device private data 65 * 66 * @adap: I2C adapter instance 67 * @dev: Pointer to device structure 68 * @regs: Base address of the device memory mapped registers 69 * @clk: Pointer to clock structure 70 * @msg: Pointer to the current I2C message 71 * @state: Current state in the driver state machine 72 * @last: Flag set for the last message in the transfer 73 * @count: Number of bytes to be sent/received in current transfer 74 * @pos: Current position in the send/receive buffer 75 * @error: Flag set when an error is received 76 * @lock: To avoid race conditions between irq handler and xfer code 77 * @done: Completion used to wait for transfer termination 78 * @tokens: Sequence of tokens to be written to the device 79 * @num_tokens: Number of tokens 80 * @data: Pointer to the controlller's platform data 81 */ 82 struct meson_i2c { 83 struct i2c_adapter adap; 84 struct device *dev; 85 void __iomem *regs; 86 struct clk *clk; 87 88 struct i2c_msg *msg; 89 int state; 90 bool last; 91 int count; 92 int pos; 93 int error; 94 95 spinlock_t lock; 96 struct completion done; 97 u32 tokens[2]; 98 int num_tokens; 99 100 const struct meson_i2c_data *data; 101 }; 102 103 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask, 104 u32 val) 105 { 106 u32 data; 107 108 data = readl(i2c->regs + reg); 109 data &= ~mask; 110 data |= val & mask; 111 writel(data, i2c->regs + reg); 112 } 113 114 static void meson_i2c_reset_tokens(struct meson_i2c *i2c) 115 { 116 i2c->tokens[0] = 0; 117 i2c->tokens[1] = 0; 118 i2c->num_tokens = 0; 119 } 120 121 static void meson_i2c_add_token(struct meson_i2c *i2c, int token) 122 { 123 if (i2c->num_tokens < 8) 124 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4); 125 else 126 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4); 127 128 i2c->num_tokens++; 129 } 130 131 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq) 132 { 133 unsigned long clk_rate = clk_get_rate(i2c->clk); 134 unsigned int div; 135 136 div = DIV_ROUND_UP(clk_rate, freq * i2c->data->div_factor); 137 138 /* clock divider has 12 bits */ 139 if (div >= (1 << 12)) { 140 dev_err(i2c->dev, "requested bus frequency too low\n"); 141 div = (1 << 12) - 1; 142 } 143 144 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK, 145 (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT); 146 147 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK, 148 (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT); 149 150 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__, 151 clk_rate, freq, div); 152 } 153 154 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len) 155 { 156 u32 rdata0, rdata1; 157 int i; 158 159 rdata0 = readl(i2c->regs + REG_TOK_RDATA0); 160 rdata1 = readl(i2c->regs + REG_TOK_RDATA1); 161 162 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__, 163 rdata0, rdata1, len); 164 165 for (i = 0; i < min(4, len); i++) 166 *buf++ = (rdata0 >> i * 8) & 0xff; 167 168 for (i = 4; i < min(8, len); i++) 169 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff; 170 } 171 172 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len) 173 { 174 u32 wdata0 = 0, wdata1 = 0; 175 int i; 176 177 for (i = 0; i < min(4, len); i++) 178 wdata0 |= *buf++ << (i * 8); 179 180 for (i = 4; i < min(8, len); i++) 181 wdata1 |= *buf++ << ((i - 4) * 8); 182 183 writel(wdata0, i2c->regs + REG_TOK_WDATA0); 184 writel(wdata1, i2c->regs + REG_TOK_WDATA1); 185 186 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__, 187 wdata0, wdata1, len); 188 } 189 190 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c) 191 { 192 bool write = !(i2c->msg->flags & I2C_M_RD); 193 int i; 194 195 i2c->count = min(i2c->msg->len - i2c->pos, 8); 196 197 for (i = 0; i < i2c->count - 1; i++) 198 meson_i2c_add_token(i2c, TOKEN_DATA); 199 200 if (i2c->count) { 201 if (write || i2c->pos + i2c->count < i2c->msg->len) 202 meson_i2c_add_token(i2c, TOKEN_DATA); 203 else 204 meson_i2c_add_token(i2c, TOKEN_DATA_LAST); 205 } 206 207 if (write) 208 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count); 209 210 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len) 211 meson_i2c_add_token(i2c, TOKEN_STOP); 212 213 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0); 214 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1); 215 } 216 217 static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl) 218 { 219 if (ctrl & REG_CTRL_ERROR) { 220 /* 221 * The bit is set when the IGNORE_NAK bit is cleared 222 * and the device didn't respond. In this case, the 223 * I2C controller automatically generates a STOP 224 * condition. 225 */ 226 dev_dbg(i2c->dev, "error bit set\n"); 227 i2c->error = -ENXIO; 228 i2c->state = STATE_IDLE; 229 } else { 230 if (i2c->state == STATE_READ && i2c->count) 231 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, 232 i2c->count); 233 234 i2c->pos += i2c->count; 235 236 if (i2c->pos >= i2c->msg->len) 237 i2c->state = STATE_IDLE; 238 } 239 } 240 241 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id) 242 { 243 struct meson_i2c *i2c = dev_id; 244 unsigned int ctrl; 245 246 spin_lock(&i2c->lock); 247 248 meson_i2c_reset_tokens(i2c); 249 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 250 ctrl = readl(i2c->regs + REG_CTRL); 251 252 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n", 253 i2c->state, i2c->pos, i2c->count, ctrl); 254 255 if (i2c->state == STATE_IDLE) { 256 spin_unlock(&i2c->lock); 257 return IRQ_NONE; 258 } 259 260 meson_i2c_transfer_complete(i2c, ctrl); 261 262 if (i2c->state == STATE_IDLE) { 263 complete(&i2c->done); 264 goto out; 265 } 266 267 /* Restart the processing */ 268 meson_i2c_prepare_xfer(i2c); 269 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START); 270 out: 271 spin_unlock(&i2c->lock); 272 273 return IRQ_HANDLED; 274 } 275 276 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg) 277 { 278 int token; 279 280 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ : 281 TOKEN_SLAVE_ADDR_WRITE; 282 283 writel(msg->addr << 1, i2c->regs + REG_SLAVE_ADDR); 284 meson_i2c_add_token(i2c, TOKEN_START); 285 meson_i2c_add_token(i2c, token); 286 } 287 288 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, 289 int last, bool atomic) 290 { 291 unsigned long time_left, flags; 292 int ret = 0; 293 u32 ctrl; 294 295 i2c->msg = msg; 296 i2c->last = last; 297 i2c->pos = 0; 298 i2c->count = 0; 299 i2c->error = 0; 300 301 meson_i2c_reset_tokens(i2c); 302 303 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0; 304 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags); 305 306 if (!(msg->flags & I2C_M_NOSTART)) 307 meson_i2c_do_start(i2c, msg); 308 309 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 310 meson_i2c_prepare_xfer(i2c); 311 312 if (!atomic) 313 reinit_completion(&i2c->done); 314 315 /* Start the transfer */ 316 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START); 317 318 if (atomic) { 319 ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl, 320 !(ctrl & REG_CTRL_STATUS), 321 10, I2C_TIMEOUT_MS * 1000); 322 } else { 323 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS); 324 time_left = wait_for_completion_timeout(&i2c->done, time_left); 325 326 if (!time_left) 327 ret = -ETIMEDOUT; 328 } 329 330 /* 331 * Protect access to i2c struct and registers from interrupt 332 * handlers triggered by a transfer terminated after the 333 * timeout period 334 */ 335 spin_lock_irqsave(&i2c->lock, flags); 336 337 if (atomic && !ret) 338 meson_i2c_transfer_complete(i2c, ctrl); 339 340 /* Abort any active operation */ 341 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 342 343 if (ret) 344 i2c->state = STATE_IDLE; 345 346 if (i2c->error) 347 ret = i2c->error; 348 349 spin_unlock_irqrestore(&i2c->lock, flags); 350 351 return ret; 352 } 353 354 static int meson_i2c_xfer_messages(struct i2c_adapter *adap, 355 struct i2c_msg *msgs, int num, bool atomic) 356 { 357 struct meson_i2c *i2c = adap->algo_data; 358 int i, ret = 0; 359 360 clk_enable(i2c->clk); 361 362 for (i = 0; i < num; i++) { 363 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic); 364 if (ret) 365 break; 366 } 367 368 clk_disable(i2c->clk); 369 370 return ret ?: i; 371 } 372 373 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 374 int num) 375 { 376 return meson_i2c_xfer_messages(adap, msgs, num, false); 377 } 378 379 static int meson_i2c_xfer_atomic(struct i2c_adapter *adap, 380 struct i2c_msg *msgs, int num) 381 { 382 return meson_i2c_xfer_messages(adap, msgs, num, true); 383 } 384 385 static u32 meson_i2c_func(struct i2c_adapter *adap) 386 { 387 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 388 } 389 390 static const struct i2c_algorithm meson_i2c_algorithm = { 391 .master_xfer = meson_i2c_xfer, 392 .master_xfer_atomic = meson_i2c_xfer_atomic, 393 .functionality = meson_i2c_func, 394 }; 395 396 static int meson_i2c_probe(struct platform_device *pdev) 397 { 398 struct device_node *np = pdev->dev.of_node; 399 struct meson_i2c *i2c; 400 struct resource *mem; 401 struct i2c_timings timings; 402 int irq, ret = 0; 403 404 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL); 405 if (!i2c) 406 return -ENOMEM; 407 408 i2c_parse_fw_timings(&pdev->dev, &timings, true); 409 410 i2c->dev = &pdev->dev; 411 platform_set_drvdata(pdev, i2c); 412 413 spin_lock_init(&i2c->lock); 414 init_completion(&i2c->done); 415 416 i2c->data = (const struct meson_i2c_data *) 417 of_device_get_match_data(&pdev->dev); 418 419 i2c->clk = devm_clk_get(&pdev->dev, NULL); 420 if (IS_ERR(i2c->clk)) { 421 dev_err(&pdev->dev, "can't get device clock\n"); 422 return PTR_ERR(i2c->clk); 423 } 424 425 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 426 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 427 if (IS_ERR(i2c->regs)) 428 return PTR_ERR(i2c->regs); 429 430 irq = platform_get_irq(pdev, 0); 431 if (irq < 0) { 432 dev_err(&pdev->dev, "can't find IRQ\n"); 433 return irq; 434 } 435 436 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c); 437 if (ret < 0) { 438 dev_err(&pdev->dev, "can't request IRQ\n"); 439 return ret; 440 } 441 442 ret = clk_prepare(i2c->clk); 443 if (ret < 0) { 444 dev_err(&pdev->dev, "can't prepare clock\n"); 445 return ret; 446 } 447 448 strlcpy(i2c->adap.name, "Meson I2C adapter", 449 sizeof(i2c->adap.name)); 450 i2c->adap.owner = THIS_MODULE; 451 i2c->adap.algo = &meson_i2c_algorithm; 452 i2c->adap.dev.parent = &pdev->dev; 453 i2c->adap.dev.of_node = np; 454 i2c->adap.algo_data = i2c; 455 456 /* 457 * A transfer is triggered when START bit changes from 0 to 1. 458 * Ensure that the bit is set to 0 after probe 459 */ 460 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0); 461 462 ret = i2c_add_adapter(&i2c->adap); 463 if (ret < 0) { 464 clk_unprepare(i2c->clk); 465 return ret; 466 } 467 468 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz); 469 470 return 0; 471 } 472 473 static int meson_i2c_remove(struct platform_device *pdev) 474 { 475 struct meson_i2c *i2c = platform_get_drvdata(pdev); 476 477 i2c_del_adapter(&i2c->adap); 478 clk_unprepare(i2c->clk); 479 480 return 0; 481 } 482 483 static const struct meson_i2c_data i2c_meson6_data = { 484 .div_factor = 4, 485 }; 486 487 static const struct meson_i2c_data i2c_gxbb_data = { 488 .div_factor = 4, 489 }; 490 491 static const struct meson_i2c_data i2c_axg_data = { 492 .div_factor = 3, 493 }; 494 495 static const struct of_device_id meson_i2c_match[] = { 496 { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data }, 497 { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data }, 498 { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data }, 499 {}, 500 }; 501 502 MODULE_DEVICE_TABLE(of, meson_i2c_match); 503 504 static struct platform_driver meson_i2c_driver = { 505 .probe = meson_i2c_probe, 506 .remove = meson_i2c_remove, 507 .driver = { 508 .name = "meson-i2c", 509 .of_match_table = meson_i2c_match, 510 }, 511 }; 512 513 module_platform_driver(meson_i2c_driver); 514 515 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver"); 516 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 517 MODULE_LICENSE("GPL v2"); 518