1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * Copyright(c) 2012 Intel Corporation. All rights reserved. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name of Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor 55 * S12xx Product Family. 56 * 57 * Features supported by this driver: 58 * Hardware PEC yes 59 * Block buffer yes 60 * Block process call transaction no 61 * Slave mode no 62 */ 63 64 #include <linux/module.h> 65 #include <linux/init.h> 66 #include <linux/pci.h> 67 #include <linux/kernel.h> 68 #include <linux/stddef.h> 69 #include <linux/completion.h> 70 #include <linux/dma-mapping.h> 71 #include <linux/i2c.h> 72 #include <linux/acpi.h> 73 #include <linux/interrupt.h> 74 75 #include <asm-generic/io-64-nonatomic-lo-hi.h> 76 77 /* PCI Address Constants */ 78 #define SMBBAR 0 79 80 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ 81 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 82 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 83 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 84 85 #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */ 86 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 87 88 /* Hardware Descriptor Constants - Control Field */ 89 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 90 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 91 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 92 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 93 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 94 #define ISMT_DESC_INT 0x40 /* Interrupt */ 95 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 96 97 /* Hardware Descriptor Constants - Status Field */ 98 #define ISMT_DESC_SCS 0x01 /* Success */ 99 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 100 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 101 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 102 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 103 #define ISMT_DESC_COL 0x40 /* Collisions */ 104 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 105 106 /* Macros */ 107 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) 108 109 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 110 #define ISMT_GR_GCTRL 0x000 /* General Control */ 111 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 112 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 113 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 114 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 115 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 116 117 /* iSMT Master Registers */ 118 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 119 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 120 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 121 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 122 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 123 124 /* iSMT Miscellaneous Registers */ 125 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 126 127 /* General Control Register (GCTRL) bit definitions */ 128 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 129 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 130 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 131 132 /* Master Control Register (MCTRL) bit definitions */ 133 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 134 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 135 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 136 137 /* Master Status Register (MSTS) bit definitions */ 138 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 139 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 140 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 141 #define ISMT_MSTS_IP 0x01 /* In Progress */ 142 143 /* Master Descriptor Size (MDS) bit definitions */ 144 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 145 146 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 147 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 148 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 149 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 150 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 151 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 152 153 154 /* MSI Control Register (MSICTL) bit definitions */ 155 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 156 157 /* iSMT Hardware Descriptor */ 158 struct ismt_desc { 159 u8 tgtaddr_rw; /* target address & r/w bit */ 160 u8 wr_len_cmd; /* write length in bytes or a command */ 161 u8 rd_len; /* read length */ 162 u8 control; /* control bits */ 163 u8 status; /* status bits */ 164 u8 retry; /* collision retry and retry count */ 165 u8 rxbytes; /* received bytes */ 166 u8 txbytes; /* transmitted bytes */ 167 u32 dptr_low; /* lower 32 bit of the data pointer */ 168 u32 dptr_high; /* upper 32 bit of the data pointer */ 169 } __packed; 170 171 struct ismt_priv { 172 struct i2c_adapter adapter; 173 void *smba; /* PCI BAR */ 174 struct pci_dev *pci_dev; 175 struct ismt_desc *hw; /* descriptor virt base addr */ 176 dma_addr_t io_rng_dma; /* descriptor HW base addr */ 177 u8 head; /* ring buffer head pointer */ 178 struct completion cmp; /* interrupt completion */ 179 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */ 180 bool using_msi; /* type of interrupt flag */ 181 }; 182 183 /** 184 * ismt_ids - PCI device IDs supported by this driver 185 */ 186 static DEFINE_PCI_DEVICE_TABLE(ismt_ids) = { 187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, 188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, 189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, 190 { 0, } 191 }; 192 193 MODULE_DEVICE_TABLE(pci, ismt_ids); 194 195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */ 196 static unsigned int bus_speed; 197 module_param(bus_speed, uint, S_IRUGO); 198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); 199 200 /** 201 * __ismt_desc_dump() - dump the contents of a specific descriptor 202 */ 203 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) 204 { 205 206 dev_dbg(dev, "Descriptor struct: %p\n", desc); 207 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); 208 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); 209 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); 210 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); 211 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); 212 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); 213 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); 214 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); 215 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); 216 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); 217 } 218 /** 219 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes 220 * @priv: iSMT private data 221 */ 222 static void ismt_desc_dump(struct ismt_priv *priv) 223 { 224 struct device *dev = &priv->pci_dev->dev; 225 struct ismt_desc *desc = &priv->hw[priv->head]; 226 227 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); 228 __ismt_desc_dump(dev, desc); 229 } 230 231 /** 232 * ismt_gen_reg_dump() - dump the iSMT General Registers 233 * @priv: iSMT private data 234 */ 235 static void ismt_gen_reg_dump(struct ismt_priv *priv) 236 { 237 struct device *dev = &priv->pci_dev->dev; 238 239 dev_dbg(dev, "Dump of the iSMT General Registers\n"); 240 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", 241 priv->smba + ISMT_GR_GCTRL, 242 readl(priv->smba + ISMT_GR_GCTRL)); 243 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", 244 priv->smba + ISMT_GR_SMTICL, 245 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); 246 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", 247 priv->smba + ISMT_GR_ERRINTMSK, 248 readl(priv->smba + ISMT_GR_ERRINTMSK)); 249 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", 250 priv->smba + ISMT_GR_ERRAERMSK, 251 readl(priv->smba + ISMT_GR_ERRAERMSK)); 252 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", 253 priv->smba + ISMT_GR_ERRSTS, 254 readl(priv->smba + ISMT_GR_ERRSTS)); 255 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", 256 priv->smba + ISMT_GR_ERRINFO, 257 readl(priv->smba + ISMT_GR_ERRINFO)); 258 } 259 260 /** 261 * ismt_mstr_reg_dump() - dump the iSMT Master Registers 262 * @priv: iSMT private data 263 */ 264 static void ismt_mstr_reg_dump(struct ismt_priv *priv) 265 { 266 struct device *dev = &priv->pci_dev->dev; 267 268 dev_dbg(dev, "Dump of the iSMT Master Registers\n"); 269 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", 270 priv->smba + ISMT_MSTR_MDBA, 271 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); 272 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", 273 priv->smba + ISMT_MSTR_MCTRL, 274 readl(priv->smba + ISMT_MSTR_MCTRL)); 275 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", 276 priv->smba + ISMT_MSTR_MSTS, 277 readl(priv->smba + ISMT_MSTR_MSTS)); 278 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", 279 priv->smba + ISMT_MSTR_MDS, 280 readl(priv->smba + ISMT_MSTR_MDS)); 281 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", 282 priv->smba + ISMT_MSTR_RPOLICY, 283 readl(priv->smba + ISMT_MSTR_RPOLICY)); 284 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", 285 priv->smba + ISMT_SPGT, 286 readl(priv->smba + ISMT_SPGT)); 287 } 288 289 /** 290 * ismt_submit_desc() - add a descriptor to the ring 291 * @priv: iSMT private data 292 */ 293 static void ismt_submit_desc(struct ismt_priv *priv) 294 { 295 uint fmhp; 296 uint val; 297 298 ismt_desc_dump(priv); 299 ismt_gen_reg_dump(priv); 300 ismt_mstr_reg_dump(priv); 301 302 /* Set the FMHP (Firmware Master Head Pointer)*/ 303 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; 304 val = readl(priv->smba + ISMT_MSTR_MCTRL); 305 writel((val & ~ISMT_MCTRL_FMHP) | fmhp, 306 priv->smba + ISMT_MSTR_MCTRL); 307 308 /* Set the start bit */ 309 val = readl(priv->smba + ISMT_MSTR_MCTRL); 310 writel(val | ISMT_MCTRL_SS, 311 priv->smba + ISMT_MSTR_MCTRL); 312 } 313 314 /** 315 * ismt_process_desc() - handle the completion of the descriptor 316 * @desc: the iSMT hardware descriptor 317 * @data: data buffer from the upper layer 318 * @priv: ismt_priv struct holding our dma buffer 319 * @size: SMBus transaction type 320 * @read_write: flag to indicate if this is a read or write 321 */ 322 static int ismt_process_desc(const struct ismt_desc *desc, 323 union i2c_smbus_data *data, 324 struct ismt_priv *priv, int size, 325 char read_write) 326 { 327 u8 *dma_buffer = priv->dma_buffer; 328 329 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); 330 __ismt_desc_dump(&priv->pci_dev->dev, desc); 331 332 if (desc->status & ISMT_DESC_SCS) { 333 if (read_write == I2C_SMBUS_WRITE && 334 size != I2C_SMBUS_PROC_CALL) 335 return 0; 336 337 switch (size) { 338 case I2C_SMBUS_BYTE: 339 case I2C_SMBUS_BYTE_DATA: 340 data->byte = dma_buffer[0]; 341 break; 342 case I2C_SMBUS_WORD_DATA: 343 case I2C_SMBUS_PROC_CALL: 344 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 345 break; 346 case I2C_SMBUS_BLOCK_DATA: 347 memcpy(&data->block[1], dma_buffer, desc->rxbytes); 348 data->block[0] = desc->rxbytes; 349 break; 350 } 351 return 0; 352 } 353 354 if (likely(desc->status & ISMT_DESC_NAK)) 355 return -ENXIO; 356 357 if (desc->status & ISMT_DESC_CRC) 358 return -EBADMSG; 359 360 if (desc->status & ISMT_DESC_COL) 361 return -EAGAIN; 362 363 if (desc->status & ISMT_DESC_LPR) 364 return -EPROTO; 365 366 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 367 return -ETIMEDOUT; 368 369 return -EIO; 370 } 371 372 /** 373 * ismt_access() - process an SMBus command 374 * @adap: the i2c host adapter 375 * @addr: address of the i2c/SMBus target 376 * @flags: command options 377 * @read_write: read from or write to device 378 * @command: the i2c/SMBus command to issue 379 * @size: SMBus transaction type 380 * @data: read/write data buffer 381 */ 382 static int ismt_access(struct i2c_adapter *adap, u16 addr, 383 unsigned short flags, char read_write, u8 command, 384 int size, union i2c_smbus_data *data) 385 { 386 int ret; 387 dma_addr_t dma_addr = 0; /* address of the data buffer */ 388 u8 dma_size = 0; 389 enum dma_data_direction dma_direction = 0; 390 struct ismt_desc *desc; 391 struct ismt_priv *priv = i2c_get_adapdata(adap); 392 struct device *dev = &priv->pci_dev->dev; 393 394 desc = &priv->hw[priv->head]; 395 396 /* Initialize the DMA buffer */ 397 memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer)); 398 399 /* Initialize the descriptor */ 400 memset(desc, 0, sizeof(struct ismt_desc)); 401 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); 402 403 /* Initialize common control bits */ 404 if (likely(priv->using_msi)) 405 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; 406 else 407 desc->control = ISMT_DESC_FAIR; 408 409 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) 410 && (size != I2C_SMBUS_I2C_BLOCK_DATA)) 411 desc->control |= ISMT_DESC_PEC; 412 413 switch (size) { 414 case I2C_SMBUS_QUICK: 415 dev_dbg(dev, "I2C_SMBUS_QUICK\n"); 416 break; 417 418 case I2C_SMBUS_BYTE: 419 if (read_write == I2C_SMBUS_WRITE) { 420 /* 421 * Send Byte 422 * The command field contains the write data 423 */ 424 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); 425 desc->control |= ISMT_DESC_CWRL; 426 desc->wr_len_cmd = command; 427 } else { 428 /* Receive Byte */ 429 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); 430 dma_size = 1; 431 dma_direction = DMA_FROM_DEVICE; 432 desc->rd_len = 1; 433 } 434 break; 435 436 case I2C_SMBUS_BYTE_DATA: 437 if (read_write == I2C_SMBUS_WRITE) { 438 /* 439 * Write Byte 440 * Command plus 1 data byte 441 */ 442 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); 443 desc->wr_len_cmd = 2; 444 dma_size = 2; 445 dma_direction = DMA_TO_DEVICE; 446 priv->dma_buffer[0] = command; 447 priv->dma_buffer[1] = data->byte; 448 } else { 449 /* Read Byte */ 450 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); 451 desc->control |= ISMT_DESC_CWRL; 452 desc->wr_len_cmd = command; 453 desc->rd_len = 1; 454 dma_size = 1; 455 dma_direction = DMA_FROM_DEVICE; 456 } 457 break; 458 459 case I2C_SMBUS_WORD_DATA: 460 if (read_write == I2C_SMBUS_WRITE) { 461 /* Write Word */ 462 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); 463 desc->wr_len_cmd = 3; 464 dma_size = 3; 465 dma_direction = DMA_TO_DEVICE; 466 priv->dma_buffer[0] = command; 467 priv->dma_buffer[1] = data->word & 0xff; 468 priv->dma_buffer[2] = data->word >> 8; 469 } else { 470 /* Read Word */ 471 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); 472 desc->wr_len_cmd = command; 473 desc->control |= ISMT_DESC_CWRL; 474 desc->rd_len = 2; 475 dma_size = 2; 476 dma_direction = DMA_FROM_DEVICE; 477 } 478 break; 479 480 case I2C_SMBUS_PROC_CALL: 481 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); 482 desc->wr_len_cmd = 3; 483 desc->rd_len = 2; 484 dma_size = 3; 485 dma_direction = DMA_BIDIRECTIONAL; 486 priv->dma_buffer[0] = command; 487 priv->dma_buffer[1] = data->word & 0xff; 488 priv->dma_buffer[2] = data->word >> 8; 489 break; 490 491 case I2C_SMBUS_BLOCK_DATA: 492 if (read_write == I2C_SMBUS_WRITE) { 493 /* Block Write */ 494 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); 495 dma_size = data->block[0] + 1; 496 dma_direction = DMA_TO_DEVICE; 497 desc->wr_len_cmd = dma_size; 498 desc->control |= ISMT_DESC_BLK; 499 priv->dma_buffer[0] = command; 500 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size); 501 } else { 502 /* Block Read */ 503 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); 504 dma_size = I2C_SMBUS_BLOCK_MAX; 505 dma_direction = DMA_FROM_DEVICE; 506 desc->rd_len = dma_size; 507 desc->wr_len_cmd = command; 508 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); 509 } 510 break; 511 512 default: 513 dev_err(dev, "Unsupported transaction %d\n", 514 size); 515 return -EOPNOTSUPP; 516 } 517 518 /* map the data buffer */ 519 if (dma_size != 0) { 520 dev_dbg(dev, " dev=%p\n", dev); 521 dev_dbg(dev, " data=%p\n", data); 522 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer); 523 dev_dbg(dev, " dma_size=%d\n", dma_size); 524 dev_dbg(dev, " dma_direction=%d\n", dma_direction); 525 526 dma_addr = dma_map_single(dev, 527 priv->dma_buffer, 528 dma_size, 529 dma_direction); 530 531 if (dma_mapping_error(dev, dma_addr)) { 532 dev_err(dev, "Error in mapping dma buffer %p\n", 533 priv->dma_buffer); 534 return -EIO; 535 } 536 537 dev_dbg(dev, " dma_addr = 0x%016llX\n", 538 (unsigned long long)dma_addr); 539 540 desc->dptr_low = lower_32_bits(dma_addr); 541 desc->dptr_high = upper_32_bits(dma_addr); 542 } 543 544 INIT_COMPLETION(priv->cmp); 545 546 /* Add the descriptor */ 547 ismt_submit_desc(priv); 548 549 /* Now we wait for interrupt completion, 1s */ 550 ret = wait_for_completion_timeout(&priv->cmp, HZ*1); 551 552 /* unmap the data buffer */ 553 if (dma_size != 0) 554 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction); 555 556 if (unlikely(!ret)) { 557 dev_err(dev, "completion wait timed out\n"); 558 ret = -ETIMEDOUT; 559 goto out; 560 } 561 562 /* do any post processing of the descriptor here */ 563 ret = ismt_process_desc(desc, data, priv, size, read_write); 564 565 out: 566 /* Update the ring pointer */ 567 priv->head++; 568 priv->head %= ISMT_DESC_ENTRIES; 569 570 return ret; 571 } 572 573 /** 574 * ismt_func() - report which i2c commands are supported by this adapter 575 * @adap: the i2c host adapter 576 */ 577 static u32 ismt_func(struct i2c_adapter *adap) 578 { 579 return I2C_FUNC_SMBUS_QUICK | 580 I2C_FUNC_SMBUS_BYTE | 581 I2C_FUNC_SMBUS_BYTE_DATA | 582 I2C_FUNC_SMBUS_WORD_DATA | 583 I2C_FUNC_SMBUS_PROC_CALL | 584 I2C_FUNC_SMBUS_BLOCK_DATA | 585 I2C_FUNC_SMBUS_PEC; 586 } 587 588 /** 589 * smbus_algorithm - the adapter algorithm and supported functionality 590 * @smbus_xfer: the adapter algorithm 591 * @functionality: functionality supported by the adapter 592 */ 593 static const struct i2c_algorithm smbus_algorithm = { 594 .smbus_xfer = ismt_access, 595 .functionality = ismt_func, 596 }; 597 598 /** 599 * ismt_handle_isr() - interrupt handler bottom half 600 * @priv: iSMT private data 601 */ 602 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) 603 { 604 complete(&priv->cmp); 605 606 return IRQ_HANDLED; 607 } 608 609 610 /** 611 * ismt_do_interrupt() - IRQ interrupt handler 612 * @vec: interrupt vector 613 * @data: iSMT private data 614 */ 615 static irqreturn_t ismt_do_interrupt(int vec, void *data) 616 { 617 u32 val; 618 struct ismt_priv *priv = data; 619 620 /* 621 * check to see it's our interrupt, return IRQ_NONE if not ours 622 * since we are sharing interrupt 623 */ 624 val = readl(priv->smba + ISMT_MSTR_MSTS); 625 626 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) 627 return IRQ_NONE; 628 else 629 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, 630 priv->smba + ISMT_MSTR_MSTS); 631 632 return ismt_handle_isr(priv); 633 } 634 635 /** 636 * ismt_do_msi_interrupt() - MSI interrupt handler 637 * @vec: interrupt vector 638 * @data: iSMT private data 639 */ 640 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) 641 { 642 return ismt_handle_isr(data); 643 } 644 645 /** 646 * ismt_hw_init() - initialize the iSMT hardware 647 * @priv: iSMT private data 648 */ 649 static void ismt_hw_init(struct ismt_priv *priv) 650 { 651 u32 val; 652 struct device *dev = &priv->pci_dev->dev; 653 654 /* initialize the Master Descriptor Base Address (MDBA) */ 655 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); 656 657 /* initialize the Master Control Register (MCTRL) */ 658 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); 659 660 /* initialize the Master Status Register (MSTS) */ 661 writel(0, priv->smba + ISMT_MSTR_MSTS); 662 663 /* initialize the Master Descriptor Size (MDS) */ 664 val = readl(priv->smba + ISMT_MSTR_MDS); 665 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), 666 priv->smba + ISMT_MSTR_MDS); 667 668 /* 669 * Set the SMBus speed (could use this for slow HW debuggers) 670 */ 671 672 val = readl(priv->smba + ISMT_SPGT); 673 674 switch (bus_speed) { 675 case 0: 676 break; 677 678 case 80: 679 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); 680 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), 681 priv->smba + ISMT_SPGT); 682 break; 683 684 case 100: 685 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); 686 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), 687 priv->smba + ISMT_SPGT); 688 break; 689 690 case 400: 691 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); 692 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), 693 priv->smba + ISMT_SPGT); 694 break; 695 696 case 1000: 697 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); 698 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), 699 priv->smba + ISMT_SPGT); 700 break; 701 702 default: 703 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); 704 break; 705 } 706 707 val = readl(priv->smba + ISMT_SPGT); 708 709 switch (val & ISMT_SPGT_SPD_MASK) { 710 case ISMT_SPGT_SPD_80K: 711 bus_speed = 80; 712 break; 713 case ISMT_SPGT_SPD_100K: 714 bus_speed = 100; 715 break; 716 case ISMT_SPGT_SPD_400K: 717 bus_speed = 400; 718 break; 719 case ISMT_SPGT_SPD_1M: 720 bus_speed = 1000; 721 break; 722 } 723 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); 724 } 725 726 /** 727 * ismt_dev_init() - initialize the iSMT data structures 728 * @priv: iSMT private data 729 */ 730 static int ismt_dev_init(struct ismt_priv *priv) 731 { 732 /* allocate memory for the descriptor */ 733 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, 734 (ISMT_DESC_ENTRIES 735 * sizeof(struct ismt_desc)), 736 &priv->io_rng_dma, 737 GFP_KERNEL); 738 if (!priv->hw) 739 return -ENOMEM; 740 741 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))); 742 743 priv->head = 0; 744 init_completion(&priv->cmp); 745 746 return 0; 747 } 748 749 /** 750 * ismt_int_init() - initialize interrupts 751 * @priv: iSMT private data 752 */ 753 static int ismt_int_init(struct ismt_priv *priv) 754 { 755 int err; 756 757 /* Try using MSI interrupts */ 758 err = pci_enable_msi(priv->pci_dev); 759 if (err) { 760 dev_warn(&priv->pci_dev->dev, 761 "Unable to use MSI interrupts, falling back to legacy\n"); 762 goto intx; 763 } 764 765 err = devm_request_irq(&priv->pci_dev->dev, 766 priv->pci_dev->irq, 767 ismt_do_msi_interrupt, 768 0, 769 "ismt-msi", 770 priv); 771 if (err) { 772 pci_disable_msi(priv->pci_dev); 773 goto intx; 774 } 775 776 priv->using_msi = true; 777 goto done; 778 779 /* Try using legacy interrupts */ 780 intx: 781 err = devm_request_irq(&priv->pci_dev->dev, 782 priv->pci_dev->irq, 783 ismt_do_interrupt, 784 IRQF_SHARED, 785 "ismt-intx", 786 priv); 787 if (err) { 788 dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); 789 return -ENODEV; 790 } 791 792 priv->using_msi = false; 793 794 done: 795 return 0; 796 } 797 798 static struct pci_driver ismt_driver; 799 800 /** 801 * ismt_probe() - probe for iSMT devices 802 * @pdev: PCI-Express device 803 * @id: PCI-Express device ID 804 */ 805 static int 806 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) 807 { 808 int err; 809 struct ismt_priv *priv; 810 unsigned long start, len; 811 812 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 813 if (!priv) 814 return -ENOMEM; 815 816 pci_set_drvdata(pdev, priv); 817 i2c_set_adapdata(&priv->adapter, priv); 818 priv->adapter.owner = THIS_MODULE; 819 820 priv->adapter.class = I2C_CLASS_HWMON; 821 822 priv->adapter.algo = &smbus_algorithm; 823 824 /* set up the sysfs linkage to our parent device */ 825 priv->adapter.dev.parent = &pdev->dev; 826 827 /* number of retries on lost arbitration */ 828 priv->adapter.retries = ISMT_MAX_RETRIES; 829 830 priv->pci_dev = pdev; 831 832 err = pcim_enable_device(pdev); 833 if (err) { 834 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", 835 err); 836 return err; 837 } 838 839 /* enable bus mastering */ 840 pci_set_master(pdev); 841 842 /* Determine the address of the SMBus area */ 843 start = pci_resource_start(pdev, SMBBAR); 844 len = pci_resource_len(pdev, SMBBAR); 845 if (!start || !len) { 846 dev_err(&pdev->dev, 847 "SMBus base address uninitialized, upgrade BIOS\n"); 848 return -ENODEV; 849 } 850 851 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 852 "SMBus iSMT adapter at %lx", start); 853 854 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); 855 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); 856 857 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); 858 if (err) { 859 dev_err(&pdev->dev, "ACPI resource conflict!\n"); 860 return err; 861 } 862 863 err = pci_request_region(pdev, SMBBAR, ismt_driver.name); 864 if (err) { 865 dev_err(&pdev->dev, 866 "Failed to request SMBus region 0x%lx-0x%lx\n", 867 start, start + len); 868 return err; 869 } 870 871 priv->smba = pcim_iomap(pdev, SMBBAR, len); 872 if (!priv->smba) { 873 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); 874 err = -ENODEV; 875 goto fail; 876 } 877 878 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 879 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 880 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 881 (pci_set_consistent_dma_mask(pdev, 882 DMA_BIT_MASK(32)) != 0)) { 883 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", 884 pdev); 885 err = -ENODEV; 886 goto fail; 887 } 888 } 889 890 err = ismt_dev_init(priv); 891 if (err) 892 goto fail; 893 894 ismt_hw_init(priv); 895 896 err = ismt_int_init(priv); 897 if (err) 898 goto fail; 899 900 err = i2c_add_adapter(&priv->adapter); 901 if (err) { 902 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n"); 903 err = -ENODEV; 904 goto fail; 905 } 906 return 0; 907 908 fail: 909 pci_release_region(pdev, SMBBAR); 910 return err; 911 } 912 913 /** 914 * ismt_remove() - release driver resources 915 * @pdev: PCI-Express device 916 */ 917 static void ismt_remove(struct pci_dev *pdev) 918 { 919 struct ismt_priv *priv = pci_get_drvdata(pdev); 920 921 i2c_del_adapter(&priv->adapter); 922 pci_release_region(pdev, SMBBAR); 923 } 924 925 /** 926 * ismt_suspend() - place the device in suspend 927 * @pdev: PCI-Express device 928 * @mesg: PM message 929 */ 930 #ifdef CONFIG_PM 931 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg) 932 { 933 pci_save_state(pdev); 934 pci_set_power_state(pdev, pci_choose_state(pdev, mesg)); 935 return 0; 936 } 937 938 /** 939 * ismt_resume() - PCI resume code 940 * @pdev: PCI-Express device 941 */ 942 static int ismt_resume(struct pci_dev *pdev) 943 { 944 pci_set_power_state(pdev, PCI_D0); 945 pci_restore_state(pdev); 946 return pci_enable_device(pdev); 947 } 948 949 #else 950 951 #define ismt_suspend NULL 952 #define ismt_resume NULL 953 954 #endif 955 956 static struct pci_driver ismt_driver = { 957 .name = "ismt_smbus", 958 .id_table = ismt_ids, 959 .probe = ismt_probe, 960 .remove = ismt_remove, 961 .suspend = ismt_suspend, 962 .resume = ismt_resume, 963 }; 964 965 module_pci_driver(ismt_driver); 966 967 MODULE_LICENSE("Dual BSD/GPL"); 968 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); 969 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); 970