1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * Copyright(c) 2012 Intel Corporation. All rights reserved. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * The full GNU General Public License is included in this distribution 18 * in the file called LICENSE.GPL. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * * Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * * Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * * Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor 51 * S12xx Product Family. 52 * 53 * Features supported by this driver: 54 * Hardware PEC yes 55 * Block buffer yes 56 * Block process call transaction no 57 * Slave mode no 58 */ 59 60 #include <linux/module.h> 61 #include <linux/pci.h> 62 #include <linux/kernel.h> 63 #include <linux/stddef.h> 64 #include <linux/completion.h> 65 #include <linux/dma-mapping.h> 66 #include <linux/i2c.h> 67 #include <linux/acpi.h> 68 #include <linux/interrupt.h> 69 70 #include <linux/io-64-nonatomic-lo-hi.h> 71 72 /* PCI Address Constants */ 73 #define SMBBAR 0 74 75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ 76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 78 #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac 79 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac 80 #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff 81 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 82 83 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ 84 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 85 86 /* Hardware Descriptor Constants - Control Field */ 87 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 88 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 89 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 90 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 91 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 92 #define ISMT_DESC_INT 0x40 /* Interrupt */ 93 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 94 95 /* Hardware Descriptor Constants - Status Field */ 96 #define ISMT_DESC_SCS 0x01 /* Success */ 97 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 98 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 99 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 100 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 101 #define ISMT_DESC_COL 0x40 /* Collisions */ 102 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 103 104 /* Macros */ 105 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) 106 107 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 108 #define ISMT_GR_GCTRL 0x000 /* General Control */ 109 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 110 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 111 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 112 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 113 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 114 115 /* iSMT Master Registers */ 116 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 117 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 118 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 119 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 120 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 121 122 /* iSMT Miscellaneous Registers */ 123 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 124 125 /* General Control Register (GCTRL) bit definitions */ 126 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 127 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 128 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 129 130 /* Master Control Register (MCTRL) bit definitions */ 131 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 132 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 133 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 134 135 /* Master Status Register (MSTS) bit definitions */ 136 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 137 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 138 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 139 #define ISMT_MSTS_IP 0x01 /* In Progress */ 140 141 /* Master Descriptor Size (MDS) bit definitions */ 142 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 143 144 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 145 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 146 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 147 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 148 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 149 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 150 151 152 /* MSI Control Register (MSICTL) bit definitions */ 153 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 154 155 /* iSMT Hardware Descriptor */ 156 struct ismt_desc { 157 u8 tgtaddr_rw; /* target address & r/w bit */ 158 u8 wr_len_cmd; /* write length in bytes or a command */ 159 u8 rd_len; /* read length */ 160 u8 control; /* control bits */ 161 u8 status; /* status bits */ 162 u8 retry; /* collision retry and retry count */ 163 u8 rxbytes; /* received bytes */ 164 u8 txbytes; /* transmitted bytes */ 165 u32 dptr_low; /* lower 32 bit of the data pointer */ 166 u32 dptr_high; /* upper 32 bit of the data pointer */ 167 } __packed; 168 169 struct ismt_priv { 170 struct i2c_adapter adapter; 171 void __iomem *smba; /* PCI BAR */ 172 struct pci_dev *pci_dev; 173 struct ismt_desc *hw; /* descriptor virt base addr */ 174 dma_addr_t io_rng_dma; /* descriptor HW base addr */ 175 u8 head; /* ring buffer head pointer */ 176 struct completion cmp; /* interrupt completion */ 177 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */ 178 }; 179 180 static const struct pci_device_id ismt_ids[] = { 181 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, 182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, 183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) }, 184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) }, 185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) }, 186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, 187 { 0, } 188 }; 189 190 MODULE_DEVICE_TABLE(pci, ismt_ids); 191 192 /* Bus speed control bits for slow debuggers - refer to the docs for usage */ 193 static unsigned int bus_speed; 194 module_param(bus_speed, uint, S_IRUGO); 195 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); 196 197 /** 198 * __ismt_desc_dump() - dump the contents of a specific descriptor 199 * @dev: the iSMT device 200 * @desc: the iSMT hardware descriptor 201 */ 202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) 203 { 204 205 dev_dbg(dev, "Descriptor struct: %p\n", desc); 206 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); 207 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); 208 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); 209 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); 210 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); 211 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); 212 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); 213 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); 214 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); 215 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); 216 } 217 /** 218 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes 219 * @priv: iSMT private data 220 */ 221 static void ismt_desc_dump(struct ismt_priv *priv) 222 { 223 struct device *dev = &priv->pci_dev->dev; 224 struct ismt_desc *desc = &priv->hw[priv->head]; 225 226 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); 227 __ismt_desc_dump(dev, desc); 228 } 229 230 /** 231 * ismt_gen_reg_dump() - dump the iSMT General Registers 232 * @priv: iSMT private data 233 */ 234 static void ismt_gen_reg_dump(struct ismt_priv *priv) 235 { 236 struct device *dev = &priv->pci_dev->dev; 237 238 dev_dbg(dev, "Dump of the iSMT General Registers\n"); 239 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", 240 priv->smba + ISMT_GR_GCTRL, 241 readl(priv->smba + ISMT_GR_GCTRL)); 242 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", 243 priv->smba + ISMT_GR_SMTICL, 244 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); 245 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", 246 priv->smba + ISMT_GR_ERRINTMSK, 247 readl(priv->smba + ISMT_GR_ERRINTMSK)); 248 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", 249 priv->smba + ISMT_GR_ERRAERMSK, 250 readl(priv->smba + ISMT_GR_ERRAERMSK)); 251 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", 252 priv->smba + ISMT_GR_ERRSTS, 253 readl(priv->smba + ISMT_GR_ERRSTS)); 254 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", 255 priv->smba + ISMT_GR_ERRINFO, 256 readl(priv->smba + ISMT_GR_ERRINFO)); 257 } 258 259 /** 260 * ismt_mstr_reg_dump() - dump the iSMT Master Registers 261 * @priv: iSMT private data 262 */ 263 static void ismt_mstr_reg_dump(struct ismt_priv *priv) 264 { 265 struct device *dev = &priv->pci_dev->dev; 266 267 dev_dbg(dev, "Dump of the iSMT Master Registers\n"); 268 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", 269 priv->smba + ISMT_MSTR_MDBA, 270 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); 271 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", 272 priv->smba + ISMT_MSTR_MCTRL, 273 readl(priv->smba + ISMT_MSTR_MCTRL)); 274 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", 275 priv->smba + ISMT_MSTR_MSTS, 276 readl(priv->smba + ISMT_MSTR_MSTS)); 277 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", 278 priv->smba + ISMT_MSTR_MDS, 279 readl(priv->smba + ISMT_MSTR_MDS)); 280 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", 281 priv->smba + ISMT_MSTR_RPOLICY, 282 readl(priv->smba + ISMT_MSTR_RPOLICY)); 283 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", 284 priv->smba + ISMT_SPGT, 285 readl(priv->smba + ISMT_SPGT)); 286 } 287 288 /** 289 * ismt_submit_desc() - add a descriptor to the ring 290 * @priv: iSMT private data 291 */ 292 static void ismt_submit_desc(struct ismt_priv *priv) 293 { 294 uint fmhp; 295 uint val; 296 297 ismt_desc_dump(priv); 298 ismt_gen_reg_dump(priv); 299 ismt_mstr_reg_dump(priv); 300 301 /* Set the FMHP (Firmware Master Head Pointer)*/ 302 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; 303 val = readl(priv->smba + ISMT_MSTR_MCTRL); 304 writel((val & ~ISMT_MCTRL_FMHP) | fmhp, 305 priv->smba + ISMT_MSTR_MCTRL); 306 307 /* Set the start bit */ 308 val = readl(priv->smba + ISMT_MSTR_MCTRL); 309 writel(val | ISMT_MCTRL_SS, 310 priv->smba + ISMT_MSTR_MCTRL); 311 } 312 313 /** 314 * ismt_process_desc() - handle the completion of the descriptor 315 * @desc: the iSMT hardware descriptor 316 * @data: data buffer from the upper layer 317 * @priv: ismt_priv struct holding our dma buffer 318 * @size: SMBus transaction type 319 * @read_write: flag to indicate if this is a read or write 320 */ 321 static int ismt_process_desc(const struct ismt_desc *desc, 322 union i2c_smbus_data *data, 323 struct ismt_priv *priv, int size, 324 char read_write) 325 { 326 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 327 328 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); 329 __ismt_desc_dump(&priv->pci_dev->dev, desc); 330 ismt_gen_reg_dump(priv); 331 ismt_mstr_reg_dump(priv); 332 333 if (desc->status & ISMT_DESC_SCS) { 334 if (read_write == I2C_SMBUS_WRITE && 335 size != I2C_SMBUS_PROC_CALL) 336 return 0; 337 338 switch (size) { 339 case I2C_SMBUS_BYTE: 340 case I2C_SMBUS_BYTE_DATA: 341 data->byte = dma_buffer[0]; 342 break; 343 case I2C_SMBUS_WORD_DATA: 344 case I2C_SMBUS_PROC_CALL: 345 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 346 break; 347 case I2C_SMBUS_BLOCK_DATA: 348 if (desc->rxbytes != dma_buffer[0] + 1) 349 return -EMSGSIZE; 350 351 memcpy(data->block, dma_buffer, desc->rxbytes); 352 break; 353 case I2C_SMBUS_I2C_BLOCK_DATA: 354 memcpy(&data->block[1], dma_buffer, desc->rxbytes); 355 data->block[0] = desc->rxbytes; 356 break; 357 } 358 return 0; 359 } 360 361 if (likely(desc->status & ISMT_DESC_NAK)) 362 return -ENXIO; 363 364 if (desc->status & ISMT_DESC_CRC) 365 return -EBADMSG; 366 367 if (desc->status & ISMT_DESC_COL) 368 return -EAGAIN; 369 370 if (desc->status & ISMT_DESC_LPR) 371 return -EPROTO; 372 373 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 374 return -ETIMEDOUT; 375 376 return -EIO; 377 } 378 379 /** 380 * ismt_access() - process an SMBus command 381 * @adap: the i2c host adapter 382 * @addr: address of the i2c/SMBus target 383 * @flags: command options 384 * @read_write: read from or write to device 385 * @command: the i2c/SMBus command to issue 386 * @size: SMBus transaction type 387 * @data: read/write data buffer 388 */ 389 static int ismt_access(struct i2c_adapter *adap, u16 addr, 390 unsigned short flags, char read_write, u8 command, 391 int size, union i2c_smbus_data *data) 392 { 393 int ret; 394 unsigned long time_left; 395 dma_addr_t dma_addr = 0; /* address of the data buffer */ 396 u8 dma_size = 0; 397 enum dma_data_direction dma_direction = 0; 398 struct ismt_desc *desc; 399 struct ismt_priv *priv = i2c_get_adapdata(adap); 400 struct device *dev = &priv->pci_dev->dev; 401 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 402 403 desc = &priv->hw[priv->head]; 404 405 /* Initialize the DMA buffer */ 406 memset(priv->buffer, 0, sizeof(priv->buffer)); 407 408 /* Initialize the descriptor */ 409 memset(desc, 0, sizeof(struct ismt_desc)); 410 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); 411 412 /* Initialize common control bits */ 413 if (likely(pci_dev_msi_enabled(priv->pci_dev))) 414 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; 415 else 416 desc->control = ISMT_DESC_FAIR; 417 418 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) 419 && (size != I2C_SMBUS_I2C_BLOCK_DATA)) 420 desc->control |= ISMT_DESC_PEC; 421 422 switch (size) { 423 case I2C_SMBUS_QUICK: 424 dev_dbg(dev, "I2C_SMBUS_QUICK\n"); 425 break; 426 427 case I2C_SMBUS_BYTE: 428 if (read_write == I2C_SMBUS_WRITE) { 429 /* 430 * Send Byte 431 * The command field contains the write data 432 */ 433 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); 434 desc->control |= ISMT_DESC_CWRL; 435 desc->wr_len_cmd = command; 436 } else { 437 /* Receive Byte */ 438 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); 439 dma_size = 1; 440 dma_direction = DMA_FROM_DEVICE; 441 desc->rd_len = 1; 442 } 443 break; 444 445 case I2C_SMBUS_BYTE_DATA: 446 if (read_write == I2C_SMBUS_WRITE) { 447 /* 448 * Write Byte 449 * Command plus 1 data byte 450 */ 451 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); 452 desc->wr_len_cmd = 2; 453 dma_size = 2; 454 dma_direction = DMA_TO_DEVICE; 455 dma_buffer[0] = command; 456 dma_buffer[1] = data->byte; 457 } else { 458 /* Read Byte */ 459 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); 460 desc->control |= ISMT_DESC_CWRL; 461 desc->wr_len_cmd = command; 462 desc->rd_len = 1; 463 dma_size = 1; 464 dma_direction = DMA_FROM_DEVICE; 465 } 466 break; 467 468 case I2C_SMBUS_WORD_DATA: 469 if (read_write == I2C_SMBUS_WRITE) { 470 /* Write Word */ 471 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); 472 desc->wr_len_cmd = 3; 473 dma_size = 3; 474 dma_direction = DMA_TO_DEVICE; 475 dma_buffer[0] = command; 476 dma_buffer[1] = data->word & 0xff; 477 dma_buffer[2] = data->word >> 8; 478 } else { 479 /* Read Word */ 480 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); 481 desc->wr_len_cmd = command; 482 desc->control |= ISMT_DESC_CWRL; 483 desc->rd_len = 2; 484 dma_size = 2; 485 dma_direction = DMA_FROM_DEVICE; 486 } 487 break; 488 489 case I2C_SMBUS_PROC_CALL: 490 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); 491 desc->wr_len_cmd = 3; 492 desc->rd_len = 2; 493 dma_size = 3; 494 dma_direction = DMA_BIDIRECTIONAL; 495 dma_buffer[0] = command; 496 dma_buffer[1] = data->word & 0xff; 497 dma_buffer[2] = data->word >> 8; 498 break; 499 500 case I2C_SMBUS_BLOCK_DATA: 501 if (read_write == I2C_SMBUS_WRITE) { 502 /* Block Write */ 503 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); 504 dma_size = data->block[0] + 1; 505 dma_direction = DMA_TO_DEVICE; 506 desc->wr_len_cmd = dma_size; 507 desc->control |= ISMT_DESC_BLK; 508 dma_buffer[0] = command; 509 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 510 } else { 511 /* Block Read */ 512 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); 513 dma_size = I2C_SMBUS_BLOCK_MAX; 514 dma_direction = DMA_FROM_DEVICE; 515 desc->rd_len = dma_size; 516 desc->wr_len_cmd = command; 517 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); 518 } 519 break; 520 521 case I2C_SMBUS_I2C_BLOCK_DATA: 522 /* Make sure the length is valid */ 523 if (data->block[0] < 1) 524 data->block[0] = 1; 525 526 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 527 data->block[0] = I2C_SMBUS_BLOCK_MAX; 528 529 if (read_write == I2C_SMBUS_WRITE) { 530 /* i2c Block Write */ 531 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n"); 532 dma_size = data->block[0] + 1; 533 dma_direction = DMA_TO_DEVICE; 534 desc->wr_len_cmd = dma_size; 535 desc->control |= ISMT_DESC_I2C; 536 dma_buffer[0] = command; 537 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 538 } else { 539 /* i2c Block Read */ 540 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n"); 541 dma_size = data->block[0]; 542 dma_direction = DMA_FROM_DEVICE; 543 desc->rd_len = dma_size; 544 desc->wr_len_cmd = command; 545 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); 546 /* 547 * Per the "Table 15-15. I2C Commands", 548 * in the External Design Specification (EDS), 549 * (Document Number: 508084, Revision: 2.0), 550 * the _rw bit must be 0 551 */ 552 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); 553 } 554 break; 555 556 default: 557 dev_err(dev, "Unsupported transaction %d\n", 558 size); 559 return -EOPNOTSUPP; 560 } 561 562 /* map the data buffer */ 563 if (dma_size != 0) { 564 dev_dbg(dev, " dev=%p\n", dev); 565 dev_dbg(dev, " data=%p\n", data); 566 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer); 567 dev_dbg(dev, " dma_size=%d\n", dma_size); 568 dev_dbg(dev, " dma_direction=%d\n", dma_direction); 569 570 dma_addr = dma_map_single(dev, 571 dma_buffer, 572 dma_size, 573 dma_direction); 574 575 if (dma_mapping_error(dev, dma_addr)) { 576 dev_err(dev, "Error in mapping dma buffer %p\n", 577 dma_buffer); 578 return -EIO; 579 } 580 581 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr); 582 583 desc->dptr_low = lower_32_bits(dma_addr); 584 desc->dptr_high = upper_32_bits(dma_addr); 585 } 586 587 reinit_completion(&priv->cmp); 588 589 /* Add the descriptor */ 590 ismt_submit_desc(priv); 591 592 /* Now we wait for interrupt completion, 1s */ 593 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1); 594 595 /* unmap the data buffer */ 596 if (dma_size != 0) 597 dma_unmap_single(dev, dma_addr, dma_size, dma_direction); 598 599 if (unlikely(!time_left)) { 600 dev_err(dev, "completion wait timed out\n"); 601 ret = -ETIMEDOUT; 602 goto out; 603 } 604 605 /* do any post processing of the descriptor here */ 606 ret = ismt_process_desc(desc, data, priv, size, read_write); 607 608 out: 609 /* Update the ring pointer */ 610 priv->head++; 611 priv->head %= ISMT_DESC_ENTRIES; 612 613 return ret; 614 } 615 616 /** 617 * ismt_func() - report which i2c commands are supported by this adapter 618 * @adap: the i2c host adapter 619 */ 620 static u32 ismt_func(struct i2c_adapter *adap) 621 { 622 return I2C_FUNC_SMBUS_QUICK | 623 I2C_FUNC_SMBUS_BYTE | 624 I2C_FUNC_SMBUS_BYTE_DATA | 625 I2C_FUNC_SMBUS_WORD_DATA | 626 I2C_FUNC_SMBUS_PROC_CALL | 627 I2C_FUNC_SMBUS_BLOCK_DATA | 628 I2C_FUNC_SMBUS_I2C_BLOCK | 629 I2C_FUNC_SMBUS_PEC; 630 } 631 632 static const struct i2c_algorithm smbus_algorithm = { 633 .smbus_xfer = ismt_access, 634 .functionality = ismt_func, 635 }; 636 637 /** 638 * ismt_handle_isr() - interrupt handler bottom half 639 * @priv: iSMT private data 640 */ 641 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) 642 { 643 complete(&priv->cmp); 644 645 return IRQ_HANDLED; 646 } 647 648 649 /** 650 * ismt_do_interrupt() - IRQ interrupt handler 651 * @vec: interrupt vector 652 * @data: iSMT private data 653 */ 654 static irqreturn_t ismt_do_interrupt(int vec, void *data) 655 { 656 u32 val; 657 struct ismt_priv *priv = data; 658 659 /* 660 * check to see it's our interrupt, return IRQ_NONE if not ours 661 * since we are sharing interrupt 662 */ 663 val = readl(priv->smba + ISMT_MSTR_MSTS); 664 665 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) 666 return IRQ_NONE; 667 else 668 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, 669 priv->smba + ISMT_MSTR_MSTS); 670 671 return ismt_handle_isr(priv); 672 } 673 674 /** 675 * ismt_do_msi_interrupt() - MSI interrupt handler 676 * @vec: interrupt vector 677 * @data: iSMT private data 678 */ 679 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) 680 { 681 return ismt_handle_isr(data); 682 } 683 684 /** 685 * ismt_hw_init() - initialize the iSMT hardware 686 * @priv: iSMT private data 687 */ 688 static void ismt_hw_init(struct ismt_priv *priv) 689 { 690 u32 val; 691 struct device *dev = &priv->pci_dev->dev; 692 693 /* initialize the Master Descriptor Base Address (MDBA) */ 694 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); 695 696 /* initialize the Master Control Register (MCTRL) */ 697 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); 698 699 /* initialize the Master Status Register (MSTS) */ 700 writel(0, priv->smba + ISMT_MSTR_MSTS); 701 702 /* initialize the Master Descriptor Size (MDS) */ 703 val = readl(priv->smba + ISMT_MSTR_MDS); 704 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), 705 priv->smba + ISMT_MSTR_MDS); 706 707 /* 708 * Set the SMBus speed (could use this for slow HW debuggers) 709 */ 710 711 val = readl(priv->smba + ISMT_SPGT); 712 713 switch (bus_speed) { 714 case 0: 715 break; 716 717 case 80: 718 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); 719 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), 720 priv->smba + ISMT_SPGT); 721 break; 722 723 case 100: 724 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); 725 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), 726 priv->smba + ISMT_SPGT); 727 break; 728 729 case 400: 730 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); 731 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), 732 priv->smba + ISMT_SPGT); 733 break; 734 735 case 1000: 736 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); 737 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), 738 priv->smba + ISMT_SPGT); 739 break; 740 741 default: 742 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); 743 break; 744 } 745 746 val = readl(priv->smba + ISMT_SPGT); 747 748 switch (val & ISMT_SPGT_SPD_MASK) { 749 case ISMT_SPGT_SPD_80K: 750 bus_speed = 80; 751 break; 752 case ISMT_SPGT_SPD_100K: 753 bus_speed = 100; 754 break; 755 case ISMT_SPGT_SPD_400K: 756 bus_speed = 400; 757 break; 758 case ISMT_SPGT_SPD_1M: 759 bus_speed = 1000; 760 break; 761 } 762 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); 763 } 764 765 /** 766 * ismt_dev_init() - initialize the iSMT data structures 767 * @priv: iSMT private data 768 */ 769 static int ismt_dev_init(struct ismt_priv *priv) 770 { 771 /* allocate memory for the descriptor */ 772 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, 773 (ISMT_DESC_ENTRIES 774 * sizeof(struct ismt_desc)), 775 &priv->io_rng_dma, 776 GFP_KERNEL); 777 if (!priv->hw) 778 return -ENOMEM; 779 780 priv->head = 0; 781 init_completion(&priv->cmp); 782 783 return 0; 784 } 785 786 /** 787 * ismt_int_init() - initialize interrupts 788 * @priv: iSMT private data 789 */ 790 static int ismt_int_init(struct ismt_priv *priv) 791 { 792 int err; 793 794 /* Try using MSI interrupts */ 795 err = pci_enable_msi(priv->pci_dev); 796 if (err) 797 goto intx; 798 799 err = devm_request_irq(&priv->pci_dev->dev, 800 priv->pci_dev->irq, 801 ismt_do_msi_interrupt, 802 0, 803 "ismt-msi", 804 priv); 805 if (err) { 806 pci_disable_msi(priv->pci_dev); 807 goto intx; 808 } 809 810 return 0; 811 812 /* Try using legacy interrupts */ 813 intx: 814 dev_warn(&priv->pci_dev->dev, 815 "Unable to use MSI interrupts, falling back to legacy\n"); 816 817 err = devm_request_irq(&priv->pci_dev->dev, 818 priv->pci_dev->irq, 819 ismt_do_interrupt, 820 IRQF_SHARED, 821 "ismt-intx", 822 priv); 823 if (err) { 824 dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); 825 return err; 826 } 827 828 return 0; 829 } 830 831 static struct pci_driver ismt_driver; 832 833 /** 834 * ismt_probe() - probe for iSMT devices 835 * @pdev: PCI-Express device 836 * @id: PCI-Express device ID 837 */ 838 static int 839 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) 840 { 841 int err; 842 struct ismt_priv *priv; 843 unsigned long start, len; 844 845 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 846 if (!priv) 847 return -ENOMEM; 848 849 pci_set_drvdata(pdev, priv); 850 851 i2c_set_adapdata(&priv->adapter, priv); 852 priv->adapter.owner = THIS_MODULE; 853 priv->adapter.class = I2C_CLASS_HWMON; 854 priv->adapter.algo = &smbus_algorithm; 855 priv->adapter.dev.parent = &pdev->dev; 856 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 857 priv->adapter.retries = ISMT_MAX_RETRIES; 858 859 priv->pci_dev = pdev; 860 861 err = pcim_enable_device(pdev); 862 if (err) { 863 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", 864 err); 865 return err; 866 } 867 868 /* enable bus mastering */ 869 pci_set_master(pdev); 870 871 /* Determine the address of the SMBus area */ 872 start = pci_resource_start(pdev, SMBBAR); 873 len = pci_resource_len(pdev, SMBBAR); 874 if (!start || !len) { 875 dev_err(&pdev->dev, 876 "SMBus base address uninitialized, upgrade BIOS\n"); 877 return -ENODEV; 878 } 879 880 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 881 "SMBus iSMT adapter at %lx", start); 882 883 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); 884 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); 885 886 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); 887 if (err) { 888 dev_err(&pdev->dev, "ACPI resource conflict!\n"); 889 return err; 890 } 891 892 err = pci_request_region(pdev, SMBBAR, ismt_driver.name); 893 if (err) { 894 dev_err(&pdev->dev, 895 "Failed to request SMBus region 0x%lx-0x%lx\n", 896 start, start + len); 897 return err; 898 } 899 900 priv->smba = pcim_iomap(pdev, SMBBAR, len); 901 if (!priv->smba) { 902 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); 903 return -ENODEV; 904 } 905 906 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 907 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 908 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 909 (pci_set_consistent_dma_mask(pdev, 910 DMA_BIT_MASK(32)) != 0)) { 911 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", 912 pdev); 913 return -ENODEV; 914 } 915 } 916 917 err = ismt_dev_init(priv); 918 if (err) 919 return err; 920 921 ismt_hw_init(priv); 922 923 err = ismt_int_init(priv); 924 if (err) 925 return err; 926 927 err = i2c_add_adapter(&priv->adapter); 928 if (err) 929 return -ENODEV; 930 return 0; 931 } 932 933 /** 934 * ismt_remove() - release driver resources 935 * @pdev: PCI-Express device 936 */ 937 static void ismt_remove(struct pci_dev *pdev) 938 { 939 struct ismt_priv *priv = pci_get_drvdata(pdev); 940 941 i2c_del_adapter(&priv->adapter); 942 } 943 944 static struct pci_driver ismt_driver = { 945 .name = "ismt_smbus", 946 .id_table = ismt_ids, 947 .probe = ismt_probe, 948 .remove = ismt_remove, 949 }; 950 951 module_pci_driver(ismt_driver); 952 953 MODULE_LICENSE("Dual BSD/GPL"); 954 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); 955 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); 956