1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * Copyright(c) 2012 Intel Corporation. All rights reserved. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name of Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor 55 * S12xx Product Family. 56 * 57 * Features supported by this driver: 58 * Hardware PEC yes 59 * Block buffer yes 60 * Block process call transaction no 61 * Slave mode no 62 */ 63 64 #include <linux/module.h> 65 #include <linux/init.h> 66 #include <linux/pci.h> 67 #include <linux/kernel.h> 68 #include <linux/stddef.h> 69 #include <linux/completion.h> 70 #include <linux/dma-mapping.h> 71 #include <linux/i2c.h> 72 #include <linux/acpi.h> 73 #include <linux/interrupt.h> 74 75 #include <asm-generic/io-64-nonatomic-lo-hi.h> 76 77 /* PCI Address Constants */ 78 #define SMBBAR 0 79 80 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ 81 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 82 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 83 84 #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */ 85 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 86 87 /* Hardware Descriptor Constants - Control Field */ 88 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 89 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 90 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 91 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 92 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 93 #define ISMT_DESC_INT 0x40 /* Interrupt */ 94 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 95 96 /* Hardware Descriptor Constants - Status Field */ 97 #define ISMT_DESC_SCS 0x01 /* Success */ 98 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 99 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 100 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 101 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 102 #define ISMT_DESC_COL 0x40 /* Collisions */ 103 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 104 105 /* Macros */ 106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) 107 108 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 109 #define ISMT_GR_GCTRL 0x000 /* General Control */ 110 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 111 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 112 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 113 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 114 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 115 116 /* iSMT Master Registers */ 117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 118 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 119 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 120 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 121 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 122 123 /* iSMT Miscellaneous Registers */ 124 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 125 126 /* General Control Register (GCTRL) bit definitions */ 127 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 128 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 129 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 130 131 /* Master Control Register (MCTRL) bit definitions */ 132 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 133 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 134 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 135 136 /* Master Status Register (MSTS) bit definitions */ 137 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 138 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 139 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 140 #define ISMT_MSTS_IP 0x01 /* In Progress */ 141 142 /* Master Descriptor Size (MDS) bit definitions */ 143 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 144 145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 146 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 149 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 150 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 151 152 153 /* MSI Control Register (MSICTL) bit definitions */ 154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 155 156 /* iSMT Hardware Descriptor */ 157 struct ismt_desc { 158 u8 tgtaddr_rw; /* target address & r/w bit */ 159 u8 wr_len_cmd; /* write length in bytes or a command */ 160 u8 rd_len; /* read length */ 161 u8 control; /* control bits */ 162 u8 status; /* status bits */ 163 u8 retry; /* collision retry and retry count */ 164 u8 rxbytes; /* received bytes */ 165 u8 txbytes; /* transmitted bytes */ 166 u32 dptr_low; /* lower 32 bit of the data pointer */ 167 u32 dptr_high; /* upper 32 bit of the data pointer */ 168 } __packed; 169 170 struct ismt_priv { 171 struct i2c_adapter adapter; 172 void *smba; /* PCI BAR */ 173 struct pci_dev *pci_dev; 174 struct ismt_desc *hw; /* descriptor virt base addr */ 175 dma_addr_t io_rng_dma; /* descriptor HW base addr */ 176 u8 head; /* ring buffer head pointer */ 177 struct completion cmp; /* interrupt completion */ 178 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */ 179 bool using_msi; /* type of interrupt flag */ 180 }; 181 182 /** 183 * ismt_ids - PCI device IDs supported by this driver 184 */ 185 static const DEFINE_PCI_DEVICE_TABLE(ismt_ids) = { 186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, 187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, 188 { 0, } 189 }; 190 191 MODULE_DEVICE_TABLE(pci, ismt_ids); 192 193 /* Bus speed control bits for slow debuggers - refer to the docs for usage */ 194 static unsigned int bus_speed; 195 module_param(bus_speed, uint, S_IRUGO); 196 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); 197 198 /** 199 * __ismt_desc_dump() - dump the contents of a specific descriptor 200 */ 201 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) 202 { 203 204 dev_dbg(dev, "Descriptor struct: %p\n", desc); 205 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); 206 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); 207 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); 208 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); 209 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); 210 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); 211 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); 212 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); 213 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); 214 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); 215 } 216 /** 217 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes 218 * @priv: iSMT private data 219 */ 220 static void ismt_desc_dump(struct ismt_priv *priv) 221 { 222 struct device *dev = &priv->pci_dev->dev; 223 struct ismt_desc *desc = &priv->hw[priv->head]; 224 225 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); 226 __ismt_desc_dump(dev, desc); 227 } 228 229 /** 230 * ismt_gen_reg_dump() - dump the iSMT General Registers 231 * @priv: iSMT private data 232 */ 233 static void ismt_gen_reg_dump(struct ismt_priv *priv) 234 { 235 struct device *dev = &priv->pci_dev->dev; 236 237 dev_dbg(dev, "Dump of the iSMT General Registers\n"); 238 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", 239 priv->smba + ISMT_GR_GCTRL, 240 readl(priv->smba + ISMT_GR_GCTRL)); 241 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", 242 priv->smba + ISMT_GR_SMTICL, 243 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); 244 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", 245 priv->smba + ISMT_GR_ERRINTMSK, 246 readl(priv->smba + ISMT_GR_ERRINTMSK)); 247 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", 248 priv->smba + ISMT_GR_ERRAERMSK, 249 readl(priv->smba + ISMT_GR_ERRAERMSK)); 250 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", 251 priv->smba + ISMT_GR_ERRSTS, 252 readl(priv->smba + ISMT_GR_ERRSTS)); 253 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", 254 priv->smba + ISMT_GR_ERRINFO, 255 readl(priv->smba + ISMT_GR_ERRINFO)); 256 } 257 258 /** 259 * ismt_mstr_reg_dump() - dump the iSMT Master Registers 260 * @priv: iSMT private data 261 */ 262 static void ismt_mstr_reg_dump(struct ismt_priv *priv) 263 { 264 struct device *dev = &priv->pci_dev->dev; 265 266 dev_dbg(dev, "Dump of the iSMT Master Registers\n"); 267 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", 268 priv->smba + ISMT_MSTR_MDBA, 269 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); 270 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", 271 priv->smba + ISMT_MSTR_MCTRL, 272 readl(priv->smba + ISMT_MSTR_MCTRL)); 273 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", 274 priv->smba + ISMT_MSTR_MSTS, 275 readl(priv->smba + ISMT_MSTR_MSTS)); 276 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", 277 priv->smba + ISMT_MSTR_MDS, 278 readl(priv->smba + ISMT_MSTR_MDS)); 279 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", 280 priv->smba + ISMT_MSTR_RPOLICY, 281 readl(priv->smba + ISMT_MSTR_RPOLICY)); 282 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", 283 priv->smba + ISMT_SPGT, 284 readl(priv->smba + ISMT_SPGT)); 285 } 286 287 /** 288 * ismt_submit_desc() - add a descriptor to the ring 289 * @priv: iSMT private data 290 */ 291 static void ismt_submit_desc(struct ismt_priv *priv) 292 { 293 uint fmhp; 294 uint val; 295 296 ismt_desc_dump(priv); 297 ismt_gen_reg_dump(priv); 298 ismt_mstr_reg_dump(priv); 299 300 /* Set the FMHP (Firmware Master Head Pointer)*/ 301 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; 302 val = readl(priv->smba + ISMT_MSTR_MCTRL); 303 writel((val & ~ISMT_MCTRL_FMHP) | fmhp, 304 priv->smba + ISMT_MSTR_MCTRL); 305 306 /* Set the start bit */ 307 val = readl(priv->smba + ISMT_MSTR_MCTRL); 308 writel(val | ISMT_MCTRL_SS, 309 priv->smba + ISMT_MSTR_MCTRL); 310 } 311 312 /** 313 * ismt_process_desc() - handle the completion of the descriptor 314 * @desc: the iSMT hardware descriptor 315 * @data: data buffer from the upper layer 316 * @priv: ismt_priv struct holding our dma buffer 317 * @size: SMBus transaction type 318 * @read_write: flag to indicate if this is a read or write 319 */ 320 static int ismt_process_desc(const struct ismt_desc *desc, 321 union i2c_smbus_data *data, 322 struct ismt_priv *priv, int size, 323 char read_write) 324 { 325 u8 *dma_buffer = priv->dma_buffer; 326 327 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); 328 __ismt_desc_dump(&priv->pci_dev->dev, desc); 329 330 if (desc->status & ISMT_DESC_SCS) { 331 if (read_write == I2C_SMBUS_WRITE && 332 size != I2C_SMBUS_PROC_CALL) 333 return 0; 334 335 switch (size) { 336 case I2C_SMBUS_BYTE: 337 case I2C_SMBUS_BYTE_DATA: 338 data->byte = dma_buffer[0]; 339 break; 340 case I2C_SMBUS_WORD_DATA: 341 case I2C_SMBUS_PROC_CALL: 342 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 343 break; 344 case I2C_SMBUS_BLOCK_DATA: 345 memcpy(&data->block[1], dma_buffer, desc->rxbytes); 346 data->block[0] = desc->rxbytes; 347 break; 348 } 349 return 0; 350 } 351 352 if (likely(desc->status & ISMT_DESC_NAK)) 353 return -ENXIO; 354 355 if (desc->status & ISMT_DESC_CRC) 356 return -EBADMSG; 357 358 if (desc->status & ISMT_DESC_COL) 359 return -EAGAIN; 360 361 if (desc->status & ISMT_DESC_LPR) 362 return -EPROTO; 363 364 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 365 return -ETIMEDOUT; 366 367 return -EIO; 368 } 369 370 /** 371 * ismt_access() - process an SMBus command 372 * @adap: the i2c host adapter 373 * @addr: address of the i2c/SMBus target 374 * @flags: command options 375 * @read_write: read from or write to device 376 * @command: the i2c/SMBus command to issue 377 * @size: SMBus transaction type 378 * @data: read/write data buffer 379 */ 380 static int ismt_access(struct i2c_adapter *adap, u16 addr, 381 unsigned short flags, char read_write, u8 command, 382 int size, union i2c_smbus_data *data) 383 { 384 int ret; 385 dma_addr_t dma_addr = 0; /* address of the data buffer */ 386 u8 dma_size = 0; 387 enum dma_data_direction dma_direction = 0; 388 struct ismt_desc *desc; 389 struct ismt_priv *priv = i2c_get_adapdata(adap); 390 struct device *dev = &priv->pci_dev->dev; 391 392 desc = &priv->hw[priv->head]; 393 394 /* Initialize the descriptor */ 395 memset(desc, 0, sizeof(struct ismt_desc)); 396 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); 397 398 /* Initialize common control bits */ 399 if (likely(priv->using_msi)) 400 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; 401 else 402 desc->control = ISMT_DESC_FAIR; 403 404 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) 405 && (size != I2C_SMBUS_I2C_BLOCK_DATA)) 406 desc->control |= ISMT_DESC_PEC; 407 408 switch (size) { 409 case I2C_SMBUS_QUICK: 410 dev_dbg(dev, "I2C_SMBUS_QUICK\n"); 411 break; 412 413 case I2C_SMBUS_BYTE: 414 if (read_write == I2C_SMBUS_WRITE) { 415 /* 416 * Send Byte 417 * The command field contains the write data 418 */ 419 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); 420 desc->control |= ISMT_DESC_CWRL; 421 desc->wr_len_cmd = command; 422 } else { 423 /* Receive Byte */ 424 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); 425 dma_size = 1; 426 dma_direction = DMA_FROM_DEVICE; 427 desc->rd_len = 1; 428 } 429 break; 430 431 case I2C_SMBUS_BYTE_DATA: 432 if (read_write == I2C_SMBUS_WRITE) { 433 /* 434 * Write Byte 435 * Command plus 1 data byte 436 */ 437 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); 438 desc->wr_len_cmd = 2; 439 dma_size = 2; 440 dma_direction = DMA_TO_DEVICE; 441 priv->dma_buffer[0] = command; 442 priv->dma_buffer[1] = data->byte; 443 } else { 444 /* Read Byte */ 445 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); 446 desc->control |= ISMT_DESC_CWRL; 447 desc->wr_len_cmd = command; 448 desc->rd_len = 1; 449 dma_size = 1; 450 dma_direction = DMA_FROM_DEVICE; 451 } 452 break; 453 454 case I2C_SMBUS_WORD_DATA: 455 if (read_write == I2C_SMBUS_WRITE) { 456 /* Write Word */ 457 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); 458 desc->wr_len_cmd = 3; 459 dma_size = 3; 460 dma_direction = DMA_TO_DEVICE; 461 priv->dma_buffer[0] = command; 462 priv->dma_buffer[1] = data->word & 0xff; 463 priv->dma_buffer[2] = data->word >> 8; 464 } else { 465 /* Read Word */ 466 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); 467 desc->wr_len_cmd = command; 468 desc->control |= ISMT_DESC_CWRL; 469 desc->rd_len = 2; 470 dma_size = 2; 471 dma_direction = DMA_FROM_DEVICE; 472 } 473 break; 474 475 case I2C_SMBUS_PROC_CALL: 476 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); 477 desc->wr_len_cmd = 3; 478 desc->rd_len = 2; 479 dma_size = 3; 480 dma_direction = DMA_BIDIRECTIONAL; 481 priv->dma_buffer[0] = command; 482 priv->dma_buffer[1] = data->word & 0xff; 483 priv->dma_buffer[2] = data->word >> 8; 484 break; 485 486 case I2C_SMBUS_BLOCK_DATA: 487 if (read_write == I2C_SMBUS_WRITE) { 488 /* Block Write */ 489 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); 490 dma_size = data->block[0] + 1; 491 dma_direction = DMA_TO_DEVICE; 492 desc->wr_len_cmd = dma_size; 493 desc->control |= ISMT_DESC_BLK; 494 priv->dma_buffer[0] = command; 495 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size); 496 } else { 497 /* Block Read */ 498 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); 499 dma_size = I2C_SMBUS_BLOCK_MAX; 500 dma_direction = DMA_FROM_DEVICE; 501 desc->rd_len = dma_size; 502 desc->wr_len_cmd = command; 503 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); 504 } 505 break; 506 507 default: 508 dev_err(dev, "Unsupported transaction %d\n", 509 size); 510 return -EOPNOTSUPP; 511 } 512 513 /* map the data buffer */ 514 if (dma_size != 0) { 515 dev_dbg(dev, " dev=%p\n", dev); 516 dev_dbg(dev, " data=%p\n", data); 517 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer); 518 dev_dbg(dev, " dma_size=%d\n", dma_size); 519 dev_dbg(dev, " dma_direction=%d\n", dma_direction); 520 521 dma_addr = dma_map_single(dev, 522 priv->dma_buffer, 523 dma_size, 524 dma_direction); 525 526 if (dma_mapping_error(dev, dma_addr)) { 527 dev_err(dev, "Error in mapping dma buffer %p\n", 528 priv->dma_buffer); 529 return -EIO; 530 } 531 532 dev_dbg(dev, " dma_addr = 0x%016llX\n", 533 (unsigned long long)dma_addr); 534 535 desc->dptr_low = lower_32_bits(dma_addr); 536 desc->dptr_high = upper_32_bits(dma_addr); 537 } 538 539 INIT_COMPLETION(priv->cmp); 540 541 /* Add the descriptor */ 542 ismt_submit_desc(priv); 543 544 /* Now we wait for interrupt completion, 1s */ 545 ret = wait_for_completion_timeout(&priv->cmp, HZ*1); 546 547 /* unmap the data buffer */ 548 if (dma_size != 0) 549 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction); 550 551 if (unlikely(!ret)) { 552 dev_err(dev, "completion wait timed out\n"); 553 ret = -ETIMEDOUT; 554 goto out; 555 } 556 557 /* do any post processing of the descriptor here */ 558 ret = ismt_process_desc(desc, data, priv, size, read_write); 559 560 out: 561 /* Update the ring pointer */ 562 priv->head++; 563 priv->head %= ISMT_DESC_ENTRIES; 564 565 return ret; 566 } 567 568 /** 569 * ismt_func() - report which i2c commands are supported by this adapter 570 * @adap: the i2c host adapter 571 */ 572 static u32 ismt_func(struct i2c_adapter *adap) 573 { 574 return I2C_FUNC_SMBUS_QUICK | 575 I2C_FUNC_SMBUS_BYTE | 576 I2C_FUNC_SMBUS_BYTE_DATA | 577 I2C_FUNC_SMBUS_WORD_DATA | 578 I2C_FUNC_SMBUS_PROC_CALL | 579 I2C_FUNC_SMBUS_BLOCK_DATA | 580 I2C_FUNC_SMBUS_PEC; 581 } 582 583 /** 584 * smbus_algorithm - the adapter algorithm and supported functionality 585 * @smbus_xfer: the adapter algorithm 586 * @functionality: functionality supported by the adapter 587 */ 588 static const struct i2c_algorithm smbus_algorithm = { 589 .smbus_xfer = ismt_access, 590 .functionality = ismt_func, 591 }; 592 593 /** 594 * ismt_handle_isr() - interrupt handler bottom half 595 * @priv: iSMT private data 596 */ 597 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) 598 { 599 complete(&priv->cmp); 600 601 return IRQ_HANDLED; 602 } 603 604 605 /** 606 * ismt_do_interrupt() - IRQ interrupt handler 607 * @vec: interrupt vector 608 * @data: iSMT private data 609 */ 610 static irqreturn_t ismt_do_interrupt(int vec, void *data) 611 { 612 u32 val; 613 struct ismt_priv *priv = data; 614 615 /* 616 * check to see it's our interrupt, return IRQ_NONE if not ours 617 * since we are sharing interrupt 618 */ 619 val = readl(priv->smba + ISMT_MSTR_MSTS); 620 621 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) 622 return IRQ_NONE; 623 else 624 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, 625 priv->smba + ISMT_MSTR_MSTS); 626 627 return ismt_handle_isr(priv); 628 } 629 630 /** 631 * ismt_do_msi_interrupt() - MSI interrupt handler 632 * @vec: interrupt vector 633 * @data: iSMT private data 634 */ 635 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) 636 { 637 return ismt_handle_isr(data); 638 } 639 640 /** 641 * ismt_hw_init() - initialize the iSMT hardware 642 * @priv: iSMT private data 643 */ 644 static void ismt_hw_init(struct ismt_priv *priv) 645 { 646 u32 val; 647 struct device *dev = &priv->pci_dev->dev; 648 649 /* initialize the Master Descriptor Base Address (MDBA) */ 650 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); 651 652 /* initialize the Master Control Register (MCTRL) */ 653 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); 654 655 /* initialize the Master Status Register (MSTS) */ 656 writel(0, priv->smba + ISMT_MSTR_MSTS); 657 658 /* initialize the Master Descriptor Size (MDS) */ 659 val = readl(priv->smba + ISMT_MSTR_MDS); 660 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), 661 priv->smba + ISMT_MSTR_MDS); 662 663 /* 664 * Set the SMBus speed (could use this for slow HW debuggers) 665 */ 666 667 val = readl(priv->smba + ISMT_SPGT); 668 669 switch (bus_speed) { 670 case 0: 671 break; 672 673 case 80: 674 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); 675 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), 676 priv->smba + ISMT_SPGT); 677 break; 678 679 case 100: 680 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); 681 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), 682 priv->smba + ISMT_SPGT); 683 break; 684 685 case 400: 686 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); 687 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), 688 priv->smba + ISMT_SPGT); 689 break; 690 691 case 1000: 692 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); 693 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), 694 priv->smba + ISMT_SPGT); 695 break; 696 697 default: 698 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); 699 break; 700 } 701 702 val = readl(priv->smba + ISMT_SPGT); 703 704 switch (val & ISMT_SPGT_SPD_MASK) { 705 case ISMT_SPGT_SPD_80K: 706 bus_speed = 80; 707 break; 708 case ISMT_SPGT_SPD_100K: 709 bus_speed = 100; 710 break; 711 case ISMT_SPGT_SPD_400K: 712 bus_speed = 400; 713 break; 714 case ISMT_SPGT_SPD_1M: 715 bus_speed = 1000; 716 break; 717 } 718 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); 719 } 720 721 /** 722 * ismt_dev_init() - initialize the iSMT data structures 723 * @priv: iSMT private data 724 */ 725 static int ismt_dev_init(struct ismt_priv *priv) 726 { 727 /* allocate memory for the descriptor */ 728 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, 729 (ISMT_DESC_ENTRIES 730 * sizeof(struct ismt_desc)), 731 &priv->io_rng_dma, 732 GFP_KERNEL); 733 if (!priv->hw) 734 return -ENOMEM; 735 736 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))); 737 738 priv->head = 0; 739 init_completion(&priv->cmp); 740 741 return 0; 742 } 743 744 /** 745 * ismt_int_init() - initialize interrupts 746 * @priv: iSMT private data 747 */ 748 static int ismt_int_init(struct ismt_priv *priv) 749 { 750 int err; 751 752 /* Try using MSI interrupts */ 753 err = pci_enable_msi(priv->pci_dev); 754 if (err) { 755 dev_warn(&priv->pci_dev->dev, 756 "Unable to use MSI interrupts, falling back to legacy\n"); 757 goto intx; 758 } 759 760 err = devm_request_irq(&priv->pci_dev->dev, 761 priv->pci_dev->irq, 762 ismt_do_msi_interrupt, 763 0, 764 "ismt-msi", 765 priv); 766 if (err) { 767 pci_disable_msi(priv->pci_dev); 768 goto intx; 769 } 770 771 priv->using_msi = true; 772 goto done; 773 774 /* Try using legacy interrupts */ 775 intx: 776 err = devm_request_irq(&priv->pci_dev->dev, 777 priv->pci_dev->irq, 778 ismt_do_interrupt, 779 IRQF_SHARED, 780 "ismt-intx", 781 priv); 782 if (err) { 783 dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); 784 return -ENODEV; 785 } 786 787 priv->using_msi = false; 788 789 done: 790 return 0; 791 } 792 793 static struct pci_driver ismt_driver; 794 795 /** 796 * ismt_probe() - probe for iSMT devices 797 * @pdev: PCI-Express device 798 * @id: PCI-Express device ID 799 */ 800 static int 801 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) 802 { 803 int err; 804 struct ismt_priv *priv; 805 unsigned long start, len; 806 807 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 808 if (!priv) 809 return -ENOMEM; 810 811 pci_set_drvdata(pdev, priv); 812 i2c_set_adapdata(&priv->adapter, priv); 813 priv->adapter.owner = THIS_MODULE; 814 815 priv->adapter.class = I2C_CLASS_HWMON; 816 817 priv->adapter.algo = &smbus_algorithm; 818 819 /* set up the sysfs linkage to our parent device */ 820 priv->adapter.dev.parent = &pdev->dev; 821 822 /* number of retries on lost arbitration */ 823 priv->adapter.retries = ISMT_MAX_RETRIES; 824 825 priv->pci_dev = pdev; 826 827 err = pcim_enable_device(pdev); 828 if (err) { 829 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", 830 err); 831 return err; 832 } 833 834 /* enable bus mastering */ 835 pci_set_master(pdev); 836 837 /* Determine the address of the SMBus area */ 838 start = pci_resource_start(pdev, SMBBAR); 839 len = pci_resource_len(pdev, SMBBAR); 840 if (!start || !len) { 841 dev_err(&pdev->dev, 842 "SMBus base address uninitialized, upgrade BIOS\n"); 843 return -ENODEV; 844 } 845 846 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 847 "SMBus iSMT adapter at %lx", start); 848 849 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); 850 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); 851 852 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); 853 if (err) { 854 dev_err(&pdev->dev, "ACPI resource conflict!\n"); 855 return err; 856 } 857 858 err = pci_request_region(pdev, SMBBAR, ismt_driver.name); 859 if (err) { 860 dev_err(&pdev->dev, 861 "Failed to request SMBus region 0x%lx-0x%lx\n", 862 start, start + len); 863 return err; 864 } 865 866 priv->smba = pcim_iomap(pdev, SMBBAR, len); 867 if (!priv->smba) { 868 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); 869 err = -ENODEV; 870 goto fail; 871 } 872 873 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 874 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 875 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 876 (pci_set_consistent_dma_mask(pdev, 877 DMA_BIT_MASK(32)) != 0)) { 878 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", 879 pdev); 880 goto fail; 881 } 882 } 883 884 err = ismt_dev_init(priv); 885 if (err) 886 goto fail; 887 888 ismt_hw_init(priv); 889 890 err = ismt_int_init(priv); 891 if (err) 892 goto fail; 893 894 err = i2c_add_adapter(&priv->adapter); 895 if (err) { 896 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n"); 897 err = -ENODEV; 898 goto fail; 899 } 900 return 0; 901 902 fail: 903 pci_release_region(pdev, SMBBAR); 904 return err; 905 } 906 907 /** 908 * ismt_remove() - release driver resources 909 * @pdev: PCI-Express device 910 */ 911 static void ismt_remove(struct pci_dev *pdev) 912 { 913 struct ismt_priv *priv = pci_get_drvdata(pdev); 914 915 i2c_del_adapter(&priv->adapter); 916 pci_release_region(pdev, SMBBAR); 917 } 918 919 /** 920 * ismt_suspend() - place the device in suspend 921 * @pdev: PCI-Express device 922 * @mesg: PM message 923 */ 924 #ifdef CONFIG_PM 925 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg) 926 { 927 pci_save_state(pdev); 928 pci_set_power_state(pdev, pci_choose_state(pdev, mesg)); 929 return 0; 930 } 931 932 /** 933 * ismt_resume() - PCI resume code 934 * @pdev: PCI-Express device 935 */ 936 static int ismt_resume(struct pci_dev *pdev) 937 { 938 pci_set_power_state(pdev, PCI_D0); 939 pci_restore_state(pdev); 940 return pci_enable_device(pdev); 941 } 942 943 #else 944 945 #define ismt_suspend NULL 946 #define ismt_resume NULL 947 948 #endif 949 950 static struct pci_driver ismt_driver = { 951 .name = "ismt_smbus", 952 .id_table = ismt_ids, 953 .probe = ismt_probe, 954 .remove = ismt_remove, 955 .suspend = ismt_suspend, 956 .resume = ismt_resume, 957 }; 958 959 module_pci_driver(ismt_driver); 960 961 MODULE_LICENSE("Dual BSD/GPL"); 962 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); 963 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); 964