1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * Copyright(c) 2012 Intel Corporation. All rights reserved. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * The full GNU General Public License is included in this distribution 18 * in the file called LICENSE.GPL. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * * Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * * Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * * Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor 51 * S12xx Product Family. 52 * 53 * Features supported by this driver: 54 * Hardware PEC yes 55 * Block buffer yes 56 * Block process call transaction no 57 * Slave mode no 58 */ 59 60 #include <linux/module.h> 61 #include <linux/pci.h> 62 #include <linux/kernel.h> 63 #include <linux/stddef.h> 64 #include <linux/completion.h> 65 #include <linux/dma-mapping.h> 66 #include <linux/i2c.h> 67 #include <linux/acpi.h> 68 #include <linux/interrupt.h> 69 70 #include <linux/io-64-nonatomic-lo-hi.h> 71 72 /* PCI Address Constants */ 73 #define SMBBAR 0 74 75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ 76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 78 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac 79 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 80 81 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ 82 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 83 84 /* Hardware Descriptor Constants - Control Field */ 85 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 86 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 87 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 88 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 89 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 90 #define ISMT_DESC_INT 0x40 /* Interrupt */ 91 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 92 93 /* Hardware Descriptor Constants - Status Field */ 94 #define ISMT_DESC_SCS 0x01 /* Success */ 95 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 96 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 97 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 98 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 99 #define ISMT_DESC_COL 0x40 /* Collisions */ 100 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 101 102 /* Macros */ 103 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) 104 105 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 106 #define ISMT_GR_GCTRL 0x000 /* General Control */ 107 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 108 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 109 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 110 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 111 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 112 113 /* iSMT Master Registers */ 114 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 115 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 116 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 117 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 118 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 119 120 /* iSMT Miscellaneous Registers */ 121 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 122 123 /* General Control Register (GCTRL) bit definitions */ 124 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 125 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 126 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 127 128 /* Master Control Register (MCTRL) bit definitions */ 129 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 130 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 131 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 132 133 /* Master Status Register (MSTS) bit definitions */ 134 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 135 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 136 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 137 #define ISMT_MSTS_IP 0x01 /* In Progress */ 138 139 /* Master Descriptor Size (MDS) bit definitions */ 140 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 141 142 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 143 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 144 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 145 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 146 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 147 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 148 149 150 /* MSI Control Register (MSICTL) bit definitions */ 151 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 152 153 /* iSMT Hardware Descriptor */ 154 struct ismt_desc { 155 u8 tgtaddr_rw; /* target address & r/w bit */ 156 u8 wr_len_cmd; /* write length in bytes or a command */ 157 u8 rd_len; /* read length */ 158 u8 control; /* control bits */ 159 u8 status; /* status bits */ 160 u8 retry; /* collision retry and retry count */ 161 u8 rxbytes; /* received bytes */ 162 u8 txbytes; /* transmitted bytes */ 163 u32 dptr_low; /* lower 32 bit of the data pointer */ 164 u32 dptr_high; /* upper 32 bit of the data pointer */ 165 } __packed; 166 167 struct ismt_priv { 168 struct i2c_adapter adapter; 169 void __iomem *smba; /* PCI BAR */ 170 struct pci_dev *pci_dev; 171 struct ismt_desc *hw; /* descriptor virt base addr */ 172 dma_addr_t io_rng_dma; /* descriptor HW base addr */ 173 u8 head; /* ring buffer head pointer */ 174 struct completion cmp; /* interrupt completion */ 175 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */ 176 }; 177 178 /** 179 * ismt_ids - PCI device IDs supported by this driver 180 */ 181 static const struct pci_device_id ismt_ids[] = { 182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, 183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, 184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) }, 185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, 186 { 0, } 187 }; 188 189 MODULE_DEVICE_TABLE(pci, ismt_ids); 190 191 /* Bus speed control bits for slow debuggers - refer to the docs for usage */ 192 static unsigned int bus_speed; 193 module_param(bus_speed, uint, S_IRUGO); 194 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); 195 196 /** 197 * __ismt_desc_dump() - dump the contents of a specific descriptor 198 */ 199 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) 200 { 201 202 dev_dbg(dev, "Descriptor struct: %p\n", desc); 203 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); 204 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); 205 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); 206 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); 207 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); 208 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); 209 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); 210 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); 211 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); 212 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); 213 } 214 /** 215 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes 216 * @priv: iSMT private data 217 */ 218 static void ismt_desc_dump(struct ismt_priv *priv) 219 { 220 struct device *dev = &priv->pci_dev->dev; 221 struct ismt_desc *desc = &priv->hw[priv->head]; 222 223 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); 224 __ismt_desc_dump(dev, desc); 225 } 226 227 /** 228 * ismt_gen_reg_dump() - dump the iSMT General Registers 229 * @priv: iSMT private data 230 */ 231 static void ismt_gen_reg_dump(struct ismt_priv *priv) 232 { 233 struct device *dev = &priv->pci_dev->dev; 234 235 dev_dbg(dev, "Dump of the iSMT General Registers\n"); 236 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", 237 priv->smba + ISMT_GR_GCTRL, 238 readl(priv->smba + ISMT_GR_GCTRL)); 239 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", 240 priv->smba + ISMT_GR_SMTICL, 241 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); 242 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", 243 priv->smba + ISMT_GR_ERRINTMSK, 244 readl(priv->smba + ISMT_GR_ERRINTMSK)); 245 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", 246 priv->smba + ISMT_GR_ERRAERMSK, 247 readl(priv->smba + ISMT_GR_ERRAERMSK)); 248 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", 249 priv->smba + ISMT_GR_ERRSTS, 250 readl(priv->smba + ISMT_GR_ERRSTS)); 251 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", 252 priv->smba + ISMT_GR_ERRINFO, 253 readl(priv->smba + ISMT_GR_ERRINFO)); 254 } 255 256 /** 257 * ismt_mstr_reg_dump() - dump the iSMT Master Registers 258 * @priv: iSMT private data 259 */ 260 static void ismt_mstr_reg_dump(struct ismt_priv *priv) 261 { 262 struct device *dev = &priv->pci_dev->dev; 263 264 dev_dbg(dev, "Dump of the iSMT Master Registers\n"); 265 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", 266 priv->smba + ISMT_MSTR_MDBA, 267 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); 268 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", 269 priv->smba + ISMT_MSTR_MCTRL, 270 readl(priv->smba + ISMT_MSTR_MCTRL)); 271 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", 272 priv->smba + ISMT_MSTR_MSTS, 273 readl(priv->smba + ISMT_MSTR_MSTS)); 274 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", 275 priv->smba + ISMT_MSTR_MDS, 276 readl(priv->smba + ISMT_MSTR_MDS)); 277 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", 278 priv->smba + ISMT_MSTR_RPOLICY, 279 readl(priv->smba + ISMT_MSTR_RPOLICY)); 280 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", 281 priv->smba + ISMT_SPGT, 282 readl(priv->smba + ISMT_SPGT)); 283 } 284 285 /** 286 * ismt_submit_desc() - add a descriptor to the ring 287 * @priv: iSMT private data 288 */ 289 static void ismt_submit_desc(struct ismt_priv *priv) 290 { 291 uint fmhp; 292 uint val; 293 294 ismt_desc_dump(priv); 295 ismt_gen_reg_dump(priv); 296 ismt_mstr_reg_dump(priv); 297 298 /* Set the FMHP (Firmware Master Head Pointer)*/ 299 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; 300 val = readl(priv->smba + ISMT_MSTR_MCTRL); 301 writel((val & ~ISMT_MCTRL_FMHP) | fmhp, 302 priv->smba + ISMT_MSTR_MCTRL); 303 304 /* Set the start bit */ 305 val = readl(priv->smba + ISMT_MSTR_MCTRL); 306 writel(val | ISMT_MCTRL_SS, 307 priv->smba + ISMT_MSTR_MCTRL); 308 } 309 310 /** 311 * ismt_process_desc() - handle the completion of the descriptor 312 * @desc: the iSMT hardware descriptor 313 * @data: data buffer from the upper layer 314 * @priv: ismt_priv struct holding our dma buffer 315 * @size: SMBus transaction type 316 * @read_write: flag to indicate if this is a read or write 317 */ 318 static int ismt_process_desc(const struct ismt_desc *desc, 319 union i2c_smbus_data *data, 320 struct ismt_priv *priv, int size, 321 char read_write) 322 { 323 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 324 325 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); 326 __ismt_desc_dump(&priv->pci_dev->dev, desc); 327 ismt_gen_reg_dump(priv); 328 ismt_mstr_reg_dump(priv); 329 330 if (desc->status & ISMT_DESC_SCS) { 331 if (read_write == I2C_SMBUS_WRITE && 332 size != I2C_SMBUS_PROC_CALL) 333 return 0; 334 335 switch (size) { 336 case I2C_SMBUS_BYTE: 337 case I2C_SMBUS_BYTE_DATA: 338 data->byte = dma_buffer[0]; 339 break; 340 case I2C_SMBUS_WORD_DATA: 341 case I2C_SMBUS_PROC_CALL: 342 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 343 break; 344 case I2C_SMBUS_BLOCK_DATA: 345 if (desc->rxbytes != dma_buffer[0] + 1) 346 return -EMSGSIZE; 347 348 memcpy(data->block, dma_buffer, desc->rxbytes); 349 break; 350 case I2C_SMBUS_I2C_BLOCK_DATA: 351 memcpy(&data->block[1], dma_buffer, desc->rxbytes); 352 data->block[0] = desc->rxbytes; 353 break; 354 } 355 return 0; 356 } 357 358 if (likely(desc->status & ISMT_DESC_NAK)) 359 return -ENXIO; 360 361 if (desc->status & ISMT_DESC_CRC) 362 return -EBADMSG; 363 364 if (desc->status & ISMT_DESC_COL) 365 return -EAGAIN; 366 367 if (desc->status & ISMT_DESC_LPR) 368 return -EPROTO; 369 370 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 371 return -ETIMEDOUT; 372 373 return -EIO; 374 } 375 376 /** 377 * ismt_access() - process an SMBus command 378 * @adap: the i2c host adapter 379 * @addr: address of the i2c/SMBus target 380 * @flags: command options 381 * @read_write: read from or write to device 382 * @command: the i2c/SMBus command to issue 383 * @size: SMBus transaction type 384 * @data: read/write data buffer 385 */ 386 static int ismt_access(struct i2c_adapter *adap, u16 addr, 387 unsigned short flags, char read_write, u8 command, 388 int size, union i2c_smbus_data *data) 389 { 390 int ret; 391 unsigned long time_left; 392 dma_addr_t dma_addr = 0; /* address of the data buffer */ 393 u8 dma_size = 0; 394 enum dma_data_direction dma_direction = 0; 395 struct ismt_desc *desc; 396 struct ismt_priv *priv = i2c_get_adapdata(adap); 397 struct device *dev = &priv->pci_dev->dev; 398 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 399 400 desc = &priv->hw[priv->head]; 401 402 /* Initialize the DMA buffer */ 403 memset(priv->buffer, 0, sizeof(priv->buffer)); 404 405 /* Initialize the descriptor */ 406 memset(desc, 0, sizeof(struct ismt_desc)); 407 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); 408 409 /* Initialize common control bits */ 410 if (likely(pci_dev_msi_enabled(priv->pci_dev))) 411 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; 412 else 413 desc->control = ISMT_DESC_FAIR; 414 415 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) 416 && (size != I2C_SMBUS_I2C_BLOCK_DATA)) 417 desc->control |= ISMT_DESC_PEC; 418 419 switch (size) { 420 case I2C_SMBUS_QUICK: 421 dev_dbg(dev, "I2C_SMBUS_QUICK\n"); 422 break; 423 424 case I2C_SMBUS_BYTE: 425 if (read_write == I2C_SMBUS_WRITE) { 426 /* 427 * Send Byte 428 * The command field contains the write data 429 */ 430 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); 431 desc->control |= ISMT_DESC_CWRL; 432 desc->wr_len_cmd = command; 433 } else { 434 /* Receive Byte */ 435 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); 436 dma_size = 1; 437 dma_direction = DMA_FROM_DEVICE; 438 desc->rd_len = 1; 439 } 440 break; 441 442 case I2C_SMBUS_BYTE_DATA: 443 if (read_write == I2C_SMBUS_WRITE) { 444 /* 445 * Write Byte 446 * Command plus 1 data byte 447 */ 448 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); 449 desc->wr_len_cmd = 2; 450 dma_size = 2; 451 dma_direction = DMA_TO_DEVICE; 452 dma_buffer[0] = command; 453 dma_buffer[1] = data->byte; 454 } else { 455 /* Read Byte */ 456 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); 457 desc->control |= ISMT_DESC_CWRL; 458 desc->wr_len_cmd = command; 459 desc->rd_len = 1; 460 dma_size = 1; 461 dma_direction = DMA_FROM_DEVICE; 462 } 463 break; 464 465 case I2C_SMBUS_WORD_DATA: 466 if (read_write == I2C_SMBUS_WRITE) { 467 /* Write Word */ 468 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); 469 desc->wr_len_cmd = 3; 470 dma_size = 3; 471 dma_direction = DMA_TO_DEVICE; 472 dma_buffer[0] = command; 473 dma_buffer[1] = data->word & 0xff; 474 dma_buffer[2] = data->word >> 8; 475 } else { 476 /* Read Word */ 477 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); 478 desc->wr_len_cmd = command; 479 desc->control |= ISMT_DESC_CWRL; 480 desc->rd_len = 2; 481 dma_size = 2; 482 dma_direction = DMA_FROM_DEVICE; 483 } 484 break; 485 486 case I2C_SMBUS_PROC_CALL: 487 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); 488 desc->wr_len_cmd = 3; 489 desc->rd_len = 2; 490 dma_size = 3; 491 dma_direction = DMA_BIDIRECTIONAL; 492 dma_buffer[0] = command; 493 dma_buffer[1] = data->word & 0xff; 494 dma_buffer[2] = data->word >> 8; 495 break; 496 497 case I2C_SMBUS_BLOCK_DATA: 498 if (read_write == I2C_SMBUS_WRITE) { 499 /* Block Write */ 500 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); 501 dma_size = data->block[0] + 1; 502 dma_direction = DMA_TO_DEVICE; 503 desc->wr_len_cmd = dma_size; 504 desc->control |= ISMT_DESC_BLK; 505 dma_buffer[0] = command; 506 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 507 } else { 508 /* Block Read */ 509 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); 510 dma_size = I2C_SMBUS_BLOCK_MAX; 511 dma_direction = DMA_FROM_DEVICE; 512 desc->rd_len = dma_size; 513 desc->wr_len_cmd = command; 514 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); 515 } 516 break; 517 518 case I2C_SMBUS_I2C_BLOCK_DATA: 519 /* Make sure the length is valid */ 520 if (data->block[0] < 1) 521 data->block[0] = 1; 522 523 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 524 data->block[0] = I2C_SMBUS_BLOCK_MAX; 525 526 if (read_write == I2C_SMBUS_WRITE) { 527 /* i2c Block Write */ 528 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n"); 529 dma_size = data->block[0] + 1; 530 dma_direction = DMA_TO_DEVICE; 531 desc->wr_len_cmd = dma_size; 532 desc->control |= ISMT_DESC_I2C; 533 dma_buffer[0] = command; 534 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 535 } else { 536 /* i2c Block Read */ 537 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n"); 538 dma_size = data->block[0]; 539 dma_direction = DMA_FROM_DEVICE; 540 desc->rd_len = dma_size; 541 desc->wr_len_cmd = command; 542 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); 543 /* 544 * Per the "Table 15-15. I2C Commands", 545 * in the External Design Specification (EDS), 546 * (Document Number: 508084, Revision: 2.0), 547 * the _rw bit must be 0 548 */ 549 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); 550 } 551 break; 552 553 default: 554 dev_err(dev, "Unsupported transaction %d\n", 555 size); 556 return -EOPNOTSUPP; 557 } 558 559 /* map the data buffer */ 560 if (dma_size != 0) { 561 dev_dbg(dev, " dev=%p\n", dev); 562 dev_dbg(dev, " data=%p\n", data); 563 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer); 564 dev_dbg(dev, " dma_size=%d\n", dma_size); 565 dev_dbg(dev, " dma_direction=%d\n", dma_direction); 566 567 dma_addr = dma_map_single(dev, 568 dma_buffer, 569 dma_size, 570 dma_direction); 571 572 if (dma_mapping_error(dev, dma_addr)) { 573 dev_err(dev, "Error in mapping dma buffer %p\n", 574 dma_buffer); 575 return -EIO; 576 } 577 578 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr); 579 580 desc->dptr_low = lower_32_bits(dma_addr); 581 desc->dptr_high = upper_32_bits(dma_addr); 582 } 583 584 reinit_completion(&priv->cmp); 585 586 /* Add the descriptor */ 587 ismt_submit_desc(priv); 588 589 /* Now we wait for interrupt completion, 1s */ 590 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1); 591 592 /* unmap the data buffer */ 593 if (dma_size != 0) 594 dma_unmap_single(dev, dma_addr, dma_size, dma_direction); 595 596 if (unlikely(!time_left)) { 597 dev_err(dev, "completion wait timed out\n"); 598 ret = -ETIMEDOUT; 599 goto out; 600 } 601 602 /* do any post processing of the descriptor here */ 603 ret = ismt_process_desc(desc, data, priv, size, read_write); 604 605 out: 606 /* Update the ring pointer */ 607 priv->head++; 608 priv->head %= ISMT_DESC_ENTRIES; 609 610 return ret; 611 } 612 613 /** 614 * ismt_func() - report which i2c commands are supported by this adapter 615 * @adap: the i2c host adapter 616 */ 617 static u32 ismt_func(struct i2c_adapter *adap) 618 { 619 return I2C_FUNC_SMBUS_QUICK | 620 I2C_FUNC_SMBUS_BYTE | 621 I2C_FUNC_SMBUS_BYTE_DATA | 622 I2C_FUNC_SMBUS_WORD_DATA | 623 I2C_FUNC_SMBUS_PROC_CALL | 624 I2C_FUNC_SMBUS_BLOCK_DATA | 625 I2C_FUNC_SMBUS_I2C_BLOCK | 626 I2C_FUNC_SMBUS_PEC; 627 } 628 629 /** 630 * smbus_algorithm - the adapter algorithm and supported functionality 631 * @smbus_xfer: the adapter algorithm 632 * @functionality: functionality supported by the adapter 633 */ 634 static const struct i2c_algorithm smbus_algorithm = { 635 .smbus_xfer = ismt_access, 636 .functionality = ismt_func, 637 }; 638 639 /** 640 * ismt_handle_isr() - interrupt handler bottom half 641 * @priv: iSMT private data 642 */ 643 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) 644 { 645 complete(&priv->cmp); 646 647 return IRQ_HANDLED; 648 } 649 650 651 /** 652 * ismt_do_interrupt() - IRQ interrupt handler 653 * @vec: interrupt vector 654 * @data: iSMT private data 655 */ 656 static irqreturn_t ismt_do_interrupt(int vec, void *data) 657 { 658 u32 val; 659 struct ismt_priv *priv = data; 660 661 /* 662 * check to see it's our interrupt, return IRQ_NONE if not ours 663 * since we are sharing interrupt 664 */ 665 val = readl(priv->smba + ISMT_MSTR_MSTS); 666 667 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) 668 return IRQ_NONE; 669 else 670 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, 671 priv->smba + ISMT_MSTR_MSTS); 672 673 return ismt_handle_isr(priv); 674 } 675 676 /** 677 * ismt_do_msi_interrupt() - MSI interrupt handler 678 * @vec: interrupt vector 679 * @data: iSMT private data 680 */ 681 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) 682 { 683 return ismt_handle_isr(data); 684 } 685 686 /** 687 * ismt_hw_init() - initialize the iSMT hardware 688 * @priv: iSMT private data 689 */ 690 static void ismt_hw_init(struct ismt_priv *priv) 691 { 692 u32 val; 693 struct device *dev = &priv->pci_dev->dev; 694 695 /* initialize the Master Descriptor Base Address (MDBA) */ 696 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); 697 698 /* initialize the Master Control Register (MCTRL) */ 699 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); 700 701 /* initialize the Master Status Register (MSTS) */ 702 writel(0, priv->smba + ISMT_MSTR_MSTS); 703 704 /* initialize the Master Descriptor Size (MDS) */ 705 val = readl(priv->smba + ISMT_MSTR_MDS); 706 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), 707 priv->smba + ISMT_MSTR_MDS); 708 709 /* 710 * Set the SMBus speed (could use this for slow HW debuggers) 711 */ 712 713 val = readl(priv->smba + ISMT_SPGT); 714 715 switch (bus_speed) { 716 case 0: 717 break; 718 719 case 80: 720 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); 721 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), 722 priv->smba + ISMT_SPGT); 723 break; 724 725 case 100: 726 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); 727 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), 728 priv->smba + ISMT_SPGT); 729 break; 730 731 case 400: 732 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); 733 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), 734 priv->smba + ISMT_SPGT); 735 break; 736 737 case 1000: 738 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); 739 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), 740 priv->smba + ISMT_SPGT); 741 break; 742 743 default: 744 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); 745 break; 746 } 747 748 val = readl(priv->smba + ISMT_SPGT); 749 750 switch (val & ISMT_SPGT_SPD_MASK) { 751 case ISMT_SPGT_SPD_80K: 752 bus_speed = 80; 753 break; 754 case ISMT_SPGT_SPD_100K: 755 bus_speed = 100; 756 break; 757 case ISMT_SPGT_SPD_400K: 758 bus_speed = 400; 759 break; 760 case ISMT_SPGT_SPD_1M: 761 bus_speed = 1000; 762 break; 763 } 764 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); 765 } 766 767 /** 768 * ismt_dev_init() - initialize the iSMT data structures 769 * @priv: iSMT private data 770 */ 771 static int ismt_dev_init(struct ismt_priv *priv) 772 { 773 /* allocate memory for the descriptor */ 774 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, 775 (ISMT_DESC_ENTRIES 776 * sizeof(struct ismt_desc)), 777 &priv->io_rng_dma, 778 GFP_KERNEL); 779 if (!priv->hw) 780 return -ENOMEM; 781 782 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))); 783 784 priv->head = 0; 785 init_completion(&priv->cmp); 786 787 return 0; 788 } 789 790 /** 791 * ismt_int_init() - initialize interrupts 792 * @priv: iSMT private data 793 */ 794 static int ismt_int_init(struct ismt_priv *priv) 795 { 796 int err; 797 798 /* Try using MSI interrupts */ 799 err = pci_enable_msi(priv->pci_dev); 800 if (err) 801 goto intx; 802 803 err = devm_request_irq(&priv->pci_dev->dev, 804 priv->pci_dev->irq, 805 ismt_do_msi_interrupt, 806 0, 807 "ismt-msi", 808 priv); 809 if (err) { 810 pci_disable_msi(priv->pci_dev); 811 goto intx; 812 } 813 814 return 0; 815 816 /* Try using legacy interrupts */ 817 intx: 818 dev_warn(&priv->pci_dev->dev, 819 "Unable to use MSI interrupts, falling back to legacy\n"); 820 821 err = devm_request_irq(&priv->pci_dev->dev, 822 priv->pci_dev->irq, 823 ismt_do_interrupt, 824 IRQF_SHARED, 825 "ismt-intx", 826 priv); 827 if (err) { 828 dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); 829 return err; 830 } 831 832 return 0; 833 } 834 835 static struct pci_driver ismt_driver; 836 837 /** 838 * ismt_probe() - probe for iSMT devices 839 * @pdev: PCI-Express device 840 * @id: PCI-Express device ID 841 */ 842 static int 843 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) 844 { 845 int err; 846 struct ismt_priv *priv; 847 unsigned long start, len; 848 849 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 850 if (!priv) 851 return -ENOMEM; 852 853 pci_set_drvdata(pdev, priv); 854 855 i2c_set_adapdata(&priv->adapter, priv); 856 priv->adapter.owner = THIS_MODULE; 857 priv->adapter.class = I2C_CLASS_HWMON; 858 priv->adapter.algo = &smbus_algorithm; 859 priv->adapter.dev.parent = &pdev->dev; 860 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 861 priv->adapter.retries = ISMT_MAX_RETRIES; 862 863 priv->pci_dev = pdev; 864 865 err = pcim_enable_device(pdev); 866 if (err) { 867 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", 868 err); 869 return err; 870 } 871 872 /* enable bus mastering */ 873 pci_set_master(pdev); 874 875 /* Determine the address of the SMBus area */ 876 start = pci_resource_start(pdev, SMBBAR); 877 len = pci_resource_len(pdev, SMBBAR); 878 if (!start || !len) { 879 dev_err(&pdev->dev, 880 "SMBus base address uninitialized, upgrade BIOS\n"); 881 return -ENODEV; 882 } 883 884 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 885 "SMBus iSMT adapter at %lx", start); 886 887 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); 888 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); 889 890 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); 891 if (err) { 892 dev_err(&pdev->dev, "ACPI resource conflict!\n"); 893 return err; 894 } 895 896 err = pci_request_region(pdev, SMBBAR, ismt_driver.name); 897 if (err) { 898 dev_err(&pdev->dev, 899 "Failed to request SMBus region 0x%lx-0x%lx\n", 900 start, start + len); 901 return err; 902 } 903 904 priv->smba = pcim_iomap(pdev, SMBBAR, len); 905 if (!priv->smba) { 906 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); 907 return -ENODEV; 908 } 909 910 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 911 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 912 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 913 (pci_set_consistent_dma_mask(pdev, 914 DMA_BIT_MASK(32)) != 0)) { 915 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", 916 pdev); 917 return -ENODEV; 918 } 919 } 920 921 err = ismt_dev_init(priv); 922 if (err) 923 return err; 924 925 ismt_hw_init(priv); 926 927 err = ismt_int_init(priv); 928 if (err) 929 return err; 930 931 err = i2c_add_adapter(&priv->adapter); 932 if (err) 933 return -ENODEV; 934 return 0; 935 } 936 937 /** 938 * ismt_remove() - release driver resources 939 * @pdev: PCI-Express device 940 */ 941 static void ismt_remove(struct pci_dev *pdev) 942 { 943 struct ismt_priv *priv = pci_get_drvdata(pdev); 944 945 i2c_del_adapter(&priv->adapter); 946 } 947 948 static struct pci_driver ismt_driver = { 949 .name = "ismt_smbus", 950 .id_table = ismt_ids, 951 .probe = ismt_probe, 952 .remove = ismt_remove, 953 }; 954 955 module_pci_driver(ismt_driver); 956 957 MODULE_LICENSE("Dual BSD/GPL"); 958 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); 959 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); 960