1 /* 2 i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus 3 - Based on i2c-piix4.c 4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 5 Philip Edelbrock <phil@netroedge.com> 6 - Intel SCH support 7 Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License version 2 as 11 published by the Free Software Foundation. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 Supports: 25 Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L) 26 Note: we assume there can only be one device, with one SMBus interface. 27 */ 28 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/kernel.h> 32 #include <linux/delay.h> 33 #include <linux/stddef.h> 34 #include <linux/ioport.h> 35 #include <linux/i2c.h> 36 #include <linux/init.h> 37 #include <linux/io.h> 38 #include <linux/acpi.h> 39 40 /* SCH SMBus address offsets */ 41 #define SMBHSTCNT (0 + sch_smba) 42 #define SMBHSTSTS (1 + sch_smba) 43 #define SMBHSTADD (4 + sch_smba) /* TSA */ 44 #define SMBHSTCMD (5 + sch_smba) 45 #define SMBHSTDAT0 (6 + sch_smba) 46 #define SMBHSTDAT1 (7 + sch_smba) 47 #define SMBBLKDAT (0x20 + sch_smba) 48 49 /* count for request_region */ 50 #define SMBIOSIZE 64 51 52 /* PCI Address Constants */ 53 #define SMBBA_SCH 0x40 54 55 /* Other settings */ 56 #define MAX_TIMEOUT 500 57 58 /* I2C constants */ 59 #define SCH_QUICK 0x00 60 #define SCH_BYTE 0x01 61 #define SCH_BYTE_DATA 0x02 62 #define SCH_WORD_DATA 0x03 63 #define SCH_BLOCK_DATA 0x05 64 65 static unsigned short sch_smba; 66 static struct pci_driver sch_driver; 67 static struct i2c_adapter sch_adapter; 68 69 /* 70 * Start the i2c transaction -- the i2c_access will prepare the transaction 71 * and this function will execute it. 72 * return 0 for success and others for failure. 73 */ 74 static int sch_transaction(void) 75 { 76 int temp; 77 int result = 0; 78 int timeout = 0; 79 80 dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 81 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), 82 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), 83 inb(SMBHSTDAT1)); 84 85 /* Make sure the SMBus host is ready to start transmitting */ 86 temp = inb(SMBHSTSTS) & 0x0f; 87 if (temp) { 88 /* Can not be busy since we checked it in sch_access */ 89 if (temp & 0x01) { 90 dev_dbg(&sch_adapter.dev, "Completion (%02x). " 91 "Clear...\n", temp); 92 } 93 if (temp & 0x06) { 94 dev_dbg(&sch_adapter.dev, "SMBus error (%02x). " 95 "Resetting...\n", temp); 96 } 97 outb(temp, SMBHSTSTS); 98 temp = inb(SMBHSTSTS) & 0x0f; 99 if (temp) { 100 dev_err(&sch_adapter.dev, 101 "SMBus is not ready: (%02x)\n", temp); 102 return -EAGAIN; 103 } 104 } 105 106 /* start the transaction by setting bit 4 */ 107 outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT); 108 109 do { 110 msleep(1); 111 temp = inb(SMBHSTSTS) & 0x0f; 112 } while ((temp & 0x08) && (timeout++ < MAX_TIMEOUT)); 113 114 /* If the SMBus is still busy, we give up */ 115 if (timeout > MAX_TIMEOUT) { 116 dev_err(&sch_adapter.dev, "SMBus Timeout!\n"); 117 result = -ETIMEDOUT; 118 } 119 if (temp & 0x04) { 120 result = -EIO; 121 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be " 122 "locked until next hard reset. (sorry!)\n"); 123 /* Clock stops and slave is stuck in mid-transmission */ 124 } else if (temp & 0x02) { 125 result = -EIO; 126 dev_err(&sch_adapter.dev, "Error: no response!\n"); 127 } else if (temp & 0x01) { 128 dev_dbg(&sch_adapter.dev, "Post complete!\n"); 129 outb(temp, SMBHSTSTS); 130 temp = inb(SMBHSTSTS) & 0x07; 131 if (temp & 0x06) { 132 /* Completion clear failed */ 133 dev_dbg(&sch_adapter.dev, "Failed reset at end of " 134 "transaction (%02x), Bus error!\n", temp); 135 } 136 } else { 137 result = -ENXIO; 138 dev_dbg(&sch_adapter.dev, "No such address.\n"); 139 } 140 dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, " 141 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), 142 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), 143 inb(SMBHSTDAT1)); 144 return result; 145 } 146 147 /* 148 * This is the main access entry for i2c-sch access 149 * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write 150 * (0 for read and 1 for write), size is i2c transaction type and data is the 151 * union of transaction for data to be transfered or data read from bus. 152 * return 0 for success and others for failure. 153 */ 154 static s32 sch_access(struct i2c_adapter *adap, u16 addr, 155 unsigned short flags, char read_write, 156 u8 command, int size, union i2c_smbus_data *data) 157 { 158 int i, len, temp, rc; 159 160 /* Make sure the SMBus host is not busy */ 161 temp = inb(SMBHSTSTS) & 0x0f; 162 if (temp & 0x08) { 163 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp); 164 return -EAGAIN; 165 } 166 dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size, 167 (read_write)?"READ":"WRITE"); 168 switch (size) { 169 case I2C_SMBUS_QUICK: 170 outb((addr << 1) | read_write, SMBHSTADD); 171 size = SCH_QUICK; 172 break; 173 case I2C_SMBUS_BYTE: 174 outb((addr << 1) | read_write, SMBHSTADD); 175 if (read_write == I2C_SMBUS_WRITE) 176 outb(command, SMBHSTCMD); 177 size = SCH_BYTE; 178 break; 179 case I2C_SMBUS_BYTE_DATA: 180 outb((addr << 1) | read_write, SMBHSTADD); 181 outb(command, SMBHSTCMD); 182 if (read_write == I2C_SMBUS_WRITE) 183 outb(data->byte, SMBHSTDAT0); 184 size = SCH_BYTE_DATA; 185 break; 186 case I2C_SMBUS_WORD_DATA: 187 outb((addr << 1) | read_write, SMBHSTADD); 188 outb(command, SMBHSTCMD); 189 if (read_write == I2C_SMBUS_WRITE) { 190 outb(data->word & 0xff, SMBHSTDAT0); 191 outb((data->word & 0xff00) >> 8, SMBHSTDAT1); 192 } 193 size = SCH_WORD_DATA; 194 break; 195 case I2C_SMBUS_BLOCK_DATA: 196 outb((addr << 1) | read_write, SMBHSTADD); 197 outb(command, SMBHSTCMD); 198 if (read_write == I2C_SMBUS_WRITE) { 199 len = data->block[0]; 200 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 201 return -EINVAL; 202 outb(len, SMBHSTDAT0); 203 for (i = 1; i <= len; i++) 204 outb(data->block[i], SMBBLKDAT+i-1); 205 } 206 size = SCH_BLOCK_DATA; 207 break; 208 default: 209 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 210 return -EOPNOTSUPP; 211 } 212 dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT); 213 outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT); 214 215 rc = sch_transaction(); 216 if (rc) /* Error in transaction */ 217 return rc; 218 219 if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK)) 220 return 0; 221 222 switch (size) { 223 case SCH_BYTE: 224 case SCH_BYTE_DATA: 225 data->byte = inb(SMBHSTDAT0); 226 break; 227 case SCH_WORD_DATA: 228 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8); 229 break; 230 case SCH_BLOCK_DATA: 231 data->block[0] = inb(SMBHSTDAT0); 232 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 233 return -EPROTO; 234 for (i = 1; i <= data->block[0]; i++) 235 data->block[i] = inb(SMBBLKDAT+i-1); 236 break; 237 } 238 return 0; 239 } 240 241 static u32 sch_func(struct i2c_adapter *adapter) 242 { 243 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 244 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 245 I2C_FUNC_SMBUS_BLOCK_DATA; 246 } 247 248 static const struct i2c_algorithm smbus_algorithm = { 249 .smbus_xfer = sch_access, 250 .functionality = sch_func, 251 }; 252 253 static struct i2c_adapter sch_adapter = { 254 .owner = THIS_MODULE, 255 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 256 .algo = &smbus_algorithm, 257 }; 258 259 static struct pci_device_id sch_ids[] = { 260 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) }, 261 { 0, } 262 }; 263 264 MODULE_DEVICE_TABLE(pci, sch_ids); 265 266 static int __devinit sch_probe(struct pci_dev *dev, 267 const struct pci_device_id *id) 268 { 269 int retval; 270 unsigned int smba; 271 272 pci_read_config_dword(dev, SMBBA_SCH, &smba); 273 if (!(smba & (1 << 31))) { 274 dev_err(&dev->dev, "SMBus I/O space disabled!\n"); 275 return -ENODEV; 276 } 277 278 sch_smba = (unsigned short)smba; 279 if (sch_smba == 0) { 280 dev_err(&dev->dev, "SMBus base address uninitialized!\n"); 281 return -ENODEV; 282 } 283 if (acpi_check_region(sch_smba, SMBIOSIZE, sch_driver.name)) 284 return -ENODEV; 285 if (!request_region(sch_smba, SMBIOSIZE, sch_driver.name)) { 286 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n", 287 sch_smba); 288 return -EBUSY; 289 } 290 dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba); 291 292 /* set up the sysfs linkage to our parent device */ 293 sch_adapter.dev.parent = &dev->dev; 294 295 snprintf(sch_adapter.name, sizeof(sch_adapter.name), 296 "SMBus SCH adapter at %04x", sch_smba); 297 298 retval = i2c_add_adapter(&sch_adapter); 299 if (retval) { 300 dev_err(&dev->dev, "Couldn't register adapter!\n"); 301 release_region(sch_smba, SMBIOSIZE); 302 sch_smba = 0; 303 } 304 305 return retval; 306 } 307 308 static void __devexit sch_remove(struct pci_dev *dev) 309 { 310 if (sch_smba) { 311 i2c_del_adapter(&sch_adapter); 312 release_region(sch_smba, SMBIOSIZE); 313 sch_smba = 0; 314 } 315 } 316 317 static struct pci_driver sch_driver = { 318 .name = "isch_smbus", 319 .id_table = sch_ids, 320 .probe = sch_probe, 321 .remove = __devexit_p(sch_remove), 322 }; 323 324 static int __init i2c_sch_init(void) 325 { 326 return pci_register_driver(&sch_driver); 327 } 328 329 static void __exit i2c_sch_exit(void) 330 { 331 pci_unregister_driver(&sch_driver); 332 } 333 334 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 335 MODULE_DESCRIPTION("Intel SCH SMBus driver"); 336 MODULE_LICENSE("GPL"); 337 338 module_init(i2c_sch_init); 339 module_exit(i2c_sch_exit); 340