1 /* 2 i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus 3 - Based on i2c-piix4.c 4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 5 Philip Edelbrock <phil@netroedge.com> 6 - Intel SCH support 7 Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License version 2 as 11 published by the Free Software Foundation. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 */ 18 19 /* 20 Supports: 21 Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L) 22 Note: we assume there can only be one device, with one SMBus interface. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/kernel.h> 28 #include <linux/delay.h> 29 #include <linux/stddef.h> 30 #include <linux/ioport.h> 31 #include <linux/i2c.h> 32 #include <linux/io.h> 33 34 /* SCH SMBus address offsets */ 35 #define SMBHSTCNT (0 + sch_smba) 36 #define SMBHSTSTS (1 + sch_smba) 37 #define SMBHSTCLK (2 + sch_smba) 38 #define SMBHSTADD (4 + sch_smba) /* TSA */ 39 #define SMBHSTCMD (5 + sch_smba) 40 #define SMBHSTDAT0 (6 + sch_smba) 41 #define SMBHSTDAT1 (7 + sch_smba) 42 #define SMBBLKDAT (0x20 + sch_smba) 43 44 /* Other settings */ 45 #define MAX_RETRIES 5000 46 47 /* I2C constants */ 48 #define SCH_QUICK 0x00 49 #define SCH_BYTE 0x01 50 #define SCH_BYTE_DATA 0x02 51 #define SCH_WORD_DATA 0x03 52 #define SCH_BLOCK_DATA 0x05 53 54 static unsigned short sch_smba; 55 static struct i2c_adapter sch_adapter; 56 static int backbone_speed = 33000; /* backbone speed in kHz */ 57 module_param(backbone_speed, int, S_IRUSR | S_IWUSR); 58 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)"); 59 60 /* 61 * Start the i2c transaction -- the i2c_access will prepare the transaction 62 * and this function will execute it. 63 * return 0 for success and others for failure. 64 */ 65 static int sch_transaction(void) 66 { 67 int temp; 68 int result = 0; 69 int retries = 0; 70 71 dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 72 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), 73 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), 74 inb(SMBHSTDAT1)); 75 76 /* Make sure the SMBus host is ready to start transmitting */ 77 temp = inb(SMBHSTSTS) & 0x0f; 78 if (temp) { 79 /* Can not be busy since we checked it in sch_access */ 80 if (temp & 0x01) { 81 dev_dbg(&sch_adapter.dev, "Completion (%02x). " 82 "Clear...\n", temp); 83 } 84 if (temp & 0x06) { 85 dev_dbg(&sch_adapter.dev, "SMBus error (%02x). " 86 "Resetting...\n", temp); 87 } 88 outb(temp, SMBHSTSTS); 89 temp = inb(SMBHSTSTS) & 0x0f; 90 if (temp) { 91 dev_err(&sch_adapter.dev, 92 "SMBus is not ready: (%02x)\n", temp); 93 return -EAGAIN; 94 } 95 } 96 97 /* start the transaction by setting bit 4 */ 98 outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT); 99 100 do { 101 usleep_range(100, 200); 102 temp = inb(SMBHSTSTS) & 0x0f; 103 } while ((temp & 0x08) && (retries++ < MAX_RETRIES)); 104 105 /* If the SMBus is still busy, we give up */ 106 if (retries > MAX_RETRIES) { 107 dev_err(&sch_adapter.dev, "SMBus Timeout!\n"); 108 result = -ETIMEDOUT; 109 } 110 if (temp & 0x04) { 111 result = -EIO; 112 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be " 113 "locked until next hard reset. (sorry!)\n"); 114 /* Clock stops and slave is stuck in mid-transmission */ 115 } else if (temp & 0x02) { 116 result = -EIO; 117 dev_err(&sch_adapter.dev, "Error: no response!\n"); 118 } else if (temp & 0x01) { 119 dev_dbg(&sch_adapter.dev, "Post complete!\n"); 120 outb(temp, SMBHSTSTS); 121 temp = inb(SMBHSTSTS) & 0x07; 122 if (temp & 0x06) { 123 /* Completion clear failed */ 124 dev_dbg(&sch_adapter.dev, "Failed reset at end of " 125 "transaction (%02x), Bus error!\n", temp); 126 } 127 } else { 128 result = -ENXIO; 129 dev_dbg(&sch_adapter.dev, "No such address.\n"); 130 } 131 dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, " 132 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), 133 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), 134 inb(SMBHSTDAT1)); 135 return result; 136 } 137 138 /* 139 * This is the main access entry for i2c-sch access 140 * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write 141 * (0 for read and 1 for write), size is i2c transaction type and data is the 142 * union of transaction for data to be transferred or data read from bus. 143 * return 0 for success and others for failure. 144 */ 145 static s32 sch_access(struct i2c_adapter *adap, u16 addr, 146 unsigned short flags, char read_write, 147 u8 command, int size, union i2c_smbus_data *data) 148 { 149 int i, len, temp, rc; 150 151 /* Make sure the SMBus host is not busy */ 152 temp = inb(SMBHSTSTS) & 0x0f; 153 if (temp & 0x08) { 154 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp); 155 return -EAGAIN; 156 } 157 temp = inw(SMBHSTCLK); 158 if (!temp) { 159 /* 160 * We can't determine if we have 33 or 25 MHz clock for 161 * SMBus, so expect 33 MHz and calculate a bus clock of 162 * 100 kHz. If we actually run at 25 MHz the bus will be 163 * run ~75 kHz instead which should do no harm. 164 */ 165 dev_notice(&sch_adapter.dev, 166 "Clock divider uninitialized. Setting defaults\n"); 167 outw(backbone_speed / (4 * 100), SMBHSTCLK); 168 } 169 170 dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size, 171 (read_write)?"READ":"WRITE"); 172 switch (size) { 173 case I2C_SMBUS_QUICK: 174 outb((addr << 1) | read_write, SMBHSTADD); 175 size = SCH_QUICK; 176 break; 177 case I2C_SMBUS_BYTE: 178 outb((addr << 1) | read_write, SMBHSTADD); 179 if (read_write == I2C_SMBUS_WRITE) 180 outb(command, SMBHSTCMD); 181 size = SCH_BYTE; 182 break; 183 case I2C_SMBUS_BYTE_DATA: 184 outb((addr << 1) | read_write, SMBHSTADD); 185 outb(command, SMBHSTCMD); 186 if (read_write == I2C_SMBUS_WRITE) 187 outb(data->byte, SMBHSTDAT0); 188 size = SCH_BYTE_DATA; 189 break; 190 case I2C_SMBUS_WORD_DATA: 191 outb((addr << 1) | read_write, SMBHSTADD); 192 outb(command, SMBHSTCMD); 193 if (read_write == I2C_SMBUS_WRITE) { 194 outb(data->word & 0xff, SMBHSTDAT0); 195 outb((data->word & 0xff00) >> 8, SMBHSTDAT1); 196 } 197 size = SCH_WORD_DATA; 198 break; 199 case I2C_SMBUS_BLOCK_DATA: 200 outb((addr << 1) | read_write, SMBHSTADD); 201 outb(command, SMBHSTCMD); 202 if (read_write == I2C_SMBUS_WRITE) { 203 len = data->block[0]; 204 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 205 return -EINVAL; 206 outb(len, SMBHSTDAT0); 207 for (i = 1; i <= len; i++) 208 outb(data->block[i], SMBBLKDAT+i-1); 209 } 210 size = SCH_BLOCK_DATA; 211 break; 212 default: 213 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 214 return -EOPNOTSUPP; 215 } 216 dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT); 217 outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT); 218 219 rc = sch_transaction(); 220 if (rc) /* Error in transaction */ 221 return rc; 222 223 if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK)) 224 return 0; 225 226 switch (size) { 227 case SCH_BYTE: 228 case SCH_BYTE_DATA: 229 data->byte = inb(SMBHSTDAT0); 230 break; 231 case SCH_WORD_DATA: 232 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8); 233 break; 234 case SCH_BLOCK_DATA: 235 data->block[0] = inb(SMBHSTDAT0); 236 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 237 return -EPROTO; 238 for (i = 1; i <= data->block[0]; i++) 239 data->block[i] = inb(SMBBLKDAT+i-1); 240 break; 241 } 242 return 0; 243 } 244 245 static u32 sch_func(struct i2c_adapter *adapter) 246 { 247 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 248 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 249 I2C_FUNC_SMBUS_BLOCK_DATA; 250 } 251 252 static const struct i2c_algorithm smbus_algorithm = { 253 .smbus_xfer = sch_access, 254 .functionality = sch_func, 255 }; 256 257 static struct i2c_adapter sch_adapter = { 258 .owner = THIS_MODULE, 259 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 260 .algo = &smbus_algorithm, 261 }; 262 263 static int smbus_sch_probe(struct platform_device *dev) 264 { 265 struct resource *res; 266 int retval; 267 268 res = platform_get_resource(dev, IORESOURCE_IO, 0); 269 if (!res) 270 return -EBUSY; 271 272 if (!devm_request_region(&dev->dev, res->start, resource_size(res), 273 dev->name)) { 274 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n", 275 sch_smba); 276 return -EBUSY; 277 } 278 279 sch_smba = res->start; 280 281 dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba); 282 283 /* set up the sysfs linkage to our parent device */ 284 sch_adapter.dev.parent = &dev->dev; 285 286 snprintf(sch_adapter.name, sizeof(sch_adapter.name), 287 "SMBus SCH adapter at %04x", sch_smba); 288 289 retval = i2c_add_adapter(&sch_adapter); 290 if (retval) 291 sch_smba = 0; 292 293 return retval; 294 } 295 296 static int smbus_sch_remove(struct platform_device *pdev) 297 { 298 if (sch_smba) { 299 i2c_del_adapter(&sch_adapter); 300 sch_smba = 0; 301 } 302 303 return 0; 304 } 305 306 static struct platform_driver smbus_sch_driver = { 307 .driver = { 308 .name = "isch_smbus", 309 }, 310 .probe = smbus_sch_probe, 311 .remove = smbus_sch_remove, 312 }; 313 314 module_platform_driver(smbus_sch_driver); 315 316 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 317 MODULE_DESCRIPTION("Intel SCH SMBus driver"); 318 MODULE_LICENSE("GPL"); 319 MODULE_ALIAS("platform:isch_smbus"); 320