1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/of_dma.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/platform_data/i2c-imx.h> 46 #include <linux/platform_device.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/sched.h> 49 #include <linux/slab.h> 50 51 /* This will be the driver name the kernel reports */ 52 #define DRIVER_NAME "imx-i2c" 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 /* 78 * All of the layerscape series SoCs support IBIC register. 79 */ 80 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 81 82 #define IMX_I2C_REGSHIFT 2 83 #define VF610_I2C_REGSHIFT 0 84 85 /* Bits of IMX I2C registers */ 86 #define I2SR_RXAK 0x01 87 #define I2SR_IIF 0x02 88 #define I2SR_SRW 0x04 89 #define I2SR_IAL 0x10 90 #define I2SR_IBB 0x20 91 #define I2SR_IAAS 0x40 92 #define I2SR_ICF 0x80 93 #define I2CR_DMAEN 0x02 94 #define I2CR_RSTA 0x04 95 #define I2CR_TXAK 0x08 96 #define I2CR_MTX 0x10 97 #define I2CR_MSTA 0x20 98 #define I2CR_IIEN 0x40 99 #define I2CR_IEN 0x80 100 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 101 102 /* register bits different operating codes definition: 103 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 104 * - write zero to clear(w0c) INT flag on i.MX, 105 * - but write one to clear(w1c) INT flag on Vybrid. 106 * 2) I2CR: I2C module enable operation also differ between SoCs: 107 * - set I2CR_IEN bit enable the module on i.MX, 108 * - but clear I2CR_IEN bit enable the module on Vybrid. 109 */ 110 #define I2SR_CLR_OPCODE_W0C 0x0 111 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 112 #define I2CR_IEN_OPCODE_0 0x0 113 #define I2CR_IEN_OPCODE_1 I2CR_IEN 114 115 #define I2C_PM_TIMEOUT 10 /* ms */ 116 117 /* 118 * sorted list of clock divider, register value pairs 119 * taken from table 26-5, p.26-9, Freescale i.MX 120 * Integrated Portable System Processor Reference Manual 121 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 122 * 123 * Duplicated divider values removed from list 124 */ 125 struct imx_i2c_clk_pair { 126 u16 div; 127 u16 val; 128 }; 129 130 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 131 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 132 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 133 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 134 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 135 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 136 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 137 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 138 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 139 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 140 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 141 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 142 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 143 { 3072, 0x1E }, { 3840, 0x1F } 144 }; 145 146 /* Vybrid VF610 clock divider, register value pairs */ 147 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 148 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 149 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 150 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 151 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 152 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 153 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 154 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 155 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 156 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 157 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 158 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 159 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 160 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 161 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 162 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 163 }; 164 165 enum imx_i2c_type { 166 IMX1_I2C, 167 IMX21_I2C, 168 VF610_I2C, 169 }; 170 171 struct imx_i2c_hwdata { 172 enum imx_i2c_type devtype; 173 unsigned regshift; 174 struct imx_i2c_clk_pair *clk_div; 175 unsigned ndivs; 176 unsigned i2sr_clr_opcode; 177 unsigned i2cr_ien_opcode; 178 }; 179 180 struct imx_i2c_dma { 181 struct dma_chan *chan_tx; 182 struct dma_chan *chan_rx; 183 struct dma_chan *chan_using; 184 struct completion cmd_complete; 185 dma_addr_t dma_buf; 186 unsigned int dma_len; 187 enum dma_transfer_direction dma_transfer_dir; 188 enum dma_data_direction dma_data_dir; 189 }; 190 191 struct imx_i2c_struct { 192 struct i2c_adapter adapter; 193 struct clk *clk; 194 struct notifier_block clk_change_nb; 195 void __iomem *base; 196 wait_queue_head_t queue; 197 unsigned long i2csr; 198 unsigned int disable_delay; 199 int stopped; 200 unsigned int ifdr; /* IMX_I2C_IFDR */ 201 unsigned int cur_clk; 202 unsigned int bitrate; 203 const struct imx_i2c_hwdata *hwdata; 204 struct i2c_bus_recovery_info rinfo; 205 206 struct pinctrl *pinctrl; 207 struct pinctrl_state *pinctrl_pins_default; 208 struct pinctrl_state *pinctrl_pins_gpio; 209 210 struct imx_i2c_dma *dma; 211 struct i2c_client *slave; 212 }; 213 214 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 215 .devtype = IMX1_I2C, 216 .regshift = IMX_I2C_REGSHIFT, 217 .clk_div = imx_i2c_clk_div, 218 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 219 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 220 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 221 222 }; 223 224 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 225 .devtype = IMX21_I2C, 226 .regshift = IMX_I2C_REGSHIFT, 227 .clk_div = imx_i2c_clk_div, 228 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 229 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 230 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 231 232 }; 233 234 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 235 .devtype = VF610_I2C, 236 .regshift = VF610_I2C_REGSHIFT, 237 .clk_div = vf610_i2c_clk_div, 238 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 239 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 240 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 241 242 }; 243 244 static const struct platform_device_id imx_i2c_devtype[] = { 245 { 246 .name = "imx1-i2c", 247 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 248 }, { 249 .name = "imx21-i2c", 250 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 251 }, { 252 /* sentinel */ 253 } 254 }; 255 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 256 257 static const struct of_device_id i2c_imx_dt_ids[] = { 258 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 259 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 260 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 261 { /* sentinel */ } 262 }; 263 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 264 265 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 266 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 267 { } 268 }; 269 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 270 271 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 272 { 273 return i2c_imx->hwdata->devtype == IMX1_I2C; 274 } 275 276 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 277 { 278 return i2c_imx->hwdata->devtype == VF610_I2C; 279 } 280 281 static inline void imx_i2c_write_reg(unsigned int val, 282 struct imx_i2c_struct *i2c_imx, unsigned int reg) 283 { 284 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 285 } 286 287 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 288 unsigned int reg) 289 { 290 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 291 } 292 293 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 294 { 295 unsigned int temp; 296 297 /* 298 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 299 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 300 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 301 */ 302 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 303 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 304 } 305 306 /* Set up i2c controller register and i2c status register to default value. */ 307 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 308 { 309 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 310 i2c_imx, IMX_I2C_I2CR); 311 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 312 } 313 314 /* Functions for DMA support */ 315 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 316 dma_addr_t phy_addr) 317 { 318 struct imx_i2c_dma *dma; 319 struct dma_slave_config dma_sconfig; 320 struct device *dev = &i2c_imx->adapter.dev; 321 int ret; 322 323 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 324 if (!dma) 325 return; 326 327 dma->chan_tx = dma_request_chan(dev, "tx"); 328 if (IS_ERR(dma->chan_tx)) { 329 ret = PTR_ERR(dma->chan_tx); 330 if (ret != -ENODEV && ret != -EPROBE_DEFER) 331 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 332 goto fail_al; 333 } 334 335 dma_sconfig.dst_addr = phy_addr + 336 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 337 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 338 dma_sconfig.dst_maxburst = 1; 339 dma_sconfig.direction = DMA_MEM_TO_DEV; 340 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 341 if (ret < 0) { 342 dev_err(dev, "can't configure tx channel (%d)\n", ret); 343 goto fail_tx; 344 } 345 346 dma->chan_rx = dma_request_chan(dev, "rx"); 347 if (IS_ERR(dma->chan_rx)) { 348 ret = PTR_ERR(dma->chan_rx); 349 if (ret != -ENODEV && ret != -EPROBE_DEFER) 350 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 351 goto fail_tx; 352 } 353 354 dma_sconfig.src_addr = phy_addr + 355 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 356 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 357 dma_sconfig.src_maxburst = 1; 358 dma_sconfig.direction = DMA_DEV_TO_MEM; 359 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 360 if (ret < 0) { 361 dev_err(dev, "can't configure rx channel (%d)\n", ret); 362 goto fail_rx; 363 } 364 365 i2c_imx->dma = dma; 366 init_completion(&dma->cmd_complete); 367 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 368 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 369 370 return; 371 372 fail_rx: 373 dma_release_channel(dma->chan_rx); 374 fail_tx: 375 dma_release_channel(dma->chan_tx); 376 fail_al: 377 devm_kfree(dev, dma); 378 } 379 380 static void i2c_imx_dma_callback(void *arg) 381 { 382 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 383 struct imx_i2c_dma *dma = i2c_imx->dma; 384 385 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 386 dma->dma_len, dma->dma_data_dir); 387 complete(&dma->cmd_complete); 388 } 389 390 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 391 struct i2c_msg *msgs) 392 { 393 struct imx_i2c_dma *dma = i2c_imx->dma; 394 struct dma_async_tx_descriptor *txdesc; 395 struct device *dev = &i2c_imx->adapter.dev; 396 struct device *chan_dev = dma->chan_using->device->dev; 397 398 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 399 dma->dma_len, dma->dma_data_dir); 400 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 401 dev_err(dev, "DMA mapping failed\n"); 402 goto err_map; 403 } 404 405 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 406 dma->dma_len, dma->dma_transfer_dir, 407 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 408 if (!txdesc) { 409 dev_err(dev, "Not able to get desc for DMA xfer\n"); 410 goto err_desc; 411 } 412 413 reinit_completion(&dma->cmd_complete); 414 txdesc->callback = i2c_imx_dma_callback; 415 txdesc->callback_param = i2c_imx; 416 if (dma_submit_error(dmaengine_submit(txdesc))) { 417 dev_err(dev, "DMA submit failed\n"); 418 goto err_submit; 419 } 420 421 dma_async_issue_pending(dma->chan_using); 422 return 0; 423 424 err_submit: 425 dmaengine_terminate_all(dma->chan_using); 426 err_desc: 427 dma_unmap_single(chan_dev, dma->dma_buf, 428 dma->dma_len, dma->dma_data_dir); 429 err_map: 430 return -EINVAL; 431 } 432 433 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 434 { 435 struct imx_i2c_dma *dma = i2c_imx->dma; 436 437 dma->dma_buf = 0; 438 dma->dma_len = 0; 439 440 dma_release_channel(dma->chan_tx); 441 dma->chan_tx = NULL; 442 443 dma_release_channel(dma->chan_rx); 444 dma->chan_rx = NULL; 445 446 dma->chan_using = NULL; 447 } 448 449 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 450 { 451 unsigned long orig_jiffies = jiffies; 452 unsigned int temp; 453 454 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 455 456 while (1) { 457 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 458 459 /* check for arbitration lost */ 460 if (temp & I2SR_IAL) { 461 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 462 return -EAGAIN; 463 } 464 465 if (for_busy && (temp & I2SR_IBB)) { 466 i2c_imx->stopped = 0; 467 break; 468 } 469 if (!for_busy && !(temp & I2SR_IBB)) { 470 i2c_imx->stopped = 1; 471 break; 472 } 473 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 474 dev_dbg(&i2c_imx->adapter.dev, 475 "<%s> I2C bus is busy\n", __func__); 476 return -ETIMEDOUT; 477 } 478 if (atomic) 479 udelay(100); 480 else 481 schedule(); 482 } 483 484 return 0; 485 } 486 487 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 488 { 489 if (atomic) { 490 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 491 unsigned int regval; 492 493 /* 494 * The formula for the poll timeout is documented in the RM 495 * Rev.5 on page 1878: 496 * T_min = 10/F_scl 497 * Set the value hard as it is done for the non-atomic use-case. 498 * Use 10 kHz for the calculation since this is the minimum 499 * allowed SMBus frequency. Also add an offset of 100us since it 500 * turned out that the I2SR_IIF bit isn't set correctly within 501 * the minimum timeout in polling mode. 502 */ 503 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 504 i2c_imx->i2csr = regval; 505 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 506 } else { 507 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 508 } 509 510 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 511 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 512 return -ETIMEDOUT; 513 } 514 515 /* check for arbitration lost */ 516 if (i2c_imx->i2csr & I2SR_IAL) { 517 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 518 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 519 520 i2c_imx->i2csr = 0; 521 return -EAGAIN; 522 } 523 524 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 525 i2c_imx->i2csr = 0; 526 return 0; 527 } 528 529 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 530 { 531 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 532 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 533 return -ENXIO; /* No ACK */ 534 } 535 536 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 537 return 0; 538 } 539 540 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 541 unsigned int i2c_clk_rate) 542 { 543 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 544 unsigned int div; 545 int i; 546 547 /* Divider value calculation */ 548 if (i2c_imx->cur_clk == i2c_clk_rate) 549 return; 550 551 i2c_imx->cur_clk = i2c_clk_rate; 552 553 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 554 if (div < i2c_clk_div[0].div) 555 i = 0; 556 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 557 i = i2c_imx->hwdata->ndivs - 1; 558 else 559 for (i = 0; i2c_clk_div[i].div < div; i++) 560 ; 561 562 /* Store divider value */ 563 i2c_imx->ifdr = i2c_clk_div[i].val; 564 565 /* 566 * There dummy delay is calculated. 567 * It should be about one I2C clock period long. 568 * This delay is used in I2C bus disable function 569 * to fix chip hardware bug. 570 */ 571 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 572 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 573 574 #ifdef CONFIG_I2C_DEBUG_BUS 575 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 576 i2c_clk_rate, div); 577 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 578 i2c_clk_div[i].val, i2c_clk_div[i].div); 579 #endif 580 } 581 582 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 583 unsigned long action, void *data) 584 { 585 struct clk_notifier_data *ndata = data; 586 struct imx_i2c_struct *i2c_imx = container_of(nb, 587 struct imx_i2c_struct, 588 clk_change_nb); 589 590 if (action & POST_RATE_CHANGE) 591 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 592 593 return NOTIFY_OK; 594 } 595 596 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 597 { 598 unsigned int temp = 0; 599 int result; 600 601 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 602 603 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 604 /* Enable I2C controller */ 605 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 606 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 607 608 /* Wait controller to be stable */ 609 if (atomic) 610 udelay(50); 611 else 612 usleep_range(50, 150); 613 614 /* Start I2C transaction */ 615 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 616 temp |= I2CR_MSTA; 617 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 618 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 619 if (result) 620 return result; 621 622 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 623 if (atomic) 624 temp &= ~I2CR_IIEN; /* Disable interrupt */ 625 626 temp &= ~I2CR_DMAEN; 627 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 628 return result; 629 } 630 631 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 632 { 633 unsigned int temp = 0; 634 635 if (!i2c_imx->stopped) { 636 /* Stop I2C transaction */ 637 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 638 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 639 if (!(temp & I2CR_MSTA)) 640 i2c_imx->stopped = 1; 641 temp &= ~(I2CR_MSTA | I2CR_MTX); 642 if (i2c_imx->dma) 643 temp &= ~I2CR_DMAEN; 644 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 645 } 646 if (is_imx1_i2c(i2c_imx)) { 647 /* 648 * This delay caused by an i.MXL hardware bug. 649 * If no (or too short) delay, no "STOP" bit will be generated. 650 */ 651 udelay(i2c_imx->disable_delay); 652 } 653 654 if (!i2c_imx->stopped) 655 i2c_imx_bus_busy(i2c_imx, 0, atomic); 656 657 /* Disable I2C controller */ 658 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 659 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 660 } 661 662 /* 663 * Enable bus idle interrupts 664 * Note: IBIC register will be cleared after disabled i2c module. 665 * All of layerscape series SoCs support IBIC register. 666 */ 667 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 668 { 669 if (is_vf610_i2c(i2c_imx)) { 670 unsigned int temp; 671 672 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 673 temp |= IBIC_BIIE; 674 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 675 } 676 } 677 678 static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, 679 unsigned int status, unsigned int ctl) 680 { 681 u8 value; 682 683 if (status & I2SR_IAL) { /* Arbitration lost */ 684 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 685 if (!(status & I2SR_IAAS)) 686 return IRQ_HANDLED; 687 } 688 689 if (status & I2SR_IAAS) { /* Addressed as a slave */ 690 if (status & I2SR_SRW) { /* Master wants to read from us*/ 691 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 692 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value); 693 694 /* Slave transmit */ 695 ctl |= I2CR_MTX; 696 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 697 698 /* Send data */ 699 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 700 } else { /* Master wants to write to us */ 701 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 702 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 703 704 /* Slave receive */ 705 ctl &= ~I2CR_MTX; 706 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 707 /* Dummy read */ 708 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 709 } 710 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 711 if (status & I2SR_IBB) { /* No STOP signal detected */ 712 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 713 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 714 } else { /* STOP signal is detected */ 715 dev_dbg(&i2c_imx->adapter.dev, 716 "STOP signal detected"); 717 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value); 718 } 719 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 720 ctl |= I2CR_MTX; 721 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 722 723 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value); 724 725 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 726 } else { /* Transmit mode received NAK */ 727 ctl &= ~I2CR_MTX; 728 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 729 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 730 } 731 732 return IRQ_HANDLED; 733 } 734 735 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 736 { 737 int temp; 738 739 /* Set slave addr. */ 740 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 741 742 i2c_imx_reset_regs(i2c_imx); 743 744 /* Enable module */ 745 temp = i2c_imx->hwdata->i2cr_ien_opcode; 746 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 747 748 /* Enable interrupt from i2c module */ 749 temp |= I2CR_IIEN; 750 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 751 752 i2c_imx_enable_bus_idle(i2c_imx); 753 } 754 755 static int i2c_imx_reg_slave(struct i2c_client *client) 756 { 757 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 758 int ret; 759 760 if (i2c_imx->slave) 761 return -EBUSY; 762 763 i2c_imx->slave = client; 764 765 /* Resume */ 766 ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 767 if (ret < 0) { 768 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 769 return ret; 770 } 771 772 i2c_imx_slave_init(i2c_imx); 773 774 return 0; 775 } 776 777 static int i2c_imx_unreg_slave(struct i2c_client *client) 778 { 779 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 780 int ret; 781 782 if (!i2c_imx->slave) 783 return -EINVAL; 784 785 /* Reset slave address. */ 786 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 787 788 i2c_imx_reset_regs(i2c_imx); 789 790 i2c_imx->slave = NULL; 791 792 /* Suspend */ 793 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 794 if (ret < 0) 795 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 796 797 return ret; 798 } 799 800 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 801 { 802 /* save status register */ 803 i2c_imx->i2csr = status; 804 wake_up(&i2c_imx->queue); 805 806 return IRQ_HANDLED; 807 } 808 809 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 810 { 811 struct imx_i2c_struct *i2c_imx = dev_id; 812 unsigned int ctl, status; 813 814 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 815 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 816 if (status & I2SR_IIF) { 817 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 818 if (i2c_imx->slave && !(ctl & I2CR_MSTA)) 819 return i2c_imx_slave_isr(i2c_imx, status, ctl); 820 return i2c_imx_master_isr(i2c_imx, status); 821 } 822 823 return IRQ_NONE; 824 } 825 826 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 827 struct i2c_msg *msgs) 828 { 829 int result; 830 unsigned long time_left; 831 unsigned int temp = 0; 832 unsigned long orig_jiffies = jiffies; 833 struct imx_i2c_dma *dma = i2c_imx->dma; 834 struct device *dev = &i2c_imx->adapter.dev; 835 836 dma->chan_using = dma->chan_tx; 837 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 838 dma->dma_data_dir = DMA_TO_DEVICE; 839 dma->dma_len = msgs->len - 1; 840 result = i2c_imx_dma_xfer(i2c_imx, msgs); 841 if (result) 842 return result; 843 844 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 845 temp |= I2CR_DMAEN; 846 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 847 848 /* 849 * Write slave address. 850 * The first byte must be transmitted by the CPU. 851 */ 852 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 853 time_left = wait_for_completion_timeout( 854 &i2c_imx->dma->cmd_complete, 855 msecs_to_jiffies(DMA_TIMEOUT)); 856 if (time_left == 0) { 857 dmaengine_terminate_all(dma->chan_using); 858 return -ETIMEDOUT; 859 } 860 861 /* Waiting for transfer complete. */ 862 while (1) { 863 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 864 if (temp & I2SR_ICF) 865 break; 866 if (time_after(jiffies, orig_jiffies + 867 msecs_to_jiffies(DMA_TIMEOUT))) { 868 dev_dbg(dev, "<%s> Timeout\n", __func__); 869 return -ETIMEDOUT; 870 } 871 schedule(); 872 } 873 874 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 875 temp &= ~I2CR_DMAEN; 876 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 877 878 /* The last data byte must be transferred by the CPU. */ 879 imx_i2c_write_reg(msgs->buf[msgs->len-1], 880 i2c_imx, IMX_I2C_I2DR); 881 result = i2c_imx_trx_complete(i2c_imx, false); 882 if (result) 883 return result; 884 885 return i2c_imx_acked(i2c_imx); 886 } 887 888 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 889 struct i2c_msg *msgs, bool is_lastmsg) 890 { 891 int result; 892 unsigned long time_left; 893 unsigned int temp; 894 unsigned long orig_jiffies = jiffies; 895 struct imx_i2c_dma *dma = i2c_imx->dma; 896 struct device *dev = &i2c_imx->adapter.dev; 897 898 899 dma->chan_using = dma->chan_rx; 900 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 901 dma->dma_data_dir = DMA_FROM_DEVICE; 902 /* The last two data bytes must be transferred by the CPU. */ 903 dma->dma_len = msgs->len - 2; 904 result = i2c_imx_dma_xfer(i2c_imx, msgs); 905 if (result) 906 return result; 907 908 time_left = wait_for_completion_timeout( 909 &i2c_imx->dma->cmd_complete, 910 msecs_to_jiffies(DMA_TIMEOUT)); 911 if (time_left == 0) { 912 dmaengine_terminate_all(dma->chan_using); 913 return -ETIMEDOUT; 914 } 915 916 /* waiting for transfer complete. */ 917 while (1) { 918 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 919 if (temp & I2SR_ICF) 920 break; 921 if (time_after(jiffies, orig_jiffies + 922 msecs_to_jiffies(DMA_TIMEOUT))) { 923 dev_dbg(dev, "<%s> Timeout\n", __func__); 924 return -ETIMEDOUT; 925 } 926 schedule(); 927 } 928 929 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 930 temp &= ~I2CR_DMAEN; 931 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 932 933 /* read n-1 byte data */ 934 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 935 temp |= I2CR_TXAK; 936 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 937 938 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 939 /* read n byte data */ 940 result = i2c_imx_trx_complete(i2c_imx, false); 941 if (result) 942 return result; 943 944 if (is_lastmsg) { 945 /* 946 * It must generate STOP before read I2DR to prevent 947 * controller from generating another clock cycle 948 */ 949 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 950 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 951 if (!(temp & I2CR_MSTA)) 952 i2c_imx->stopped = 1; 953 temp &= ~(I2CR_MSTA | I2CR_MTX); 954 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 955 if (!i2c_imx->stopped) 956 i2c_imx_bus_busy(i2c_imx, 0, false); 957 } else { 958 /* 959 * For i2c master receiver repeat restart operation like: 960 * read -> repeat MSTA -> read/write 961 * The controller must set MTX before read the last byte in 962 * the first read operation, otherwise the first read cost 963 * one extra clock cycle. 964 */ 965 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 966 temp |= I2CR_MTX; 967 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 968 } 969 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 970 971 return 0; 972 } 973 974 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 975 bool atomic) 976 { 977 int i, result; 978 979 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 980 __func__, i2c_8bit_addr_from_msg(msgs)); 981 982 /* write slave address */ 983 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 984 result = i2c_imx_trx_complete(i2c_imx, atomic); 985 if (result) 986 return result; 987 result = i2c_imx_acked(i2c_imx); 988 if (result) 989 return result; 990 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 991 992 /* write data */ 993 for (i = 0; i < msgs->len; i++) { 994 dev_dbg(&i2c_imx->adapter.dev, 995 "<%s> write byte: B%d=0x%X\n", 996 __func__, i, msgs->buf[i]); 997 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 998 result = i2c_imx_trx_complete(i2c_imx, atomic); 999 if (result) 1000 return result; 1001 result = i2c_imx_acked(i2c_imx); 1002 if (result) 1003 return result; 1004 } 1005 return 0; 1006 } 1007 1008 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1009 bool is_lastmsg, bool atomic) 1010 { 1011 int i, result; 1012 unsigned int temp; 1013 int block_data = msgs->flags & I2C_M_RECV_LEN; 1014 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 1015 1016 dev_dbg(&i2c_imx->adapter.dev, 1017 "<%s> write slave address: addr=0x%x\n", 1018 __func__, i2c_8bit_addr_from_msg(msgs)); 1019 1020 /* write slave address */ 1021 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1022 result = i2c_imx_trx_complete(i2c_imx, atomic); 1023 if (result) 1024 return result; 1025 result = i2c_imx_acked(i2c_imx); 1026 if (result) 1027 return result; 1028 1029 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1030 1031 /* setup bus to read data */ 1032 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1033 temp &= ~I2CR_MTX; 1034 1035 /* 1036 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1037 * length is unknown 1038 */ 1039 if ((msgs->len - 1) || block_data) 1040 temp &= ~I2CR_TXAK; 1041 if (use_dma) 1042 temp |= I2CR_DMAEN; 1043 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1044 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1045 1046 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1047 1048 if (use_dma) 1049 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 1050 1051 /* read data */ 1052 for (i = 0; i < msgs->len; i++) { 1053 u8 len = 0; 1054 1055 result = i2c_imx_trx_complete(i2c_imx, atomic); 1056 if (result) 1057 return result; 1058 /* 1059 * First byte is the length of remaining packet 1060 * in the SMBus block data read. Add it to 1061 * msgs->len. 1062 */ 1063 if ((!i) && block_data) { 1064 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1065 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1066 return -EPROTO; 1067 dev_dbg(&i2c_imx->adapter.dev, 1068 "<%s> read length: 0x%X\n", 1069 __func__, len); 1070 msgs->len += len; 1071 } 1072 if (i == (msgs->len - 1)) { 1073 if (is_lastmsg) { 1074 /* 1075 * It must generate STOP before read I2DR to prevent 1076 * controller from generating another clock cycle 1077 */ 1078 dev_dbg(&i2c_imx->adapter.dev, 1079 "<%s> clear MSTA\n", __func__); 1080 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1081 if (!(temp & I2CR_MSTA)) 1082 i2c_imx->stopped = 1; 1083 temp &= ~(I2CR_MSTA | I2CR_MTX); 1084 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1085 if (!i2c_imx->stopped) 1086 i2c_imx_bus_busy(i2c_imx, 0, atomic); 1087 } else { 1088 /* 1089 * For i2c master receiver repeat restart operation like: 1090 * read -> repeat MSTA -> read/write 1091 * The controller must set MTX before read the last byte in 1092 * the first read operation, otherwise the first read cost 1093 * one extra clock cycle. 1094 */ 1095 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1096 temp |= I2CR_MTX; 1097 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1098 } 1099 } else if (i == (msgs->len - 2)) { 1100 dev_dbg(&i2c_imx->adapter.dev, 1101 "<%s> set TXAK\n", __func__); 1102 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1103 temp |= I2CR_TXAK; 1104 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1105 } 1106 if ((!i) && block_data) 1107 msgs->buf[0] = len; 1108 else 1109 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1110 dev_dbg(&i2c_imx->adapter.dev, 1111 "<%s> read byte: B%d=0x%X\n", 1112 __func__, i, msgs->buf[i]); 1113 } 1114 return 0; 1115 } 1116 1117 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1118 struct i2c_msg *msgs, int num, bool atomic) 1119 { 1120 unsigned int i, temp; 1121 int result; 1122 bool is_lastmsg = false; 1123 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1124 1125 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 1126 1127 /* Start I2C transfer */ 1128 result = i2c_imx_start(i2c_imx, atomic); 1129 if (result) { 1130 /* 1131 * Bus recovery uses gpiod_get_value_cansleep() which is not 1132 * allowed within atomic context. 1133 */ 1134 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1135 i2c_recover_bus(&i2c_imx->adapter); 1136 result = i2c_imx_start(i2c_imx, atomic); 1137 } 1138 } 1139 1140 if (result) 1141 goto fail0; 1142 1143 /* read/write data */ 1144 for (i = 0; i < num; i++) { 1145 if (i == num - 1) 1146 is_lastmsg = true; 1147 1148 if (i) { 1149 dev_dbg(&i2c_imx->adapter.dev, 1150 "<%s> repeated start\n", __func__); 1151 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1152 temp |= I2CR_RSTA; 1153 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1154 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1155 if (result) 1156 goto fail0; 1157 } 1158 dev_dbg(&i2c_imx->adapter.dev, 1159 "<%s> transfer message: %d\n", __func__, i); 1160 /* write/read data */ 1161 #ifdef CONFIG_I2C_DEBUG_BUS 1162 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1163 dev_dbg(&i2c_imx->adapter.dev, 1164 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1165 __func__, 1166 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1167 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1168 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1169 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1170 dev_dbg(&i2c_imx->adapter.dev, 1171 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1172 __func__, 1173 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1174 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1175 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1176 (temp & I2SR_RXAK ? 1 : 0)); 1177 #endif 1178 if (msgs[i].flags & I2C_M_RD) { 1179 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1180 } else { 1181 if (!atomic && 1182 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 1183 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1184 else 1185 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1186 } 1187 if (result) 1188 goto fail0; 1189 } 1190 1191 fail0: 1192 /* Stop I2C transfer */ 1193 i2c_imx_stop(i2c_imx, atomic); 1194 1195 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1196 (result < 0) ? "error" : "success msg", 1197 (result < 0) ? result : num); 1198 /* After data is transferred, switch to slave mode(as a receiver) */ 1199 if (i2c_imx->slave) 1200 i2c_imx_slave_init(i2c_imx); 1201 1202 return (result < 0) ? result : num; 1203 } 1204 1205 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1206 struct i2c_msg *msgs, int num) 1207 { 1208 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1209 int result; 1210 1211 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 1212 if (result < 0) 1213 return result; 1214 1215 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1216 1217 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1218 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1219 1220 return result; 1221 } 1222 1223 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1224 struct i2c_msg *msgs, int num) 1225 { 1226 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1227 int result; 1228 1229 result = clk_enable(i2c_imx->clk); 1230 if (result) 1231 return result; 1232 1233 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1234 1235 clk_disable(i2c_imx->clk); 1236 1237 return result; 1238 } 1239 1240 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1241 { 1242 struct imx_i2c_struct *i2c_imx; 1243 1244 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1245 1246 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1247 } 1248 1249 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1250 { 1251 struct imx_i2c_struct *i2c_imx; 1252 1253 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1254 1255 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1256 } 1257 1258 /* 1259 * We switch SCL and SDA to their GPIO function and do some bitbanging 1260 * for bus recovery. These alternative pinmux settings can be 1261 * described in the device tree by a separate pinctrl state "gpio". If 1262 * this is missing this is not a big problem, the only implication is 1263 * that we can't do bus recovery. 1264 */ 1265 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1266 struct platform_device *pdev) 1267 { 1268 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1269 1270 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1271 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1272 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1273 return PTR_ERR(i2c_imx->pinctrl); 1274 } 1275 1276 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1277 PINCTRL_STATE_DEFAULT); 1278 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1279 "gpio"); 1280 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1281 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1282 1283 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1284 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1285 return -EPROBE_DEFER; 1286 } else if (IS_ERR(rinfo->sda_gpiod) || 1287 IS_ERR(rinfo->scl_gpiod) || 1288 IS_ERR(i2c_imx->pinctrl_pins_default) || 1289 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1290 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1291 return 0; 1292 } 1293 1294 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1295 rinfo->sda_gpiod ? ",sda" : ""); 1296 1297 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1298 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1299 rinfo->recover_bus = i2c_generic_scl_recovery; 1300 i2c_imx->adapter.bus_recovery_info = rinfo; 1301 1302 return 0; 1303 } 1304 1305 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1306 { 1307 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1308 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1309 } 1310 1311 static const struct i2c_algorithm i2c_imx_algo = { 1312 .master_xfer = i2c_imx_xfer, 1313 .master_xfer_atomic = i2c_imx_xfer_atomic, 1314 .functionality = i2c_imx_func, 1315 .reg_slave = i2c_imx_reg_slave, 1316 .unreg_slave = i2c_imx_unreg_slave, 1317 }; 1318 1319 static int i2c_imx_probe(struct platform_device *pdev) 1320 { 1321 struct imx_i2c_struct *i2c_imx; 1322 struct resource *res; 1323 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1324 void __iomem *base; 1325 int irq, ret; 1326 dma_addr_t phy_addr; 1327 const struct imx_i2c_hwdata *match; 1328 1329 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1330 1331 irq = platform_get_irq(pdev, 0); 1332 if (irq < 0) 1333 return irq; 1334 1335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1336 base = devm_ioremap_resource(&pdev->dev, res); 1337 if (IS_ERR(base)) 1338 return PTR_ERR(base); 1339 1340 phy_addr = (dma_addr_t)res->start; 1341 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1342 if (!i2c_imx) 1343 return -ENOMEM; 1344 1345 match = device_get_match_data(&pdev->dev); 1346 if (match) 1347 i2c_imx->hwdata = match; 1348 else 1349 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1350 platform_get_device_id(pdev)->driver_data; 1351 1352 /* Setup i2c_imx driver structure */ 1353 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1354 i2c_imx->adapter.owner = THIS_MODULE; 1355 i2c_imx->adapter.algo = &i2c_imx_algo; 1356 i2c_imx->adapter.dev.parent = &pdev->dev; 1357 i2c_imx->adapter.nr = pdev->id; 1358 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1359 i2c_imx->base = base; 1360 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1361 1362 /* Get I2C clock */ 1363 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1364 if (IS_ERR(i2c_imx->clk)) 1365 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1366 "can't get I2C clock\n"); 1367 1368 ret = clk_prepare_enable(i2c_imx->clk); 1369 if (ret) { 1370 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1371 return ret; 1372 } 1373 1374 /* Init queue */ 1375 init_waitqueue_head(&i2c_imx->queue); 1376 1377 /* Set up adapter data */ 1378 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1379 1380 /* Set up platform driver data */ 1381 platform_set_drvdata(pdev, i2c_imx); 1382 1383 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1384 pm_runtime_use_autosuspend(&pdev->dev); 1385 pm_runtime_set_active(&pdev->dev); 1386 pm_runtime_enable(&pdev->dev); 1387 1388 ret = pm_runtime_get_sync(&pdev->dev); 1389 if (ret < 0) 1390 goto rpm_disable; 1391 1392 /* Request IRQ */ 1393 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1394 pdev->name, i2c_imx); 1395 if (ret) { 1396 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1397 goto rpm_disable; 1398 } 1399 1400 /* Set up clock divider */ 1401 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1402 ret = of_property_read_u32(pdev->dev.of_node, 1403 "clock-frequency", &i2c_imx->bitrate); 1404 if (ret < 0 && pdata && pdata->bitrate) 1405 i2c_imx->bitrate = pdata->bitrate; 1406 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1407 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1408 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1409 1410 i2c_imx_reset_regs(i2c_imx); 1411 1412 /* Init optional bus recovery function */ 1413 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1414 /* Give it another chance if pinctrl used is not ready yet */ 1415 if (ret == -EPROBE_DEFER) 1416 goto clk_notifier_unregister; 1417 1418 /* Add I2C adapter */ 1419 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1420 if (ret < 0) 1421 goto clk_notifier_unregister; 1422 1423 pm_runtime_mark_last_busy(&pdev->dev); 1424 pm_runtime_put_autosuspend(&pdev->dev); 1425 1426 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1427 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1428 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1429 i2c_imx->adapter.name); 1430 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1431 1432 /* Init DMA config if supported */ 1433 i2c_imx_dma_request(i2c_imx, phy_addr); 1434 1435 return 0; /* Return OK */ 1436 1437 clk_notifier_unregister: 1438 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1439 free_irq(irq, i2c_imx); 1440 rpm_disable: 1441 pm_runtime_put_noidle(&pdev->dev); 1442 pm_runtime_disable(&pdev->dev); 1443 pm_runtime_set_suspended(&pdev->dev); 1444 pm_runtime_dont_use_autosuspend(&pdev->dev); 1445 clk_disable_unprepare(i2c_imx->clk); 1446 return ret; 1447 } 1448 1449 static int i2c_imx_remove(struct platform_device *pdev) 1450 { 1451 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1452 int irq, ret; 1453 1454 ret = pm_runtime_get_sync(&pdev->dev); 1455 if (ret < 0) 1456 return ret; 1457 1458 /* remove adapter */ 1459 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1460 i2c_del_adapter(&i2c_imx->adapter); 1461 1462 if (i2c_imx->dma) 1463 i2c_imx_dma_free(i2c_imx); 1464 1465 /* setup chip registers to defaults */ 1466 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1467 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1468 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1469 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1470 1471 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1472 irq = platform_get_irq(pdev, 0); 1473 if (irq >= 0) 1474 free_irq(irq, i2c_imx); 1475 clk_disable_unprepare(i2c_imx->clk); 1476 1477 pm_runtime_put_noidle(&pdev->dev); 1478 pm_runtime_disable(&pdev->dev); 1479 1480 return 0; 1481 } 1482 1483 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1484 { 1485 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1486 1487 clk_disable(i2c_imx->clk); 1488 1489 return 0; 1490 } 1491 1492 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1493 { 1494 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1495 int ret; 1496 1497 ret = clk_enable(i2c_imx->clk); 1498 if (ret) 1499 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1500 1501 return ret; 1502 } 1503 1504 static const struct dev_pm_ops i2c_imx_pm_ops = { 1505 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1506 i2c_imx_runtime_resume, NULL) 1507 }; 1508 1509 static struct platform_driver i2c_imx_driver = { 1510 .probe = i2c_imx_probe, 1511 .remove = i2c_imx_remove, 1512 .driver = { 1513 .name = DRIVER_NAME, 1514 .pm = &i2c_imx_pm_ops, 1515 .of_match_table = i2c_imx_dt_ids, 1516 .acpi_match_table = i2c_imx_acpi_ids, 1517 }, 1518 .id_table = imx_i2c_devtype, 1519 }; 1520 1521 static int __init i2c_adap_imx_init(void) 1522 { 1523 return platform_driver_register(&i2c_imx_driver); 1524 } 1525 subsys_initcall(i2c_adap_imx_init); 1526 1527 static void __exit i2c_adap_imx_exit(void) 1528 { 1529 platform_driver_unregister(&i2c_imx_driver); 1530 } 1531 module_exit(i2c_adap_imx_exit); 1532 1533 MODULE_LICENSE("GPL"); 1534 MODULE_AUTHOR("Darius Augulis"); 1535 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1536 MODULE_ALIAS("platform:" DRIVER_NAME); 1537