1 /* 2 * Copyright (C) 2002 Motorola GSG-China 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * Author: 15 * Darius Augulis, Teltonika Inc. 16 * 17 * Desc.: 18 * Implementation of I2C Adapter/Algorithm Driver 19 * for I2C Bus integrated in Freescale i.MX/MXC processors 20 * 21 * Derived from Motorola GSG China I2C example driver 22 * 23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 25 * Copyright (C) 2007 RightHand Technologies, Inc. 26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 27 * 28 * Copyright 2013 Freescale Semiconductor, Inc. 29 * 30 */ 31 32 #include <linux/clk.h> 33 #include <linux/completion.h> 34 #include <linux/delay.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/dmaengine.h> 37 #include <linux/dmapool.h> 38 #include <linux/err.h> 39 #include <linux/errno.h> 40 #include <linux/gpio/consumer.h> 41 #include <linux/i2c.h> 42 #include <linux/init.h> 43 #include <linux/interrupt.h> 44 #include <linux/io.h> 45 #include <linux/kernel.h> 46 #include <linux/module.h> 47 #include <linux/of.h> 48 #include <linux/of_device.h> 49 #include <linux/of_dma.h> 50 #include <linux/pinctrl/consumer.h> 51 #include <linux/platform_data/i2c-imx.h> 52 #include <linux/platform_device.h> 53 #include <linux/pm_runtime.h> 54 #include <linux/sched.h> 55 #include <linux/slab.h> 56 57 /* This will be the driver name the kernel reports */ 58 #define DRIVER_NAME "imx-i2c" 59 60 /* Default value */ 61 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 62 63 /* 64 * Enable DMA if transfer byte size is bigger than this threshold. 65 * As the hardware request, it must bigger than 4 bytes.\ 66 * I have set '16' here, maybe it's not the best but I think it's 67 * the appropriate. 68 */ 69 #define DMA_THRESHOLD 16 70 #define DMA_TIMEOUT 1000 71 72 /* IMX I2C registers: 73 * the I2C register offset is different between SoCs, 74 * to provid support for all these chips, split the 75 * register offset into a fixed base address and a 76 * variable shift value, then the full register offset 77 * will be calculated by 78 * reg_off = ( reg_base_addr << reg_shift) 79 */ 80 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 81 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 82 #define IMX_I2C_I2CR 0x02 /* i2c control */ 83 #define IMX_I2C_I2SR 0x03 /* i2c status */ 84 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 85 86 #define IMX_I2C_REGSHIFT 2 87 #define VF610_I2C_REGSHIFT 0 88 89 /* Bits of IMX I2C registers */ 90 #define I2SR_RXAK 0x01 91 #define I2SR_IIF 0x02 92 #define I2SR_SRW 0x04 93 #define I2SR_IAL 0x10 94 #define I2SR_IBB 0x20 95 #define I2SR_IAAS 0x40 96 #define I2SR_ICF 0x80 97 #define I2CR_DMAEN 0x02 98 #define I2CR_RSTA 0x04 99 #define I2CR_TXAK 0x08 100 #define I2CR_MTX 0x10 101 #define I2CR_MSTA 0x20 102 #define I2CR_IIEN 0x40 103 #define I2CR_IEN 0x80 104 105 /* register bits different operating codes definition: 106 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 107 * - write zero to clear(w0c) INT flag on i.MX, 108 * - but write one to clear(w1c) INT flag on Vybrid. 109 * 2) I2CR: I2C module enable operation also differ between SoCs: 110 * - set I2CR_IEN bit enable the module on i.MX, 111 * - but clear I2CR_IEN bit enable the module on Vybrid. 112 */ 113 #define I2SR_CLR_OPCODE_W0C 0x0 114 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 115 #define I2CR_IEN_OPCODE_0 0x0 116 #define I2CR_IEN_OPCODE_1 I2CR_IEN 117 118 #define I2C_PM_TIMEOUT 10 /* ms */ 119 120 /* 121 * sorted list of clock divider, register value pairs 122 * taken from table 26-5, p.26-9, Freescale i.MX 123 * Integrated Portable System Processor Reference Manual 124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 125 * 126 * Duplicated divider values removed from list 127 */ 128 struct imx_i2c_clk_pair { 129 u16 div; 130 u16 val; 131 }; 132 133 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 146 { 3072, 0x1E }, { 3840, 0x1F } 147 }; 148 149 /* Vybrid VF610 clock divider, register value pairs */ 150 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 166 }; 167 168 enum imx_i2c_type { 169 IMX1_I2C, 170 IMX21_I2C, 171 VF610_I2C, 172 }; 173 174 struct imx_i2c_hwdata { 175 enum imx_i2c_type devtype; 176 unsigned regshift; 177 struct imx_i2c_clk_pair *clk_div; 178 unsigned ndivs; 179 unsigned i2sr_clr_opcode; 180 unsigned i2cr_ien_opcode; 181 }; 182 183 struct imx_i2c_dma { 184 struct dma_chan *chan_tx; 185 struct dma_chan *chan_rx; 186 struct dma_chan *chan_using; 187 struct completion cmd_complete; 188 dma_addr_t dma_buf; 189 unsigned int dma_len; 190 enum dma_transfer_direction dma_transfer_dir; 191 enum dma_data_direction dma_data_dir; 192 }; 193 194 struct imx_i2c_struct { 195 struct i2c_adapter adapter; 196 struct clk *clk; 197 struct notifier_block clk_change_nb; 198 void __iomem *base; 199 wait_queue_head_t queue; 200 unsigned long i2csr; 201 unsigned int disable_delay; 202 int stopped; 203 unsigned int ifdr; /* IMX_I2C_IFDR */ 204 unsigned int cur_clk; 205 unsigned int bitrate; 206 const struct imx_i2c_hwdata *hwdata; 207 struct i2c_bus_recovery_info rinfo; 208 209 struct pinctrl *pinctrl; 210 struct pinctrl_state *pinctrl_pins_default; 211 struct pinctrl_state *pinctrl_pins_gpio; 212 213 struct imx_i2c_dma *dma; 214 }; 215 216 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 217 .devtype = IMX1_I2C, 218 .regshift = IMX_I2C_REGSHIFT, 219 .clk_div = imx_i2c_clk_div, 220 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 221 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 222 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 223 224 }; 225 226 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 227 .devtype = IMX21_I2C, 228 .regshift = IMX_I2C_REGSHIFT, 229 .clk_div = imx_i2c_clk_div, 230 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 231 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 232 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 233 234 }; 235 236 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 237 .devtype = VF610_I2C, 238 .regshift = VF610_I2C_REGSHIFT, 239 .clk_div = vf610_i2c_clk_div, 240 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 241 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 242 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 243 244 }; 245 246 static const struct platform_device_id imx_i2c_devtype[] = { 247 { 248 .name = "imx1-i2c", 249 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 250 }, { 251 .name = "imx21-i2c", 252 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 253 }, { 254 /* sentinel */ 255 } 256 }; 257 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 258 259 static const struct of_device_id i2c_imx_dt_ids[] = { 260 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 261 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 262 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 263 { /* sentinel */ } 264 }; 265 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 266 267 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 268 { 269 return i2c_imx->hwdata->devtype == IMX1_I2C; 270 } 271 272 static inline void imx_i2c_write_reg(unsigned int val, 273 struct imx_i2c_struct *i2c_imx, unsigned int reg) 274 { 275 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 276 } 277 278 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 279 unsigned int reg) 280 { 281 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 282 } 283 284 /* Functions for DMA support */ 285 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 286 dma_addr_t phy_addr) 287 { 288 struct imx_i2c_dma *dma; 289 struct dma_slave_config dma_sconfig; 290 struct device *dev = &i2c_imx->adapter.dev; 291 int ret; 292 293 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 294 if (!dma) 295 return; 296 297 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 298 if (!dma->chan_tx) { 299 dev_dbg(dev, "can't request DMA tx channel\n"); 300 goto fail_al; 301 } 302 303 dma_sconfig.dst_addr = phy_addr + 304 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 305 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 306 dma_sconfig.dst_maxburst = 1; 307 dma_sconfig.direction = DMA_MEM_TO_DEV; 308 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 309 if (ret < 0) { 310 dev_dbg(dev, "can't configure tx channel\n"); 311 goto fail_tx; 312 } 313 314 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 315 if (!dma->chan_rx) { 316 dev_dbg(dev, "can't request DMA rx channel\n"); 317 goto fail_tx; 318 } 319 320 dma_sconfig.src_addr = phy_addr + 321 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 322 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 323 dma_sconfig.src_maxburst = 1; 324 dma_sconfig.direction = DMA_DEV_TO_MEM; 325 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 326 if (ret < 0) { 327 dev_dbg(dev, "can't configure rx channel\n"); 328 goto fail_rx; 329 } 330 331 i2c_imx->dma = dma; 332 init_completion(&dma->cmd_complete); 333 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 334 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 335 336 return; 337 338 fail_rx: 339 dma_release_channel(dma->chan_rx); 340 fail_tx: 341 dma_release_channel(dma->chan_tx); 342 fail_al: 343 devm_kfree(dev, dma); 344 dev_info(dev, "can't use DMA, using PIO instead.\n"); 345 } 346 347 static void i2c_imx_dma_callback(void *arg) 348 { 349 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 350 struct imx_i2c_dma *dma = i2c_imx->dma; 351 352 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 353 dma->dma_len, dma->dma_data_dir); 354 complete(&dma->cmd_complete); 355 } 356 357 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 358 struct i2c_msg *msgs) 359 { 360 struct imx_i2c_dma *dma = i2c_imx->dma; 361 struct dma_async_tx_descriptor *txdesc; 362 struct device *dev = &i2c_imx->adapter.dev; 363 struct device *chan_dev = dma->chan_using->device->dev; 364 365 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 366 dma->dma_len, dma->dma_data_dir); 367 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 368 dev_err(dev, "DMA mapping failed\n"); 369 goto err_map; 370 } 371 372 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 373 dma->dma_len, dma->dma_transfer_dir, 374 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 375 if (!txdesc) { 376 dev_err(dev, "Not able to get desc for DMA xfer\n"); 377 goto err_desc; 378 } 379 380 txdesc->callback = i2c_imx_dma_callback; 381 txdesc->callback_param = i2c_imx; 382 if (dma_submit_error(dmaengine_submit(txdesc))) { 383 dev_err(dev, "DMA submit failed\n"); 384 goto err_submit; 385 } 386 387 dma_async_issue_pending(dma->chan_using); 388 return 0; 389 390 err_submit: 391 dmaengine_terminate_all(dma->chan_using); 392 err_desc: 393 dma_unmap_single(chan_dev, dma->dma_buf, 394 dma->dma_len, dma->dma_data_dir); 395 err_map: 396 return -EINVAL; 397 } 398 399 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 400 { 401 struct imx_i2c_dma *dma = i2c_imx->dma; 402 403 dma->dma_buf = 0; 404 dma->dma_len = 0; 405 406 dma_release_channel(dma->chan_tx); 407 dma->chan_tx = NULL; 408 409 dma_release_channel(dma->chan_rx); 410 dma->chan_rx = NULL; 411 412 dma->chan_using = NULL; 413 } 414 415 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 416 { 417 unsigned long orig_jiffies = jiffies; 418 unsigned int temp; 419 420 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 421 422 while (1) { 423 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 424 425 /* check for arbitration lost */ 426 if (temp & I2SR_IAL) { 427 temp &= ~I2SR_IAL; 428 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 429 return -EAGAIN; 430 } 431 432 if (for_busy && (temp & I2SR_IBB)) 433 break; 434 if (!for_busy && !(temp & I2SR_IBB)) 435 break; 436 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 437 dev_dbg(&i2c_imx->adapter.dev, 438 "<%s> I2C bus is busy\n", __func__); 439 return -ETIMEDOUT; 440 } 441 schedule(); 442 } 443 444 return 0; 445 } 446 447 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 448 { 449 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 450 451 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 452 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 453 return -ETIMEDOUT; 454 } 455 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 456 i2c_imx->i2csr = 0; 457 return 0; 458 } 459 460 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 461 { 462 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 463 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 464 return -ENXIO; /* No ACK */ 465 } 466 467 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 468 return 0; 469 } 470 471 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 472 unsigned int i2c_clk_rate) 473 { 474 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 475 unsigned int div; 476 int i; 477 478 /* Divider value calculation */ 479 if (i2c_imx->cur_clk == i2c_clk_rate) 480 return; 481 482 i2c_imx->cur_clk = i2c_clk_rate; 483 484 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 485 if (div < i2c_clk_div[0].div) 486 i = 0; 487 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 488 i = i2c_imx->hwdata->ndivs - 1; 489 else 490 for (i = 0; i2c_clk_div[i].div < div; i++) 491 ; 492 493 /* Store divider value */ 494 i2c_imx->ifdr = i2c_clk_div[i].val; 495 496 /* 497 * There dummy delay is calculated. 498 * It should be about one I2C clock period long. 499 * This delay is used in I2C bus disable function 500 * to fix chip hardware bug. 501 */ 502 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 503 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 504 505 #ifdef CONFIG_I2C_DEBUG_BUS 506 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 507 i2c_clk_rate, div); 508 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 509 i2c_clk_div[i].val, i2c_clk_div[i].div); 510 #endif 511 } 512 513 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 514 unsigned long action, void *data) 515 { 516 struct clk_notifier_data *ndata = data; 517 struct imx_i2c_struct *i2c_imx = container_of(&ndata->clk, 518 struct imx_i2c_struct, 519 clk); 520 521 if (action & POST_RATE_CHANGE) 522 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 523 524 return NOTIFY_OK; 525 } 526 527 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 528 { 529 unsigned int temp = 0; 530 int result; 531 532 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 533 534 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 535 /* Enable I2C controller */ 536 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 537 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 538 539 /* Wait controller to be stable */ 540 usleep_range(50, 150); 541 542 /* Start I2C transaction */ 543 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 544 temp |= I2CR_MSTA; 545 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 546 result = i2c_imx_bus_busy(i2c_imx, 1); 547 if (result) 548 return result; 549 i2c_imx->stopped = 0; 550 551 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 552 temp &= ~I2CR_DMAEN; 553 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 554 return result; 555 } 556 557 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 558 { 559 unsigned int temp = 0; 560 561 if (!i2c_imx->stopped) { 562 /* Stop I2C transaction */ 563 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 564 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 565 temp &= ~(I2CR_MSTA | I2CR_MTX); 566 if (i2c_imx->dma) 567 temp &= ~I2CR_DMAEN; 568 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 569 } 570 if (is_imx1_i2c(i2c_imx)) { 571 /* 572 * This delay caused by an i.MXL hardware bug. 573 * If no (or too short) delay, no "STOP" bit will be generated. 574 */ 575 udelay(i2c_imx->disable_delay); 576 } 577 578 if (!i2c_imx->stopped) { 579 i2c_imx_bus_busy(i2c_imx, 0); 580 i2c_imx->stopped = 1; 581 } 582 583 /* Disable I2C controller */ 584 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 585 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 586 } 587 588 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 589 { 590 struct imx_i2c_struct *i2c_imx = dev_id; 591 unsigned int temp; 592 593 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 594 if (temp & I2SR_IIF) { 595 /* save status register */ 596 i2c_imx->i2csr = temp; 597 temp &= ~I2SR_IIF; 598 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 599 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 600 wake_up(&i2c_imx->queue); 601 return IRQ_HANDLED; 602 } 603 604 return IRQ_NONE; 605 } 606 607 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 608 struct i2c_msg *msgs) 609 { 610 int result; 611 unsigned long time_left; 612 unsigned int temp = 0; 613 unsigned long orig_jiffies = jiffies; 614 struct imx_i2c_dma *dma = i2c_imx->dma; 615 struct device *dev = &i2c_imx->adapter.dev; 616 617 dma->chan_using = dma->chan_tx; 618 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 619 dma->dma_data_dir = DMA_TO_DEVICE; 620 dma->dma_len = msgs->len - 1; 621 result = i2c_imx_dma_xfer(i2c_imx, msgs); 622 if (result) 623 return result; 624 625 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 626 temp |= I2CR_DMAEN; 627 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 628 629 /* 630 * Write slave address. 631 * The first byte must be transmitted by the CPU. 632 */ 633 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 634 reinit_completion(&i2c_imx->dma->cmd_complete); 635 time_left = wait_for_completion_timeout( 636 &i2c_imx->dma->cmd_complete, 637 msecs_to_jiffies(DMA_TIMEOUT)); 638 if (time_left == 0) { 639 dmaengine_terminate_all(dma->chan_using); 640 return -ETIMEDOUT; 641 } 642 643 /* Waiting for transfer complete. */ 644 while (1) { 645 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 646 if (temp & I2SR_ICF) 647 break; 648 if (time_after(jiffies, orig_jiffies + 649 msecs_to_jiffies(DMA_TIMEOUT))) { 650 dev_dbg(dev, "<%s> Timeout\n", __func__); 651 return -ETIMEDOUT; 652 } 653 schedule(); 654 } 655 656 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 657 temp &= ~I2CR_DMAEN; 658 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 659 660 /* The last data byte must be transferred by the CPU. */ 661 imx_i2c_write_reg(msgs->buf[msgs->len-1], 662 i2c_imx, IMX_I2C_I2DR); 663 result = i2c_imx_trx_complete(i2c_imx); 664 if (result) 665 return result; 666 667 return i2c_imx_acked(i2c_imx); 668 } 669 670 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 671 struct i2c_msg *msgs, bool is_lastmsg) 672 { 673 int result; 674 unsigned long time_left; 675 unsigned int temp; 676 unsigned long orig_jiffies = jiffies; 677 struct imx_i2c_dma *dma = i2c_imx->dma; 678 struct device *dev = &i2c_imx->adapter.dev; 679 680 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 681 temp |= I2CR_DMAEN; 682 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 683 684 dma->chan_using = dma->chan_rx; 685 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 686 dma->dma_data_dir = DMA_FROM_DEVICE; 687 /* The last two data bytes must be transferred by the CPU. */ 688 dma->dma_len = msgs->len - 2; 689 result = i2c_imx_dma_xfer(i2c_imx, msgs); 690 if (result) 691 return result; 692 693 reinit_completion(&i2c_imx->dma->cmd_complete); 694 time_left = wait_for_completion_timeout( 695 &i2c_imx->dma->cmd_complete, 696 msecs_to_jiffies(DMA_TIMEOUT)); 697 if (time_left == 0) { 698 dmaengine_terminate_all(dma->chan_using); 699 return -ETIMEDOUT; 700 } 701 702 /* waiting for transfer complete. */ 703 while (1) { 704 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 705 if (temp & I2SR_ICF) 706 break; 707 if (time_after(jiffies, orig_jiffies + 708 msecs_to_jiffies(DMA_TIMEOUT))) { 709 dev_dbg(dev, "<%s> Timeout\n", __func__); 710 return -ETIMEDOUT; 711 } 712 schedule(); 713 } 714 715 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 716 temp &= ~I2CR_DMAEN; 717 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 718 719 /* read n-1 byte data */ 720 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 721 temp |= I2CR_TXAK; 722 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 723 724 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 725 /* read n byte data */ 726 result = i2c_imx_trx_complete(i2c_imx); 727 if (result) 728 return result; 729 730 if (is_lastmsg) { 731 /* 732 * It must generate STOP before read I2DR to prevent 733 * controller from generating another clock cycle 734 */ 735 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 736 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 737 temp &= ~(I2CR_MSTA | I2CR_MTX); 738 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 739 i2c_imx_bus_busy(i2c_imx, 0); 740 i2c_imx->stopped = 1; 741 } else { 742 /* 743 * For i2c master receiver repeat restart operation like: 744 * read -> repeat MSTA -> read/write 745 * The controller must set MTX before read the last byte in 746 * the first read operation, otherwise the first read cost 747 * one extra clock cycle. 748 */ 749 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 750 temp |= I2CR_MTX; 751 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 752 } 753 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 754 755 return 0; 756 } 757 758 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 759 { 760 int i, result; 761 762 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 763 __func__, msgs->addr << 1); 764 765 /* write slave address */ 766 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 767 result = i2c_imx_trx_complete(i2c_imx); 768 if (result) 769 return result; 770 result = i2c_imx_acked(i2c_imx); 771 if (result) 772 return result; 773 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 774 775 /* write data */ 776 for (i = 0; i < msgs->len; i++) { 777 dev_dbg(&i2c_imx->adapter.dev, 778 "<%s> write byte: B%d=0x%X\n", 779 __func__, i, msgs->buf[i]); 780 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 781 result = i2c_imx_trx_complete(i2c_imx); 782 if (result) 783 return result; 784 result = i2c_imx_acked(i2c_imx); 785 if (result) 786 return result; 787 } 788 return 0; 789 } 790 791 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 792 { 793 int i, result; 794 unsigned int temp; 795 int block_data = msgs->flags & I2C_M_RECV_LEN; 796 797 dev_dbg(&i2c_imx->adapter.dev, 798 "<%s> write slave address: addr=0x%x\n", 799 __func__, (msgs->addr << 1) | 0x01); 800 801 /* write slave address */ 802 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); 803 result = i2c_imx_trx_complete(i2c_imx); 804 if (result) 805 return result; 806 result = i2c_imx_acked(i2c_imx); 807 if (result) 808 return result; 809 810 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 811 812 /* setup bus to read data */ 813 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 814 temp &= ~I2CR_MTX; 815 816 /* 817 * Reset the I2CR_TXAK flag initially for SMBus block read since the 818 * length is unknown 819 */ 820 if ((msgs->len - 1) || block_data) 821 temp &= ~I2CR_TXAK; 822 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 823 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 824 825 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 826 827 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data) 828 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 829 830 /* read data */ 831 for (i = 0; i < msgs->len; i++) { 832 u8 len = 0; 833 834 result = i2c_imx_trx_complete(i2c_imx); 835 if (result) 836 return result; 837 /* 838 * First byte is the length of remaining packet 839 * in the SMBus block data read. Add it to 840 * msgs->len. 841 */ 842 if ((!i) && block_data) { 843 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 844 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 845 return -EPROTO; 846 dev_dbg(&i2c_imx->adapter.dev, 847 "<%s> read length: 0x%X\n", 848 __func__, len); 849 msgs->len += len; 850 } 851 if (i == (msgs->len - 1)) { 852 if (is_lastmsg) { 853 /* 854 * It must generate STOP before read I2DR to prevent 855 * controller from generating another clock cycle 856 */ 857 dev_dbg(&i2c_imx->adapter.dev, 858 "<%s> clear MSTA\n", __func__); 859 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 860 temp &= ~(I2CR_MSTA | I2CR_MTX); 861 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 862 i2c_imx_bus_busy(i2c_imx, 0); 863 i2c_imx->stopped = 1; 864 } else { 865 /* 866 * For i2c master receiver repeat restart operation like: 867 * read -> repeat MSTA -> read/write 868 * The controller must set MTX before read the last byte in 869 * the first read operation, otherwise the first read cost 870 * one extra clock cycle. 871 */ 872 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 873 temp |= I2CR_MTX; 874 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 875 } 876 } else if (i == (msgs->len - 2)) { 877 dev_dbg(&i2c_imx->adapter.dev, 878 "<%s> set TXAK\n", __func__); 879 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 880 temp |= I2CR_TXAK; 881 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 882 } 883 if ((!i) && block_data) 884 msgs->buf[0] = len; 885 else 886 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 887 dev_dbg(&i2c_imx->adapter.dev, 888 "<%s> read byte: B%d=0x%X\n", 889 __func__, i, msgs->buf[i]); 890 } 891 return 0; 892 } 893 894 static int i2c_imx_xfer(struct i2c_adapter *adapter, 895 struct i2c_msg *msgs, int num) 896 { 897 unsigned int i, temp; 898 int result; 899 bool is_lastmsg = false; 900 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 901 902 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 903 904 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 905 if (result < 0) 906 goto out; 907 908 /* Start I2C transfer */ 909 result = i2c_imx_start(i2c_imx); 910 if (result) { 911 if (i2c_imx->adapter.bus_recovery_info) { 912 i2c_recover_bus(&i2c_imx->adapter); 913 result = i2c_imx_start(i2c_imx); 914 } 915 } 916 917 if (result) 918 goto fail0; 919 920 /* read/write data */ 921 for (i = 0; i < num; i++) { 922 if (i == num - 1) 923 is_lastmsg = true; 924 925 if (i) { 926 dev_dbg(&i2c_imx->adapter.dev, 927 "<%s> repeated start\n", __func__); 928 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 929 temp |= I2CR_RSTA; 930 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 931 result = i2c_imx_bus_busy(i2c_imx, 1); 932 if (result) 933 goto fail0; 934 } 935 dev_dbg(&i2c_imx->adapter.dev, 936 "<%s> transfer message: %d\n", __func__, i); 937 /* write/read data */ 938 #ifdef CONFIG_I2C_DEBUG_BUS 939 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 940 dev_dbg(&i2c_imx->adapter.dev, 941 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 942 __func__, 943 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 944 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 945 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 946 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 947 dev_dbg(&i2c_imx->adapter.dev, 948 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 949 __func__, 950 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 951 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 952 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 953 (temp & I2SR_RXAK ? 1 : 0)); 954 #endif 955 if (msgs[i].flags & I2C_M_RD) 956 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 957 else { 958 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 959 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 960 else 961 result = i2c_imx_write(i2c_imx, &msgs[i]); 962 } 963 if (result) 964 goto fail0; 965 } 966 967 fail0: 968 /* Stop I2C transfer */ 969 i2c_imx_stop(i2c_imx); 970 971 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 972 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 973 974 out: 975 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 976 (result < 0) ? "error" : "success msg", 977 (result < 0) ? result : num); 978 return (result < 0) ? result : num; 979 } 980 981 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 982 { 983 struct imx_i2c_struct *i2c_imx; 984 985 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 986 987 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 988 } 989 990 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 991 { 992 struct imx_i2c_struct *i2c_imx; 993 994 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 995 996 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 997 } 998 999 /* 1000 * We switch SCL and SDA to their GPIO function and do some bitbanging 1001 * for bus recovery. These alternative pinmux settings can be 1002 * described in the device tree by a separate pinctrl state "gpio". If 1003 * this is missing this is not a big problem, the only implication is 1004 * that we can't do bus recovery. 1005 */ 1006 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1007 struct platform_device *pdev) 1008 { 1009 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1010 1011 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1012 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1013 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1014 return PTR_ERR(i2c_imx->pinctrl); 1015 } 1016 1017 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1018 PINCTRL_STATE_DEFAULT); 1019 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1020 "gpio"); 1021 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1022 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH); 1023 1024 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1025 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1026 return -EPROBE_DEFER; 1027 } else if (IS_ERR(rinfo->sda_gpiod) || 1028 IS_ERR(rinfo->scl_gpiod) || 1029 IS_ERR(i2c_imx->pinctrl_pins_default) || 1030 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1031 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1032 return 0; 1033 } 1034 1035 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1036 rinfo->sda_gpiod ? ",sda" : ""); 1037 1038 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1039 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1040 rinfo->recover_bus = i2c_generic_scl_recovery; 1041 i2c_imx->adapter.bus_recovery_info = rinfo; 1042 1043 return 0; 1044 } 1045 1046 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1047 { 1048 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1049 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1050 } 1051 1052 static const struct i2c_algorithm i2c_imx_algo = { 1053 .master_xfer = i2c_imx_xfer, 1054 .functionality = i2c_imx_func, 1055 }; 1056 1057 static int i2c_imx_probe(struct platform_device *pdev) 1058 { 1059 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 1060 &pdev->dev); 1061 struct imx_i2c_struct *i2c_imx; 1062 struct resource *res; 1063 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1064 void __iomem *base; 1065 int irq, ret; 1066 dma_addr_t phy_addr; 1067 1068 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1069 1070 irq = platform_get_irq(pdev, 0); 1071 if (irq < 0) { 1072 dev_err(&pdev->dev, "can't get irq number\n"); 1073 return irq; 1074 } 1075 1076 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1077 base = devm_ioremap_resource(&pdev->dev, res); 1078 if (IS_ERR(base)) 1079 return PTR_ERR(base); 1080 1081 phy_addr = (dma_addr_t)res->start; 1082 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1083 if (!i2c_imx) 1084 return -ENOMEM; 1085 1086 if (of_id) 1087 i2c_imx->hwdata = of_id->data; 1088 else 1089 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1090 platform_get_device_id(pdev)->driver_data; 1091 1092 /* Setup i2c_imx driver structure */ 1093 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1094 i2c_imx->adapter.owner = THIS_MODULE; 1095 i2c_imx->adapter.algo = &i2c_imx_algo; 1096 i2c_imx->adapter.dev.parent = &pdev->dev; 1097 i2c_imx->adapter.nr = pdev->id; 1098 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1099 i2c_imx->base = base; 1100 1101 /* Get I2C clock */ 1102 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1103 if (IS_ERR(i2c_imx->clk)) { 1104 dev_err(&pdev->dev, "can't get I2C clock\n"); 1105 return PTR_ERR(i2c_imx->clk); 1106 } 1107 1108 ret = clk_prepare_enable(i2c_imx->clk); 1109 if (ret) { 1110 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1111 return ret; 1112 } 1113 1114 /* Request IRQ */ 1115 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED, 1116 pdev->name, i2c_imx); 1117 if (ret) { 1118 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1119 goto clk_disable; 1120 } 1121 1122 /* Init queue */ 1123 init_waitqueue_head(&i2c_imx->queue); 1124 1125 /* Set up adapter data */ 1126 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1127 1128 /* Set up platform driver data */ 1129 platform_set_drvdata(pdev, i2c_imx); 1130 1131 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1132 pm_runtime_use_autosuspend(&pdev->dev); 1133 pm_runtime_set_active(&pdev->dev); 1134 pm_runtime_enable(&pdev->dev); 1135 1136 ret = pm_runtime_get_sync(&pdev->dev); 1137 if (ret < 0) 1138 goto rpm_disable; 1139 1140 /* Set up clock divider */ 1141 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 1142 ret = of_property_read_u32(pdev->dev.of_node, 1143 "clock-frequency", &i2c_imx->bitrate); 1144 if (ret < 0 && pdata && pdata->bitrate) 1145 i2c_imx->bitrate = pdata->bitrate; 1146 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1147 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1148 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1149 1150 /* Set up chip registers to defaults */ 1151 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1152 i2c_imx, IMX_I2C_I2CR); 1153 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1154 1155 /* Init optional bus recovery function */ 1156 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1157 /* Give it another chance if pinctrl used is not ready yet */ 1158 if (ret == -EPROBE_DEFER) 1159 goto clk_notifier_unregister; 1160 1161 /* Add I2C adapter */ 1162 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1163 if (ret < 0) 1164 goto clk_notifier_unregister; 1165 1166 pm_runtime_mark_last_busy(&pdev->dev); 1167 pm_runtime_put_autosuspend(&pdev->dev); 1168 1169 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1170 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1171 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1172 i2c_imx->adapter.name); 1173 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1174 1175 /* Init DMA config if supported */ 1176 i2c_imx_dma_request(i2c_imx, phy_addr); 1177 1178 return 0; /* Return OK */ 1179 1180 clk_notifier_unregister: 1181 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1182 rpm_disable: 1183 pm_runtime_put_noidle(&pdev->dev); 1184 pm_runtime_disable(&pdev->dev); 1185 pm_runtime_set_suspended(&pdev->dev); 1186 pm_runtime_dont_use_autosuspend(&pdev->dev); 1187 1188 clk_disable: 1189 clk_disable_unprepare(i2c_imx->clk); 1190 return ret; 1191 } 1192 1193 static int i2c_imx_remove(struct platform_device *pdev) 1194 { 1195 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1196 int ret; 1197 1198 ret = pm_runtime_get_sync(&pdev->dev); 1199 if (ret < 0) 1200 return ret; 1201 1202 /* remove adapter */ 1203 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1204 i2c_del_adapter(&i2c_imx->adapter); 1205 1206 if (i2c_imx->dma) 1207 i2c_imx_dma_free(i2c_imx); 1208 1209 /* setup chip registers to defaults */ 1210 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1211 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1212 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1213 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1214 1215 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1216 clk_disable_unprepare(i2c_imx->clk); 1217 1218 pm_runtime_put_noidle(&pdev->dev); 1219 pm_runtime_disable(&pdev->dev); 1220 1221 return 0; 1222 } 1223 1224 #ifdef CONFIG_PM 1225 static int i2c_imx_runtime_suspend(struct device *dev) 1226 { 1227 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1228 1229 clk_disable(i2c_imx->clk); 1230 1231 return 0; 1232 } 1233 1234 static int i2c_imx_runtime_resume(struct device *dev) 1235 { 1236 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1237 int ret; 1238 1239 ret = clk_enable(i2c_imx->clk); 1240 if (ret) 1241 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1242 1243 return ret; 1244 } 1245 1246 static const struct dev_pm_ops i2c_imx_pm_ops = { 1247 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1248 i2c_imx_runtime_resume, NULL) 1249 }; 1250 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops) 1251 #else 1252 #define I2C_IMX_PM_OPS NULL 1253 #endif /* CONFIG_PM */ 1254 1255 static struct platform_driver i2c_imx_driver = { 1256 .probe = i2c_imx_probe, 1257 .remove = i2c_imx_remove, 1258 .driver = { 1259 .name = DRIVER_NAME, 1260 .pm = I2C_IMX_PM_OPS, 1261 .of_match_table = i2c_imx_dt_ids, 1262 }, 1263 .id_table = imx_i2c_devtype, 1264 }; 1265 1266 static int __init i2c_adap_imx_init(void) 1267 { 1268 return platform_driver_register(&i2c_imx_driver); 1269 } 1270 subsys_initcall(i2c_adap_imx_init); 1271 1272 static void __exit i2c_adap_imx_exit(void) 1273 { 1274 platform_driver_unregister(&i2c_imx_driver); 1275 } 1276 module_exit(i2c_adap_imx_exit); 1277 1278 MODULE_LICENSE("GPL"); 1279 MODULE_AUTHOR("Darius Augulis"); 1280 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1281 MODULE_ALIAS("platform:" DRIVER_NAME); 1282