1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/of_dma.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/platform_data/i2c-imx.h> 46 #include <linux/platform_device.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/sched.h> 49 #include <linux/slab.h> 50 51 /* This will be the driver name the kernel reports */ 52 #define DRIVER_NAME "imx-i2c" 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 /* 78 * All of the layerscape series SoCs support IBIC register. 79 */ 80 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 81 82 #define IMX_I2C_REGSHIFT 2 83 #define VF610_I2C_REGSHIFT 0 84 85 /* Bits of IMX I2C registers */ 86 #define I2SR_RXAK 0x01 87 #define I2SR_IIF 0x02 88 #define I2SR_SRW 0x04 89 #define I2SR_IAL 0x10 90 #define I2SR_IBB 0x20 91 #define I2SR_IAAS 0x40 92 #define I2SR_ICF 0x80 93 #define I2CR_DMAEN 0x02 94 #define I2CR_RSTA 0x04 95 #define I2CR_TXAK 0x08 96 #define I2CR_MTX 0x10 97 #define I2CR_MSTA 0x20 98 #define I2CR_IIEN 0x40 99 #define I2CR_IEN 0x80 100 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 101 102 /* register bits different operating codes definition: 103 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 104 * - write zero to clear(w0c) INT flag on i.MX, 105 * - but write one to clear(w1c) INT flag on Vybrid. 106 * 2) I2CR: I2C module enable operation also differ between SoCs: 107 * - set I2CR_IEN bit enable the module on i.MX, 108 * - but clear I2CR_IEN bit enable the module on Vybrid. 109 */ 110 #define I2SR_CLR_OPCODE_W0C 0x0 111 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 112 #define I2CR_IEN_OPCODE_0 0x0 113 #define I2CR_IEN_OPCODE_1 I2CR_IEN 114 115 #define I2C_PM_TIMEOUT 10 /* ms */ 116 117 /* 118 * sorted list of clock divider, register value pairs 119 * taken from table 26-5, p.26-9, Freescale i.MX 120 * Integrated Portable System Processor Reference Manual 121 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 122 * 123 * Duplicated divider values removed from list 124 */ 125 struct imx_i2c_clk_pair { 126 u16 div; 127 u16 val; 128 }; 129 130 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 131 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 132 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 133 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 134 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 135 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 136 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 137 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 138 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 139 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 140 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 141 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 142 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 143 { 3072, 0x1E }, { 3840, 0x1F } 144 }; 145 146 /* Vybrid VF610 clock divider, register value pairs */ 147 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 148 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 149 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 150 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 151 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 152 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 153 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 154 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 155 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 156 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 157 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 158 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 159 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 160 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 161 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 162 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 163 }; 164 165 enum imx_i2c_type { 166 IMX1_I2C, 167 IMX21_I2C, 168 VF610_I2C, 169 }; 170 171 struct imx_i2c_hwdata { 172 enum imx_i2c_type devtype; 173 unsigned regshift; 174 struct imx_i2c_clk_pair *clk_div; 175 unsigned ndivs; 176 unsigned i2sr_clr_opcode; 177 unsigned i2cr_ien_opcode; 178 }; 179 180 struct imx_i2c_dma { 181 struct dma_chan *chan_tx; 182 struct dma_chan *chan_rx; 183 struct dma_chan *chan_using; 184 struct completion cmd_complete; 185 dma_addr_t dma_buf; 186 unsigned int dma_len; 187 enum dma_transfer_direction dma_transfer_dir; 188 enum dma_data_direction dma_data_dir; 189 }; 190 191 struct imx_i2c_struct { 192 struct i2c_adapter adapter; 193 struct clk *clk; 194 struct notifier_block clk_change_nb; 195 void __iomem *base; 196 wait_queue_head_t queue; 197 unsigned long i2csr; 198 unsigned int disable_delay; 199 int stopped; 200 unsigned int ifdr; /* IMX_I2C_IFDR */ 201 unsigned int cur_clk; 202 unsigned int bitrate; 203 const struct imx_i2c_hwdata *hwdata; 204 struct i2c_bus_recovery_info rinfo; 205 206 struct pinctrl *pinctrl; 207 struct pinctrl_state *pinctrl_pins_default; 208 struct pinctrl_state *pinctrl_pins_gpio; 209 210 struct imx_i2c_dma *dma; 211 struct i2c_client *slave; 212 }; 213 214 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 215 .devtype = IMX1_I2C, 216 .regshift = IMX_I2C_REGSHIFT, 217 .clk_div = imx_i2c_clk_div, 218 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 219 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 220 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 221 222 }; 223 224 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 225 .devtype = IMX21_I2C, 226 .regshift = IMX_I2C_REGSHIFT, 227 .clk_div = imx_i2c_clk_div, 228 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 229 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 230 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 231 232 }; 233 234 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 235 .devtype = VF610_I2C, 236 .regshift = VF610_I2C_REGSHIFT, 237 .clk_div = vf610_i2c_clk_div, 238 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 239 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 240 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 241 242 }; 243 244 static const struct of_device_id i2c_imx_dt_ids[] = { 245 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 246 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 247 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 248 { /* sentinel */ } 249 }; 250 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 251 252 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 253 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 254 { } 255 }; 256 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 257 258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 259 { 260 return i2c_imx->hwdata->devtype == IMX1_I2C; 261 } 262 263 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 264 { 265 return i2c_imx->hwdata->devtype == VF610_I2C; 266 } 267 268 static inline void imx_i2c_write_reg(unsigned int val, 269 struct imx_i2c_struct *i2c_imx, unsigned int reg) 270 { 271 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 272 } 273 274 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 275 unsigned int reg) 276 { 277 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 278 } 279 280 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 281 { 282 unsigned int temp; 283 284 /* 285 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 286 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 287 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 288 */ 289 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 290 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 291 } 292 293 /* Set up i2c controller register and i2c status register to default value. */ 294 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 295 { 296 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 297 i2c_imx, IMX_I2C_I2CR); 298 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 299 } 300 301 /* Functions for DMA support */ 302 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 303 dma_addr_t phy_addr) 304 { 305 struct imx_i2c_dma *dma; 306 struct dma_slave_config dma_sconfig; 307 struct device *dev = &i2c_imx->adapter.dev; 308 int ret; 309 310 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 311 if (!dma) 312 return; 313 314 dma->chan_tx = dma_request_chan(dev, "tx"); 315 if (IS_ERR(dma->chan_tx)) { 316 ret = PTR_ERR(dma->chan_tx); 317 if (ret != -ENODEV && ret != -EPROBE_DEFER) 318 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 319 goto fail_al; 320 } 321 322 dma_sconfig.dst_addr = phy_addr + 323 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 324 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 325 dma_sconfig.dst_maxburst = 1; 326 dma_sconfig.direction = DMA_MEM_TO_DEV; 327 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 328 if (ret < 0) { 329 dev_err(dev, "can't configure tx channel (%d)\n", ret); 330 goto fail_tx; 331 } 332 333 dma->chan_rx = dma_request_chan(dev, "rx"); 334 if (IS_ERR(dma->chan_rx)) { 335 ret = PTR_ERR(dma->chan_rx); 336 if (ret != -ENODEV && ret != -EPROBE_DEFER) 337 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 338 goto fail_tx; 339 } 340 341 dma_sconfig.src_addr = phy_addr + 342 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 343 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 344 dma_sconfig.src_maxburst = 1; 345 dma_sconfig.direction = DMA_DEV_TO_MEM; 346 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 347 if (ret < 0) { 348 dev_err(dev, "can't configure rx channel (%d)\n", ret); 349 goto fail_rx; 350 } 351 352 i2c_imx->dma = dma; 353 init_completion(&dma->cmd_complete); 354 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 355 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 356 357 return; 358 359 fail_rx: 360 dma_release_channel(dma->chan_rx); 361 fail_tx: 362 dma_release_channel(dma->chan_tx); 363 fail_al: 364 devm_kfree(dev, dma); 365 } 366 367 static void i2c_imx_dma_callback(void *arg) 368 { 369 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 370 struct imx_i2c_dma *dma = i2c_imx->dma; 371 372 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 373 dma->dma_len, dma->dma_data_dir); 374 complete(&dma->cmd_complete); 375 } 376 377 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 378 struct i2c_msg *msgs) 379 { 380 struct imx_i2c_dma *dma = i2c_imx->dma; 381 struct dma_async_tx_descriptor *txdesc; 382 struct device *dev = &i2c_imx->adapter.dev; 383 struct device *chan_dev = dma->chan_using->device->dev; 384 385 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 386 dma->dma_len, dma->dma_data_dir); 387 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 388 dev_err(dev, "DMA mapping failed\n"); 389 goto err_map; 390 } 391 392 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 393 dma->dma_len, dma->dma_transfer_dir, 394 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 395 if (!txdesc) { 396 dev_err(dev, "Not able to get desc for DMA xfer\n"); 397 goto err_desc; 398 } 399 400 reinit_completion(&dma->cmd_complete); 401 txdesc->callback = i2c_imx_dma_callback; 402 txdesc->callback_param = i2c_imx; 403 if (dma_submit_error(dmaengine_submit(txdesc))) { 404 dev_err(dev, "DMA submit failed\n"); 405 goto err_submit; 406 } 407 408 dma_async_issue_pending(dma->chan_using); 409 return 0; 410 411 err_submit: 412 dmaengine_terminate_all(dma->chan_using); 413 err_desc: 414 dma_unmap_single(chan_dev, dma->dma_buf, 415 dma->dma_len, dma->dma_data_dir); 416 err_map: 417 return -EINVAL; 418 } 419 420 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 421 { 422 struct imx_i2c_dma *dma = i2c_imx->dma; 423 424 dma->dma_buf = 0; 425 dma->dma_len = 0; 426 427 dma_release_channel(dma->chan_tx); 428 dma->chan_tx = NULL; 429 430 dma_release_channel(dma->chan_rx); 431 dma->chan_rx = NULL; 432 433 dma->chan_using = NULL; 434 } 435 436 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 437 { 438 unsigned long orig_jiffies = jiffies; 439 unsigned int temp; 440 441 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 442 443 while (1) { 444 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 445 446 /* check for arbitration lost */ 447 if (temp & I2SR_IAL) { 448 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 449 return -EAGAIN; 450 } 451 452 if (for_busy && (temp & I2SR_IBB)) { 453 i2c_imx->stopped = 0; 454 break; 455 } 456 if (!for_busy && !(temp & I2SR_IBB)) { 457 i2c_imx->stopped = 1; 458 break; 459 } 460 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 461 dev_dbg(&i2c_imx->adapter.dev, 462 "<%s> I2C bus is busy\n", __func__); 463 return -ETIMEDOUT; 464 } 465 if (atomic) 466 udelay(100); 467 else 468 schedule(); 469 } 470 471 return 0; 472 } 473 474 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 475 { 476 if (atomic) { 477 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 478 unsigned int regval; 479 480 /* 481 * The formula for the poll timeout is documented in the RM 482 * Rev.5 on page 1878: 483 * T_min = 10/F_scl 484 * Set the value hard as it is done for the non-atomic use-case. 485 * Use 10 kHz for the calculation since this is the minimum 486 * allowed SMBus frequency. Also add an offset of 100us since it 487 * turned out that the I2SR_IIF bit isn't set correctly within 488 * the minimum timeout in polling mode. 489 */ 490 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 491 i2c_imx->i2csr = regval; 492 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 493 } else { 494 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 495 } 496 497 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 498 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 499 return -ETIMEDOUT; 500 } 501 502 /* check for arbitration lost */ 503 if (i2c_imx->i2csr & I2SR_IAL) { 504 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 505 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 506 507 i2c_imx->i2csr = 0; 508 return -EAGAIN; 509 } 510 511 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 512 i2c_imx->i2csr = 0; 513 return 0; 514 } 515 516 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 517 { 518 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 519 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 520 return -ENXIO; /* No ACK */ 521 } 522 523 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 524 return 0; 525 } 526 527 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 528 unsigned int i2c_clk_rate) 529 { 530 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 531 unsigned int div; 532 int i; 533 534 /* Divider value calculation */ 535 if (i2c_imx->cur_clk == i2c_clk_rate) 536 return; 537 538 i2c_imx->cur_clk = i2c_clk_rate; 539 540 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 541 if (div < i2c_clk_div[0].div) 542 i = 0; 543 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 544 i = i2c_imx->hwdata->ndivs - 1; 545 else 546 for (i = 0; i2c_clk_div[i].div < div; i++) 547 ; 548 549 /* Store divider value */ 550 i2c_imx->ifdr = i2c_clk_div[i].val; 551 552 /* 553 * There dummy delay is calculated. 554 * It should be about one I2C clock period long. 555 * This delay is used in I2C bus disable function 556 * to fix chip hardware bug. 557 */ 558 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 559 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 560 561 #ifdef CONFIG_I2C_DEBUG_BUS 562 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 563 i2c_clk_rate, div); 564 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 565 i2c_clk_div[i].val, i2c_clk_div[i].div); 566 #endif 567 } 568 569 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 570 unsigned long action, void *data) 571 { 572 struct clk_notifier_data *ndata = data; 573 struct imx_i2c_struct *i2c_imx = container_of(nb, 574 struct imx_i2c_struct, 575 clk_change_nb); 576 577 if (action & POST_RATE_CHANGE) 578 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 579 580 return NOTIFY_OK; 581 } 582 583 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 584 { 585 unsigned int temp = 0; 586 int result; 587 588 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 589 590 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 591 /* Enable I2C controller */ 592 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 593 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 594 595 /* Wait controller to be stable */ 596 if (atomic) 597 udelay(50); 598 else 599 usleep_range(50, 150); 600 601 /* Start I2C transaction */ 602 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 603 temp |= I2CR_MSTA; 604 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 605 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 606 if (result) 607 return result; 608 609 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 610 if (atomic) 611 temp &= ~I2CR_IIEN; /* Disable interrupt */ 612 613 temp &= ~I2CR_DMAEN; 614 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 615 return result; 616 } 617 618 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 619 { 620 unsigned int temp = 0; 621 622 if (!i2c_imx->stopped) { 623 /* Stop I2C transaction */ 624 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 625 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 626 if (!(temp & I2CR_MSTA)) 627 i2c_imx->stopped = 1; 628 temp &= ~(I2CR_MSTA | I2CR_MTX); 629 if (i2c_imx->dma) 630 temp &= ~I2CR_DMAEN; 631 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 632 } 633 if (is_imx1_i2c(i2c_imx)) { 634 /* 635 * This delay caused by an i.MXL hardware bug. 636 * If no (or too short) delay, no "STOP" bit will be generated. 637 */ 638 udelay(i2c_imx->disable_delay); 639 } 640 641 if (!i2c_imx->stopped) 642 i2c_imx_bus_busy(i2c_imx, 0, atomic); 643 644 /* Disable I2C controller */ 645 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 646 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 647 } 648 649 /* 650 * Enable bus idle interrupts 651 * Note: IBIC register will be cleared after disabled i2c module. 652 * All of layerscape series SoCs support IBIC register. 653 */ 654 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 655 { 656 if (is_vf610_i2c(i2c_imx)) { 657 unsigned int temp; 658 659 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 660 temp |= IBIC_BIIE; 661 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 662 } 663 } 664 665 static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, 666 unsigned int status, unsigned int ctl) 667 { 668 u8 value; 669 670 if (status & I2SR_IAL) { /* Arbitration lost */ 671 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 672 if (!(status & I2SR_IAAS)) 673 return IRQ_HANDLED; 674 } 675 676 if (status & I2SR_IAAS) { /* Addressed as a slave */ 677 if (status & I2SR_SRW) { /* Master wants to read from us*/ 678 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 679 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value); 680 681 /* Slave transmit */ 682 ctl |= I2CR_MTX; 683 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 684 685 /* Send data */ 686 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 687 } else { /* Master wants to write to us */ 688 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 689 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 690 691 /* Slave receive */ 692 ctl &= ~I2CR_MTX; 693 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 694 /* Dummy read */ 695 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 696 } 697 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 698 if (status & I2SR_IBB) { /* No STOP signal detected */ 699 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 700 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 701 } else { /* STOP signal is detected */ 702 dev_dbg(&i2c_imx->adapter.dev, 703 "STOP signal detected"); 704 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value); 705 } 706 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 707 ctl |= I2CR_MTX; 708 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 709 710 i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value); 711 712 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 713 } else { /* Transmit mode received NAK */ 714 ctl &= ~I2CR_MTX; 715 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 716 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 717 } 718 719 return IRQ_HANDLED; 720 } 721 722 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 723 { 724 int temp; 725 726 /* Set slave addr. */ 727 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 728 729 i2c_imx_reset_regs(i2c_imx); 730 731 /* Enable module */ 732 temp = i2c_imx->hwdata->i2cr_ien_opcode; 733 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 734 735 /* Enable interrupt from i2c module */ 736 temp |= I2CR_IIEN; 737 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 738 739 i2c_imx_enable_bus_idle(i2c_imx); 740 } 741 742 static int i2c_imx_reg_slave(struct i2c_client *client) 743 { 744 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 745 int ret; 746 747 if (i2c_imx->slave) 748 return -EBUSY; 749 750 i2c_imx->slave = client; 751 752 /* Resume */ 753 ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 754 if (ret < 0) { 755 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 756 return ret; 757 } 758 759 i2c_imx_slave_init(i2c_imx); 760 761 return 0; 762 } 763 764 static int i2c_imx_unreg_slave(struct i2c_client *client) 765 { 766 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 767 int ret; 768 769 if (!i2c_imx->slave) 770 return -EINVAL; 771 772 /* Reset slave address. */ 773 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 774 775 i2c_imx_reset_regs(i2c_imx); 776 777 i2c_imx->slave = NULL; 778 779 /* Suspend */ 780 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 781 if (ret < 0) 782 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 783 784 return ret; 785 } 786 787 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 788 { 789 /* save status register */ 790 i2c_imx->i2csr = status; 791 wake_up(&i2c_imx->queue); 792 793 return IRQ_HANDLED; 794 } 795 796 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 797 { 798 struct imx_i2c_struct *i2c_imx = dev_id; 799 unsigned int ctl, status; 800 801 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 802 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 803 if (status & I2SR_IIF) { 804 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 805 if (i2c_imx->slave && !(ctl & I2CR_MSTA)) 806 return i2c_imx_slave_isr(i2c_imx, status, ctl); 807 return i2c_imx_master_isr(i2c_imx, status); 808 } 809 810 return IRQ_NONE; 811 } 812 813 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 814 struct i2c_msg *msgs) 815 { 816 int result; 817 unsigned long time_left; 818 unsigned int temp = 0; 819 unsigned long orig_jiffies = jiffies; 820 struct imx_i2c_dma *dma = i2c_imx->dma; 821 struct device *dev = &i2c_imx->adapter.dev; 822 823 dma->chan_using = dma->chan_tx; 824 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 825 dma->dma_data_dir = DMA_TO_DEVICE; 826 dma->dma_len = msgs->len - 1; 827 result = i2c_imx_dma_xfer(i2c_imx, msgs); 828 if (result) 829 return result; 830 831 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 832 temp |= I2CR_DMAEN; 833 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 834 835 /* 836 * Write slave address. 837 * The first byte must be transmitted by the CPU. 838 */ 839 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 840 time_left = wait_for_completion_timeout( 841 &i2c_imx->dma->cmd_complete, 842 msecs_to_jiffies(DMA_TIMEOUT)); 843 if (time_left == 0) { 844 dmaengine_terminate_all(dma->chan_using); 845 return -ETIMEDOUT; 846 } 847 848 /* Waiting for transfer complete. */ 849 while (1) { 850 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 851 if (temp & I2SR_ICF) 852 break; 853 if (time_after(jiffies, orig_jiffies + 854 msecs_to_jiffies(DMA_TIMEOUT))) { 855 dev_dbg(dev, "<%s> Timeout\n", __func__); 856 return -ETIMEDOUT; 857 } 858 schedule(); 859 } 860 861 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 862 temp &= ~I2CR_DMAEN; 863 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 864 865 /* The last data byte must be transferred by the CPU. */ 866 imx_i2c_write_reg(msgs->buf[msgs->len-1], 867 i2c_imx, IMX_I2C_I2DR); 868 result = i2c_imx_trx_complete(i2c_imx, false); 869 if (result) 870 return result; 871 872 return i2c_imx_acked(i2c_imx); 873 } 874 875 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 876 struct i2c_msg *msgs, bool is_lastmsg) 877 { 878 int result; 879 unsigned long time_left; 880 unsigned int temp; 881 unsigned long orig_jiffies = jiffies; 882 struct imx_i2c_dma *dma = i2c_imx->dma; 883 struct device *dev = &i2c_imx->adapter.dev; 884 885 886 dma->chan_using = dma->chan_rx; 887 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 888 dma->dma_data_dir = DMA_FROM_DEVICE; 889 /* The last two data bytes must be transferred by the CPU. */ 890 dma->dma_len = msgs->len - 2; 891 result = i2c_imx_dma_xfer(i2c_imx, msgs); 892 if (result) 893 return result; 894 895 time_left = wait_for_completion_timeout( 896 &i2c_imx->dma->cmd_complete, 897 msecs_to_jiffies(DMA_TIMEOUT)); 898 if (time_left == 0) { 899 dmaengine_terminate_all(dma->chan_using); 900 return -ETIMEDOUT; 901 } 902 903 /* waiting for transfer complete. */ 904 while (1) { 905 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 906 if (temp & I2SR_ICF) 907 break; 908 if (time_after(jiffies, orig_jiffies + 909 msecs_to_jiffies(DMA_TIMEOUT))) { 910 dev_dbg(dev, "<%s> Timeout\n", __func__); 911 return -ETIMEDOUT; 912 } 913 schedule(); 914 } 915 916 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 917 temp &= ~I2CR_DMAEN; 918 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 919 920 /* read n-1 byte data */ 921 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 922 temp |= I2CR_TXAK; 923 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 924 925 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 926 /* read n byte data */ 927 result = i2c_imx_trx_complete(i2c_imx, false); 928 if (result) 929 return result; 930 931 if (is_lastmsg) { 932 /* 933 * It must generate STOP before read I2DR to prevent 934 * controller from generating another clock cycle 935 */ 936 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 937 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 938 if (!(temp & I2CR_MSTA)) 939 i2c_imx->stopped = 1; 940 temp &= ~(I2CR_MSTA | I2CR_MTX); 941 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 942 if (!i2c_imx->stopped) 943 i2c_imx_bus_busy(i2c_imx, 0, false); 944 } else { 945 /* 946 * For i2c master receiver repeat restart operation like: 947 * read -> repeat MSTA -> read/write 948 * The controller must set MTX before read the last byte in 949 * the first read operation, otherwise the first read cost 950 * one extra clock cycle. 951 */ 952 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 953 temp |= I2CR_MTX; 954 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 955 } 956 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 957 958 return 0; 959 } 960 961 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 962 bool atomic) 963 { 964 int i, result; 965 966 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 967 __func__, i2c_8bit_addr_from_msg(msgs)); 968 969 /* write slave address */ 970 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 971 result = i2c_imx_trx_complete(i2c_imx, atomic); 972 if (result) 973 return result; 974 result = i2c_imx_acked(i2c_imx); 975 if (result) 976 return result; 977 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 978 979 /* write data */ 980 for (i = 0; i < msgs->len; i++) { 981 dev_dbg(&i2c_imx->adapter.dev, 982 "<%s> write byte: B%d=0x%X\n", 983 __func__, i, msgs->buf[i]); 984 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 985 result = i2c_imx_trx_complete(i2c_imx, atomic); 986 if (result) 987 return result; 988 result = i2c_imx_acked(i2c_imx); 989 if (result) 990 return result; 991 } 992 return 0; 993 } 994 995 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 996 bool is_lastmsg, bool atomic) 997 { 998 int i, result; 999 unsigned int temp; 1000 int block_data = msgs->flags & I2C_M_RECV_LEN; 1001 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 1002 1003 dev_dbg(&i2c_imx->adapter.dev, 1004 "<%s> write slave address: addr=0x%x\n", 1005 __func__, i2c_8bit_addr_from_msg(msgs)); 1006 1007 /* write slave address */ 1008 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1009 result = i2c_imx_trx_complete(i2c_imx, atomic); 1010 if (result) 1011 return result; 1012 result = i2c_imx_acked(i2c_imx); 1013 if (result) 1014 return result; 1015 1016 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1017 1018 /* setup bus to read data */ 1019 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1020 temp &= ~I2CR_MTX; 1021 1022 /* 1023 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1024 * length is unknown 1025 */ 1026 if ((msgs->len - 1) || block_data) 1027 temp &= ~I2CR_TXAK; 1028 if (use_dma) 1029 temp |= I2CR_DMAEN; 1030 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1031 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1032 1033 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1034 1035 if (use_dma) 1036 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 1037 1038 /* read data */ 1039 for (i = 0; i < msgs->len; i++) { 1040 u8 len = 0; 1041 1042 result = i2c_imx_trx_complete(i2c_imx, atomic); 1043 if (result) 1044 return result; 1045 /* 1046 * First byte is the length of remaining packet 1047 * in the SMBus block data read. Add it to 1048 * msgs->len. 1049 */ 1050 if ((!i) && block_data) { 1051 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1052 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1053 return -EPROTO; 1054 dev_dbg(&i2c_imx->adapter.dev, 1055 "<%s> read length: 0x%X\n", 1056 __func__, len); 1057 msgs->len += len; 1058 } 1059 if (i == (msgs->len - 1)) { 1060 if (is_lastmsg) { 1061 /* 1062 * It must generate STOP before read I2DR to prevent 1063 * controller from generating another clock cycle 1064 */ 1065 dev_dbg(&i2c_imx->adapter.dev, 1066 "<%s> clear MSTA\n", __func__); 1067 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1068 if (!(temp & I2CR_MSTA)) 1069 i2c_imx->stopped = 1; 1070 temp &= ~(I2CR_MSTA | I2CR_MTX); 1071 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1072 if (!i2c_imx->stopped) 1073 i2c_imx_bus_busy(i2c_imx, 0, atomic); 1074 } else { 1075 /* 1076 * For i2c master receiver repeat restart operation like: 1077 * read -> repeat MSTA -> read/write 1078 * The controller must set MTX before read the last byte in 1079 * the first read operation, otherwise the first read cost 1080 * one extra clock cycle. 1081 */ 1082 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1083 temp |= I2CR_MTX; 1084 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1085 } 1086 } else if (i == (msgs->len - 2)) { 1087 dev_dbg(&i2c_imx->adapter.dev, 1088 "<%s> set TXAK\n", __func__); 1089 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1090 temp |= I2CR_TXAK; 1091 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1092 } 1093 if ((!i) && block_data) 1094 msgs->buf[0] = len; 1095 else 1096 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1097 dev_dbg(&i2c_imx->adapter.dev, 1098 "<%s> read byte: B%d=0x%X\n", 1099 __func__, i, msgs->buf[i]); 1100 } 1101 return 0; 1102 } 1103 1104 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1105 struct i2c_msg *msgs, int num, bool atomic) 1106 { 1107 unsigned int i, temp; 1108 int result; 1109 bool is_lastmsg = false; 1110 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1111 1112 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 1113 1114 /* Start I2C transfer */ 1115 result = i2c_imx_start(i2c_imx, atomic); 1116 if (result) { 1117 /* 1118 * Bus recovery uses gpiod_get_value_cansleep() which is not 1119 * allowed within atomic context. 1120 */ 1121 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1122 i2c_recover_bus(&i2c_imx->adapter); 1123 result = i2c_imx_start(i2c_imx, atomic); 1124 } 1125 } 1126 1127 if (result) 1128 goto fail0; 1129 1130 /* read/write data */ 1131 for (i = 0; i < num; i++) { 1132 if (i == num - 1) 1133 is_lastmsg = true; 1134 1135 if (i) { 1136 dev_dbg(&i2c_imx->adapter.dev, 1137 "<%s> repeated start\n", __func__); 1138 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1139 temp |= I2CR_RSTA; 1140 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1141 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1142 if (result) 1143 goto fail0; 1144 } 1145 dev_dbg(&i2c_imx->adapter.dev, 1146 "<%s> transfer message: %d\n", __func__, i); 1147 /* write/read data */ 1148 #ifdef CONFIG_I2C_DEBUG_BUS 1149 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1150 dev_dbg(&i2c_imx->adapter.dev, 1151 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1152 __func__, 1153 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1154 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1155 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1156 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1157 dev_dbg(&i2c_imx->adapter.dev, 1158 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1159 __func__, 1160 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1161 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1162 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1163 (temp & I2SR_RXAK ? 1 : 0)); 1164 #endif 1165 if (msgs[i].flags & I2C_M_RD) { 1166 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1167 } else { 1168 if (!atomic && 1169 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 1170 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1171 else 1172 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1173 } 1174 if (result) 1175 goto fail0; 1176 } 1177 1178 fail0: 1179 /* Stop I2C transfer */ 1180 i2c_imx_stop(i2c_imx, atomic); 1181 1182 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1183 (result < 0) ? "error" : "success msg", 1184 (result < 0) ? result : num); 1185 /* After data is transferred, switch to slave mode(as a receiver) */ 1186 if (i2c_imx->slave) 1187 i2c_imx_slave_init(i2c_imx); 1188 1189 return (result < 0) ? result : num; 1190 } 1191 1192 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1193 struct i2c_msg *msgs, int num) 1194 { 1195 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1196 int result; 1197 1198 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 1199 if (result < 0) 1200 return result; 1201 1202 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1203 1204 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1205 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1206 1207 return result; 1208 } 1209 1210 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1211 struct i2c_msg *msgs, int num) 1212 { 1213 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1214 int result; 1215 1216 result = clk_enable(i2c_imx->clk); 1217 if (result) 1218 return result; 1219 1220 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1221 1222 clk_disable(i2c_imx->clk); 1223 1224 return result; 1225 } 1226 1227 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1228 { 1229 struct imx_i2c_struct *i2c_imx; 1230 1231 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1232 1233 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1234 } 1235 1236 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1237 { 1238 struct imx_i2c_struct *i2c_imx; 1239 1240 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1241 1242 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1243 } 1244 1245 /* 1246 * We switch SCL and SDA to their GPIO function and do some bitbanging 1247 * for bus recovery. These alternative pinmux settings can be 1248 * described in the device tree by a separate pinctrl state "gpio". If 1249 * this is missing this is not a big problem, the only implication is 1250 * that we can't do bus recovery. 1251 */ 1252 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1253 struct platform_device *pdev) 1254 { 1255 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1256 1257 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1258 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1259 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1260 return PTR_ERR(i2c_imx->pinctrl); 1261 } 1262 1263 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1264 PINCTRL_STATE_DEFAULT); 1265 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1266 "gpio"); 1267 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1268 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1269 1270 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1271 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1272 return -EPROBE_DEFER; 1273 } else if (IS_ERR(rinfo->sda_gpiod) || 1274 IS_ERR(rinfo->scl_gpiod) || 1275 IS_ERR(i2c_imx->pinctrl_pins_default) || 1276 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1277 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1278 return 0; 1279 } 1280 1281 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1282 rinfo->sda_gpiod ? ",sda" : ""); 1283 1284 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1285 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1286 rinfo->recover_bus = i2c_generic_scl_recovery; 1287 i2c_imx->adapter.bus_recovery_info = rinfo; 1288 1289 return 0; 1290 } 1291 1292 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1293 { 1294 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1295 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1296 } 1297 1298 static const struct i2c_algorithm i2c_imx_algo = { 1299 .master_xfer = i2c_imx_xfer, 1300 .master_xfer_atomic = i2c_imx_xfer_atomic, 1301 .functionality = i2c_imx_func, 1302 .reg_slave = i2c_imx_reg_slave, 1303 .unreg_slave = i2c_imx_unreg_slave, 1304 }; 1305 1306 static int i2c_imx_probe(struct platform_device *pdev) 1307 { 1308 struct imx_i2c_struct *i2c_imx; 1309 struct resource *res; 1310 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1311 void __iomem *base; 1312 int irq, ret; 1313 dma_addr_t phy_addr; 1314 const struct imx_i2c_hwdata *match; 1315 1316 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1317 1318 irq = platform_get_irq(pdev, 0); 1319 if (irq < 0) 1320 return irq; 1321 1322 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1323 base = devm_ioremap_resource(&pdev->dev, res); 1324 if (IS_ERR(base)) 1325 return PTR_ERR(base); 1326 1327 phy_addr = (dma_addr_t)res->start; 1328 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1329 if (!i2c_imx) 1330 return -ENOMEM; 1331 1332 match = device_get_match_data(&pdev->dev); 1333 i2c_imx->hwdata = match; 1334 1335 /* Setup i2c_imx driver structure */ 1336 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1337 i2c_imx->adapter.owner = THIS_MODULE; 1338 i2c_imx->adapter.algo = &i2c_imx_algo; 1339 i2c_imx->adapter.dev.parent = &pdev->dev; 1340 i2c_imx->adapter.nr = pdev->id; 1341 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1342 i2c_imx->base = base; 1343 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1344 1345 /* Get I2C clock */ 1346 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1347 if (IS_ERR(i2c_imx->clk)) 1348 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1349 "can't get I2C clock\n"); 1350 1351 ret = clk_prepare_enable(i2c_imx->clk); 1352 if (ret) { 1353 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1354 return ret; 1355 } 1356 1357 /* Init queue */ 1358 init_waitqueue_head(&i2c_imx->queue); 1359 1360 /* Set up adapter data */ 1361 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1362 1363 /* Set up platform driver data */ 1364 platform_set_drvdata(pdev, i2c_imx); 1365 1366 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1367 pm_runtime_use_autosuspend(&pdev->dev); 1368 pm_runtime_set_active(&pdev->dev); 1369 pm_runtime_enable(&pdev->dev); 1370 1371 ret = pm_runtime_get_sync(&pdev->dev); 1372 if (ret < 0) 1373 goto rpm_disable; 1374 1375 /* Request IRQ */ 1376 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1377 pdev->name, i2c_imx); 1378 if (ret) { 1379 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1380 goto rpm_disable; 1381 } 1382 1383 /* Set up clock divider */ 1384 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1385 ret = of_property_read_u32(pdev->dev.of_node, 1386 "clock-frequency", &i2c_imx->bitrate); 1387 if (ret < 0 && pdata && pdata->bitrate) 1388 i2c_imx->bitrate = pdata->bitrate; 1389 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1390 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1391 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1392 1393 i2c_imx_reset_regs(i2c_imx); 1394 1395 /* Init optional bus recovery function */ 1396 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1397 /* Give it another chance if pinctrl used is not ready yet */ 1398 if (ret == -EPROBE_DEFER) 1399 goto clk_notifier_unregister; 1400 1401 /* Add I2C adapter */ 1402 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1403 if (ret < 0) 1404 goto clk_notifier_unregister; 1405 1406 pm_runtime_mark_last_busy(&pdev->dev); 1407 pm_runtime_put_autosuspend(&pdev->dev); 1408 1409 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1410 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1411 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1412 i2c_imx->adapter.name); 1413 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1414 1415 /* Init DMA config if supported */ 1416 i2c_imx_dma_request(i2c_imx, phy_addr); 1417 1418 return 0; /* Return OK */ 1419 1420 clk_notifier_unregister: 1421 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1422 free_irq(irq, i2c_imx); 1423 rpm_disable: 1424 pm_runtime_put_noidle(&pdev->dev); 1425 pm_runtime_disable(&pdev->dev); 1426 pm_runtime_set_suspended(&pdev->dev); 1427 pm_runtime_dont_use_autosuspend(&pdev->dev); 1428 clk_disable_unprepare(i2c_imx->clk); 1429 return ret; 1430 } 1431 1432 static int i2c_imx_remove(struct platform_device *pdev) 1433 { 1434 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1435 int irq, ret; 1436 1437 ret = pm_runtime_get_sync(&pdev->dev); 1438 if (ret < 0) 1439 return ret; 1440 1441 /* remove adapter */ 1442 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1443 i2c_del_adapter(&i2c_imx->adapter); 1444 1445 if (i2c_imx->dma) 1446 i2c_imx_dma_free(i2c_imx); 1447 1448 /* setup chip registers to defaults */ 1449 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1450 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1451 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1452 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1453 1454 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1455 irq = platform_get_irq(pdev, 0); 1456 if (irq >= 0) 1457 free_irq(irq, i2c_imx); 1458 clk_disable_unprepare(i2c_imx->clk); 1459 1460 pm_runtime_put_noidle(&pdev->dev); 1461 pm_runtime_disable(&pdev->dev); 1462 1463 return 0; 1464 } 1465 1466 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1467 { 1468 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1469 1470 clk_disable(i2c_imx->clk); 1471 1472 return 0; 1473 } 1474 1475 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1476 { 1477 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1478 int ret; 1479 1480 ret = clk_enable(i2c_imx->clk); 1481 if (ret) 1482 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1483 1484 return ret; 1485 } 1486 1487 static const struct dev_pm_ops i2c_imx_pm_ops = { 1488 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1489 i2c_imx_runtime_resume, NULL) 1490 }; 1491 1492 static struct platform_driver i2c_imx_driver = { 1493 .probe = i2c_imx_probe, 1494 .remove = i2c_imx_remove, 1495 .driver = { 1496 .name = DRIVER_NAME, 1497 .pm = &i2c_imx_pm_ops, 1498 .of_match_table = i2c_imx_dt_ids, 1499 .acpi_match_table = i2c_imx_acpi_ids, 1500 }, 1501 }; 1502 1503 static int __init i2c_adap_imx_init(void) 1504 { 1505 return platform_driver_register(&i2c_imx_driver); 1506 } 1507 subsys_initcall(i2c_adap_imx_init); 1508 1509 static void __exit i2c_adap_imx_exit(void) 1510 { 1511 platform_driver_unregister(&i2c_imx_driver); 1512 } 1513 module_exit(i2c_adap_imx_exit); 1514 1515 MODULE_LICENSE("GPL"); 1516 MODULE_AUTHOR("Darius Augulis"); 1517 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1518 MODULE_ALIAS("platform:" DRIVER_NAME); 1519