1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/completion.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/errno.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/i2c.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/io.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_dma.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/platform_data/i2c-imx.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/sched.h> 46 #include <linux/slab.h> 47 48 /* This will be the driver name the kernel reports */ 49 #define DRIVER_NAME "imx-i2c" 50 51 /* Default value */ 52 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 #define IMX_I2C_REGSHIFT 2 78 #define VF610_I2C_REGSHIFT 0 79 80 /* Bits of IMX I2C registers */ 81 #define I2SR_RXAK 0x01 82 #define I2SR_IIF 0x02 83 #define I2SR_SRW 0x04 84 #define I2SR_IAL 0x10 85 #define I2SR_IBB 0x20 86 #define I2SR_IAAS 0x40 87 #define I2SR_ICF 0x80 88 #define I2CR_DMAEN 0x02 89 #define I2CR_RSTA 0x04 90 #define I2CR_TXAK 0x08 91 #define I2CR_MTX 0x10 92 #define I2CR_MSTA 0x20 93 #define I2CR_IIEN 0x40 94 #define I2CR_IEN 0x80 95 96 /* register bits different operating codes definition: 97 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 98 * - write zero to clear(w0c) INT flag on i.MX, 99 * - but write one to clear(w1c) INT flag on Vybrid. 100 * 2) I2CR: I2C module enable operation also differ between SoCs: 101 * - set I2CR_IEN bit enable the module on i.MX, 102 * - but clear I2CR_IEN bit enable the module on Vybrid. 103 */ 104 #define I2SR_CLR_OPCODE_W0C 0x0 105 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 106 #define I2CR_IEN_OPCODE_0 0x0 107 #define I2CR_IEN_OPCODE_1 I2CR_IEN 108 109 #define I2C_PM_TIMEOUT 10 /* ms */ 110 111 /* 112 * sorted list of clock divider, register value pairs 113 * taken from table 26-5, p.26-9, Freescale i.MX 114 * Integrated Portable System Processor Reference Manual 115 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 116 * 117 * Duplicated divider values removed from list 118 */ 119 struct imx_i2c_clk_pair { 120 u16 div; 121 u16 val; 122 }; 123 124 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 125 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 126 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 127 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 128 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 129 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 130 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 131 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 132 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 133 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 134 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 135 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 136 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 137 { 3072, 0x1E }, { 3840, 0x1F } 138 }; 139 140 /* Vybrid VF610 clock divider, register value pairs */ 141 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 142 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 143 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 144 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 145 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 146 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 147 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 148 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 149 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 150 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 151 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 152 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 153 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 154 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 155 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 156 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 157 }; 158 159 enum imx_i2c_type { 160 IMX1_I2C, 161 IMX21_I2C, 162 VF610_I2C, 163 }; 164 165 struct imx_i2c_hwdata { 166 enum imx_i2c_type devtype; 167 unsigned regshift; 168 struct imx_i2c_clk_pair *clk_div; 169 unsigned ndivs; 170 unsigned i2sr_clr_opcode; 171 unsigned i2cr_ien_opcode; 172 }; 173 174 struct imx_i2c_dma { 175 struct dma_chan *chan_tx; 176 struct dma_chan *chan_rx; 177 struct dma_chan *chan_using; 178 struct completion cmd_complete; 179 dma_addr_t dma_buf; 180 unsigned int dma_len; 181 enum dma_transfer_direction dma_transfer_dir; 182 enum dma_data_direction dma_data_dir; 183 }; 184 185 struct imx_i2c_struct { 186 struct i2c_adapter adapter; 187 struct clk *clk; 188 struct notifier_block clk_change_nb; 189 void __iomem *base; 190 wait_queue_head_t queue; 191 unsigned long i2csr; 192 unsigned int disable_delay; 193 int stopped; 194 unsigned int ifdr; /* IMX_I2C_IFDR */ 195 unsigned int cur_clk; 196 unsigned int bitrate; 197 const struct imx_i2c_hwdata *hwdata; 198 struct i2c_bus_recovery_info rinfo; 199 200 struct pinctrl *pinctrl; 201 struct pinctrl_state *pinctrl_pins_default; 202 struct pinctrl_state *pinctrl_pins_gpio; 203 204 struct imx_i2c_dma *dma; 205 }; 206 207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 208 .devtype = IMX1_I2C, 209 .regshift = IMX_I2C_REGSHIFT, 210 .clk_div = imx_i2c_clk_div, 211 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 212 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 213 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 214 215 }; 216 217 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 218 .devtype = IMX21_I2C, 219 .regshift = IMX_I2C_REGSHIFT, 220 .clk_div = imx_i2c_clk_div, 221 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 222 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 223 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 224 225 }; 226 227 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 228 .devtype = VF610_I2C, 229 .regshift = VF610_I2C_REGSHIFT, 230 .clk_div = vf610_i2c_clk_div, 231 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 232 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 233 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 234 235 }; 236 237 static const struct platform_device_id imx_i2c_devtype[] = { 238 { 239 .name = "imx1-i2c", 240 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 241 }, { 242 .name = "imx21-i2c", 243 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 244 }, { 245 /* sentinel */ 246 } 247 }; 248 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 249 250 static const struct of_device_id i2c_imx_dt_ids[] = { 251 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 252 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 253 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 254 { /* sentinel */ } 255 }; 256 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 257 258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 259 { 260 return i2c_imx->hwdata->devtype == IMX1_I2C; 261 } 262 263 static inline void imx_i2c_write_reg(unsigned int val, 264 struct imx_i2c_struct *i2c_imx, unsigned int reg) 265 { 266 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 267 } 268 269 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 270 unsigned int reg) 271 { 272 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 273 } 274 275 /* Functions for DMA support */ 276 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 277 dma_addr_t phy_addr) 278 { 279 struct imx_i2c_dma *dma; 280 struct dma_slave_config dma_sconfig; 281 struct device *dev = &i2c_imx->adapter.dev; 282 int ret; 283 284 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 285 if (!dma) 286 return; 287 288 dma->chan_tx = dma_request_chan(dev, "tx"); 289 if (IS_ERR(dma->chan_tx)) { 290 ret = PTR_ERR(dma->chan_tx); 291 if (ret != -ENODEV && ret != -EPROBE_DEFER) 292 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 293 goto fail_al; 294 } 295 296 dma_sconfig.dst_addr = phy_addr + 297 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 298 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 299 dma_sconfig.dst_maxburst = 1; 300 dma_sconfig.direction = DMA_MEM_TO_DEV; 301 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 302 if (ret < 0) { 303 dev_err(dev, "can't configure tx channel (%d)\n", ret); 304 goto fail_tx; 305 } 306 307 dma->chan_rx = dma_request_chan(dev, "rx"); 308 if (IS_ERR(dma->chan_rx)) { 309 ret = PTR_ERR(dma->chan_rx); 310 if (ret != -ENODEV && ret != -EPROBE_DEFER) 311 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 312 goto fail_tx; 313 } 314 315 dma_sconfig.src_addr = phy_addr + 316 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 317 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 318 dma_sconfig.src_maxburst = 1; 319 dma_sconfig.direction = DMA_DEV_TO_MEM; 320 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 321 if (ret < 0) { 322 dev_err(dev, "can't configure rx channel (%d)\n", ret); 323 goto fail_rx; 324 } 325 326 i2c_imx->dma = dma; 327 init_completion(&dma->cmd_complete); 328 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 329 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 330 331 return; 332 333 fail_rx: 334 dma_release_channel(dma->chan_rx); 335 fail_tx: 336 dma_release_channel(dma->chan_tx); 337 fail_al: 338 devm_kfree(dev, dma); 339 } 340 341 static void i2c_imx_dma_callback(void *arg) 342 { 343 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 344 struct imx_i2c_dma *dma = i2c_imx->dma; 345 346 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 347 dma->dma_len, dma->dma_data_dir); 348 complete(&dma->cmd_complete); 349 } 350 351 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 352 struct i2c_msg *msgs) 353 { 354 struct imx_i2c_dma *dma = i2c_imx->dma; 355 struct dma_async_tx_descriptor *txdesc; 356 struct device *dev = &i2c_imx->adapter.dev; 357 struct device *chan_dev = dma->chan_using->device->dev; 358 359 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 360 dma->dma_len, dma->dma_data_dir); 361 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 362 dev_err(dev, "DMA mapping failed\n"); 363 goto err_map; 364 } 365 366 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 367 dma->dma_len, dma->dma_transfer_dir, 368 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 369 if (!txdesc) { 370 dev_err(dev, "Not able to get desc for DMA xfer\n"); 371 goto err_desc; 372 } 373 374 reinit_completion(&dma->cmd_complete); 375 txdesc->callback = i2c_imx_dma_callback; 376 txdesc->callback_param = i2c_imx; 377 if (dma_submit_error(dmaengine_submit(txdesc))) { 378 dev_err(dev, "DMA submit failed\n"); 379 goto err_submit; 380 } 381 382 dma_async_issue_pending(dma->chan_using); 383 return 0; 384 385 err_submit: 386 dmaengine_terminate_all(dma->chan_using); 387 err_desc: 388 dma_unmap_single(chan_dev, dma->dma_buf, 389 dma->dma_len, dma->dma_data_dir); 390 err_map: 391 return -EINVAL; 392 } 393 394 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 395 { 396 struct imx_i2c_dma *dma = i2c_imx->dma; 397 398 dma->dma_buf = 0; 399 dma->dma_len = 0; 400 401 dma_release_channel(dma->chan_tx); 402 dma->chan_tx = NULL; 403 404 dma_release_channel(dma->chan_rx); 405 dma->chan_rx = NULL; 406 407 dma->chan_using = NULL; 408 } 409 410 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 411 { 412 unsigned long orig_jiffies = jiffies; 413 unsigned int temp; 414 415 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 416 417 while (1) { 418 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 419 420 /* check for arbitration lost */ 421 if (temp & I2SR_IAL) { 422 temp &= ~I2SR_IAL; 423 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 424 return -EAGAIN; 425 } 426 427 if (for_busy && (temp & I2SR_IBB)) { 428 i2c_imx->stopped = 0; 429 break; 430 } 431 if (!for_busy && !(temp & I2SR_IBB)) { 432 i2c_imx->stopped = 1; 433 break; 434 } 435 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 436 dev_dbg(&i2c_imx->adapter.dev, 437 "<%s> I2C bus is busy\n", __func__); 438 return -ETIMEDOUT; 439 } 440 schedule(); 441 } 442 443 return 0; 444 } 445 446 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 447 { 448 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 449 450 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 451 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 452 return -ETIMEDOUT; 453 } 454 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 455 i2c_imx->i2csr = 0; 456 return 0; 457 } 458 459 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 460 { 461 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 462 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 463 return -ENXIO; /* No ACK */ 464 } 465 466 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 467 return 0; 468 } 469 470 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 471 unsigned int i2c_clk_rate) 472 { 473 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 474 unsigned int div; 475 int i; 476 477 /* Divider value calculation */ 478 if (i2c_imx->cur_clk == i2c_clk_rate) 479 return; 480 481 i2c_imx->cur_clk = i2c_clk_rate; 482 483 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 484 if (div < i2c_clk_div[0].div) 485 i = 0; 486 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 487 i = i2c_imx->hwdata->ndivs - 1; 488 else 489 for (i = 0; i2c_clk_div[i].div < div; i++) 490 ; 491 492 /* Store divider value */ 493 i2c_imx->ifdr = i2c_clk_div[i].val; 494 495 /* 496 * There dummy delay is calculated. 497 * It should be about one I2C clock period long. 498 * This delay is used in I2C bus disable function 499 * to fix chip hardware bug. 500 */ 501 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 502 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 503 504 #ifdef CONFIG_I2C_DEBUG_BUS 505 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 506 i2c_clk_rate, div); 507 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 508 i2c_clk_div[i].val, i2c_clk_div[i].div); 509 #endif 510 } 511 512 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 513 unsigned long action, void *data) 514 { 515 struct clk_notifier_data *ndata = data; 516 struct imx_i2c_struct *i2c_imx = container_of(nb, 517 struct imx_i2c_struct, 518 clk_change_nb); 519 520 if (action & POST_RATE_CHANGE) 521 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 522 523 return NOTIFY_OK; 524 } 525 526 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 527 { 528 unsigned int temp = 0; 529 int result; 530 531 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 532 533 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 534 /* Enable I2C controller */ 535 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 536 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 537 538 /* Wait controller to be stable */ 539 usleep_range(50, 150); 540 541 /* Start I2C transaction */ 542 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 543 temp |= I2CR_MSTA; 544 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 545 result = i2c_imx_bus_busy(i2c_imx, 1); 546 if (result) 547 return result; 548 549 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 550 temp &= ~I2CR_DMAEN; 551 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 552 return result; 553 } 554 555 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 556 { 557 unsigned int temp = 0; 558 559 if (!i2c_imx->stopped) { 560 /* Stop I2C transaction */ 561 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 562 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 563 temp &= ~(I2CR_MSTA | I2CR_MTX); 564 if (i2c_imx->dma) 565 temp &= ~I2CR_DMAEN; 566 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 567 } 568 if (is_imx1_i2c(i2c_imx)) { 569 /* 570 * This delay caused by an i.MXL hardware bug. 571 * If no (or too short) delay, no "STOP" bit will be generated. 572 */ 573 udelay(i2c_imx->disable_delay); 574 } 575 576 if (!i2c_imx->stopped) 577 i2c_imx_bus_busy(i2c_imx, 0); 578 579 /* Disable I2C controller */ 580 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 581 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 582 } 583 584 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 585 { 586 struct imx_i2c_struct *i2c_imx = dev_id; 587 unsigned int temp; 588 589 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 590 if (temp & I2SR_IIF) { 591 /* save status register */ 592 i2c_imx->i2csr = temp; 593 temp &= ~I2SR_IIF; 594 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 595 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 596 wake_up(&i2c_imx->queue); 597 return IRQ_HANDLED; 598 } 599 600 return IRQ_NONE; 601 } 602 603 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 604 struct i2c_msg *msgs) 605 { 606 int result; 607 unsigned long time_left; 608 unsigned int temp = 0; 609 unsigned long orig_jiffies = jiffies; 610 struct imx_i2c_dma *dma = i2c_imx->dma; 611 struct device *dev = &i2c_imx->adapter.dev; 612 613 dma->chan_using = dma->chan_tx; 614 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 615 dma->dma_data_dir = DMA_TO_DEVICE; 616 dma->dma_len = msgs->len - 1; 617 result = i2c_imx_dma_xfer(i2c_imx, msgs); 618 if (result) 619 return result; 620 621 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 622 temp |= I2CR_DMAEN; 623 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 624 625 /* 626 * Write slave address. 627 * The first byte must be transmitted by the CPU. 628 */ 629 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 630 time_left = wait_for_completion_timeout( 631 &i2c_imx->dma->cmd_complete, 632 msecs_to_jiffies(DMA_TIMEOUT)); 633 if (time_left == 0) { 634 dmaengine_terminate_all(dma->chan_using); 635 return -ETIMEDOUT; 636 } 637 638 /* Waiting for transfer complete. */ 639 while (1) { 640 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 641 if (temp & I2SR_ICF) 642 break; 643 if (time_after(jiffies, orig_jiffies + 644 msecs_to_jiffies(DMA_TIMEOUT))) { 645 dev_dbg(dev, "<%s> Timeout\n", __func__); 646 return -ETIMEDOUT; 647 } 648 schedule(); 649 } 650 651 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 652 temp &= ~I2CR_DMAEN; 653 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 654 655 /* The last data byte must be transferred by the CPU. */ 656 imx_i2c_write_reg(msgs->buf[msgs->len-1], 657 i2c_imx, IMX_I2C_I2DR); 658 result = i2c_imx_trx_complete(i2c_imx); 659 if (result) 660 return result; 661 662 return i2c_imx_acked(i2c_imx); 663 } 664 665 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 666 struct i2c_msg *msgs, bool is_lastmsg) 667 { 668 int result; 669 unsigned long time_left; 670 unsigned int temp; 671 unsigned long orig_jiffies = jiffies; 672 struct imx_i2c_dma *dma = i2c_imx->dma; 673 struct device *dev = &i2c_imx->adapter.dev; 674 675 676 dma->chan_using = dma->chan_rx; 677 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 678 dma->dma_data_dir = DMA_FROM_DEVICE; 679 /* The last two data bytes must be transferred by the CPU. */ 680 dma->dma_len = msgs->len - 2; 681 result = i2c_imx_dma_xfer(i2c_imx, msgs); 682 if (result) 683 return result; 684 685 time_left = wait_for_completion_timeout( 686 &i2c_imx->dma->cmd_complete, 687 msecs_to_jiffies(DMA_TIMEOUT)); 688 if (time_left == 0) { 689 dmaengine_terminate_all(dma->chan_using); 690 return -ETIMEDOUT; 691 } 692 693 /* waiting for transfer complete. */ 694 while (1) { 695 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 696 if (temp & I2SR_ICF) 697 break; 698 if (time_after(jiffies, orig_jiffies + 699 msecs_to_jiffies(DMA_TIMEOUT))) { 700 dev_dbg(dev, "<%s> Timeout\n", __func__); 701 return -ETIMEDOUT; 702 } 703 schedule(); 704 } 705 706 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 707 temp &= ~I2CR_DMAEN; 708 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 709 710 /* read n-1 byte data */ 711 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 712 temp |= I2CR_TXAK; 713 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 714 715 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 716 /* read n byte data */ 717 result = i2c_imx_trx_complete(i2c_imx); 718 if (result) 719 return result; 720 721 if (is_lastmsg) { 722 /* 723 * It must generate STOP before read I2DR to prevent 724 * controller from generating another clock cycle 725 */ 726 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 727 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 728 temp &= ~(I2CR_MSTA | I2CR_MTX); 729 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 730 i2c_imx_bus_busy(i2c_imx, 0); 731 } else { 732 /* 733 * For i2c master receiver repeat restart operation like: 734 * read -> repeat MSTA -> read/write 735 * The controller must set MTX before read the last byte in 736 * the first read operation, otherwise the first read cost 737 * one extra clock cycle. 738 */ 739 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 740 temp |= I2CR_MTX; 741 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 742 } 743 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 744 745 return 0; 746 } 747 748 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 749 { 750 int i, result; 751 752 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 753 __func__, i2c_8bit_addr_from_msg(msgs)); 754 755 /* write slave address */ 756 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 757 result = i2c_imx_trx_complete(i2c_imx); 758 if (result) 759 return result; 760 result = i2c_imx_acked(i2c_imx); 761 if (result) 762 return result; 763 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 764 765 /* write data */ 766 for (i = 0; i < msgs->len; i++) { 767 dev_dbg(&i2c_imx->adapter.dev, 768 "<%s> write byte: B%d=0x%X\n", 769 __func__, i, msgs->buf[i]); 770 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 771 result = i2c_imx_trx_complete(i2c_imx); 772 if (result) 773 return result; 774 result = i2c_imx_acked(i2c_imx); 775 if (result) 776 return result; 777 } 778 return 0; 779 } 780 781 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 782 { 783 int i, result; 784 unsigned int temp; 785 int block_data = msgs->flags & I2C_M_RECV_LEN; 786 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 787 788 dev_dbg(&i2c_imx->adapter.dev, 789 "<%s> write slave address: addr=0x%x\n", 790 __func__, i2c_8bit_addr_from_msg(msgs)); 791 792 /* write slave address */ 793 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 794 result = i2c_imx_trx_complete(i2c_imx); 795 if (result) 796 return result; 797 result = i2c_imx_acked(i2c_imx); 798 if (result) 799 return result; 800 801 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 802 803 /* setup bus to read data */ 804 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 805 temp &= ~I2CR_MTX; 806 807 /* 808 * Reset the I2CR_TXAK flag initially for SMBus block read since the 809 * length is unknown 810 */ 811 if ((msgs->len - 1) || block_data) 812 temp &= ~I2CR_TXAK; 813 if (use_dma) 814 temp |= I2CR_DMAEN; 815 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 816 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 817 818 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 819 820 if (use_dma) 821 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 822 823 /* read data */ 824 for (i = 0; i < msgs->len; i++) { 825 u8 len = 0; 826 827 result = i2c_imx_trx_complete(i2c_imx); 828 if (result) 829 return result; 830 /* 831 * First byte is the length of remaining packet 832 * in the SMBus block data read. Add it to 833 * msgs->len. 834 */ 835 if ((!i) && block_data) { 836 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 837 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 838 return -EPROTO; 839 dev_dbg(&i2c_imx->adapter.dev, 840 "<%s> read length: 0x%X\n", 841 __func__, len); 842 msgs->len += len; 843 } 844 if (i == (msgs->len - 1)) { 845 if (is_lastmsg) { 846 /* 847 * It must generate STOP before read I2DR to prevent 848 * controller from generating another clock cycle 849 */ 850 dev_dbg(&i2c_imx->adapter.dev, 851 "<%s> clear MSTA\n", __func__); 852 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 853 temp &= ~(I2CR_MSTA | I2CR_MTX); 854 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 855 i2c_imx_bus_busy(i2c_imx, 0); 856 } else { 857 /* 858 * For i2c master receiver repeat restart operation like: 859 * read -> repeat MSTA -> read/write 860 * The controller must set MTX before read the last byte in 861 * the first read operation, otherwise the first read cost 862 * one extra clock cycle. 863 */ 864 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 865 temp |= I2CR_MTX; 866 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 867 } 868 } else if (i == (msgs->len - 2)) { 869 dev_dbg(&i2c_imx->adapter.dev, 870 "<%s> set TXAK\n", __func__); 871 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 872 temp |= I2CR_TXAK; 873 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 874 } 875 if ((!i) && block_data) 876 msgs->buf[0] = len; 877 else 878 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 879 dev_dbg(&i2c_imx->adapter.dev, 880 "<%s> read byte: B%d=0x%X\n", 881 __func__, i, msgs->buf[i]); 882 } 883 return 0; 884 } 885 886 static int i2c_imx_xfer(struct i2c_adapter *adapter, 887 struct i2c_msg *msgs, int num) 888 { 889 unsigned int i, temp; 890 int result; 891 bool is_lastmsg = false; 892 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 893 894 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 895 896 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 897 if (result < 0) 898 goto out; 899 900 /* Start I2C transfer */ 901 result = i2c_imx_start(i2c_imx); 902 if (result) { 903 if (i2c_imx->adapter.bus_recovery_info) { 904 i2c_recover_bus(&i2c_imx->adapter); 905 result = i2c_imx_start(i2c_imx); 906 } 907 } 908 909 if (result) 910 goto fail0; 911 912 /* read/write data */ 913 for (i = 0; i < num; i++) { 914 if (i == num - 1) 915 is_lastmsg = true; 916 917 if (i) { 918 dev_dbg(&i2c_imx->adapter.dev, 919 "<%s> repeated start\n", __func__); 920 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 921 temp |= I2CR_RSTA; 922 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 923 result = i2c_imx_bus_busy(i2c_imx, 1); 924 if (result) 925 goto fail0; 926 } 927 dev_dbg(&i2c_imx->adapter.dev, 928 "<%s> transfer message: %d\n", __func__, i); 929 /* write/read data */ 930 #ifdef CONFIG_I2C_DEBUG_BUS 931 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 932 dev_dbg(&i2c_imx->adapter.dev, 933 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 934 __func__, 935 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 936 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 937 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 938 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 939 dev_dbg(&i2c_imx->adapter.dev, 940 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 941 __func__, 942 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 943 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 944 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 945 (temp & I2SR_RXAK ? 1 : 0)); 946 #endif 947 if (msgs[i].flags & I2C_M_RD) 948 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 949 else { 950 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 951 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 952 else 953 result = i2c_imx_write(i2c_imx, &msgs[i]); 954 } 955 if (result) 956 goto fail0; 957 } 958 959 fail0: 960 /* Stop I2C transfer */ 961 i2c_imx_stop(i2c_imx); 962 963 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 964 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 965 966 out: 967 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 968 (result < 0) ? "error" : "success msg", 969 (result < 0) ? result : num); 970 return (result < 0) ? result : num; 971 } 972 973 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 974 { 975 struct imx_i2c_struct *i2c_imx; 976 977 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 978 979 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 980 } 981 982 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 983 { 984 struct imx_i2c_struct *i2c_imx; 985 986 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 987 988 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 989 } 990 991 /* 992 * We switch SCL and SDA to their GPIO function and do some bitbanging 993 * for bus recovery. These alternative pinmux settings can be 994 * described in the device tree by a separate pinctrl state "gpio". If 995 * this is missing this is not a big problem, the only implication is 996 * that we can't do bus recovery. 997 */ 998 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 999 struct platform_device *pdev) 1000 { 1001 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1002 1003 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1004 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1005 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1006 return PTR_ERR(i2c_imx->pinctrl); 1007 } 1008 1009 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1010 PINCTRL_STATE_DEFAULT); 1011 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1012 "gpio"); 1013 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1014 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1015 1016 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1017 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1018 return -EPROBE_DEFER; 1019 } else if (IS_ERR(rinfo->sda_gpiod) || 1020 IS_ERR(rinfo->scl_gpiod) || 1021 IS_ERR(i2c_imx->pinctrl_pins_default) || 1022 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1023 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1024 return 0; 1025 } 1026 1027 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1028 rinfo->sda_gpiod ? ",sda" : ""); 1029 1030 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1031 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1032 rinfo->recover_bus = i2c_generic_scl_recovery; 1033 i2c_imx->adapter.bus_recovery_info = rinfo; 1034 1035 return 0; 1036 } 1037 1038 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1039 { 1040 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1041 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1042 } 1043 1044 static const struct i2c_algorithm i2c_imx_algo = { 1045 .master_xfer = i2c_imx_xfer, 1046 .functionality = i2c_imx_func, 1047 }; 1048 1049 static int i2c_imx_probe(struct platform_device *pdev) 1050 { 1051 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 1052 &pdev->dev); 1053 struct imx_i2c_struct *i2c_imx; 1054 struct resource *res; 1055 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1056 void __iomem *base; 1057 int irq, ret; 1058 dma_addr_t phy_addr; 1059 1060 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1061 1062 irq = platform_get_irq(pdev, 0); 1063 if (irq < 0) { 1064 dev_err(&pdev->dev, "can't get irq number\n"); 1065 return irq; 1066 } 1067 1068 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1069 base = devm_ioremap_resource(&pdev->dev, res); 1070 if (IS_ERR(base)) 1071 return PTR_ERR(base); 1072 1073 phy_addr = (dma_addr_t)res->start; 1074 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1075 if (!i2c_imx) 1076 return -ENOMEM; 1077 1078 if (of_id) 1079 i2c_imx->hwdata = of_id->data; 1080 else 1081 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1082 platform_get_device_id(pdev)->driver_data; 1083 1084 /* Setup i2c_imx driver structure */ 1085 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1086 i2c_imx->adapter.owner = THIS_MODULE; 1087 i2c_imx->adapter.algo = &i2c_imx_algo; 1088 i2c_imx->adapter.dev.parent = &pdev->dev; 1089 i2c_imx->adapter.nr = pdev->id; 1090 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1091 i2c_imx->base = base; 1092 1093 /* Get I2C clock */ 1094 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1095 if (IS_ERR(i2c_imx->clk)) { 1096 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER) 1097 dev_err(&pdev->dev, "can't get I2C clock\n"); 1098 return PTR_ERR(i2c_imx->clk); 1099 } 1100 1101 ret = clk_prepare_enable(i2c_imx->clk); 1102 if (ret) { 1103 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1104 return ret; 1105 } 1106 1107 /* Request IRQ */ 1108 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED, 1109 pdev->name, i2c_imx); 1110 if (ret) { 1111 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1112 goto clk_disable; 1113 } 1114 1115 /* Init queue */ 1116 init_waitqueue_head(&i2c_imx->queue); 1117 1118 /* Set up adapter data */ 1119 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1120 1121 /* Set up platform driver data */ 1122 platform_set_drvdata(pdev, i2c_imx); 1123 1124 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1125 pm_runtime_use_autosuspend(&pdev->dev); 1126 pm_runtime_set_active(&pdev->dev); 1127 pm_runtime_enable(&pdev->dev); 1128 1129 ret = pm_runtime_get_sync(&pdev->dev); 1130 if (ret < 0) 1131 goto rpm_disable; 1132 1133 /* Set up clock divider */ 1134 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 1135 ret = of_property_read_u32(pdev->dev.of_node, 1136 "clock-frequency", &i2c_imx->bitrate); 1137 if (ret < 0 && pdata && pdata->bitrate) 1138 i2c_imx->bitrate = pdata->bitrate; 1139 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1140 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1141 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1142 1143 /* Set up chip registers to defaults */ 1144 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1145 i2c_imx, IMX_I2C_I2CR); 1146 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1147 1148 /* Init optional bus recovery function */ 1149 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1150 /* Give it another chance if pinctrl used is not ready yet */ 1151 if (ret == -EPROBE_DEFER) 1152 goto clk_notifier_unregister; 1153 1154 /* Add I2C adapter */ 1155 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1156 if (ret < 0) 1157 goto clk_notifier_unregister; 1158 1159 pm_runtime_mark_last_busy(&pdev->dev); 1160 pm_runtime_put_autosuspend(&pdev->dev); 1161 1162 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1163 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1164 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1165 i2c_imx->adapter.name); 1166 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1167 1168 /* Init DMA config if supported */ 1169 i2c_imx_dma_request(i2c_imx, phy_addr); 1170 1171 return 0; /* Return OK */ 1172 1173 clk_notifier_unregister: 1174 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1175 rpm_disable: 1176 pm_runtime_put_noidle(&pdev->dev); 1177 pm_runtime_disable(&pdev->dev); 1178 pm_runtime_set_suspended(&pdev->dev); 1179 pm_runtime_dont_use_autosuspend(&pdev->dev); 1180 1181 clk_disable: 1182 clk_disable_unprepare(i2c_imx->clk); 1183 return ret; 1184 } 1185 1186 static int i2c_imx_remove(struct platform_device *pdev) 1187 { 1188 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1189 int ret; 1190 1191 ret = pm_runtime_get_sync(&pdev->dev); 1192 if (ret < 0) 1193 return ret; 1194 1195 /* remove adapter */ 1196 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1197 i2c_del_adapter(&i2c_imx->adapter); 1198 1199 if (i2c_imx->dma) 1200 i2c_imx_dma_free(i2c_imx); 1201 1202 /* setup chip registers to defaults */ 1203 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1204 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1205 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1206 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1207 1208 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1209 clk_disable_unprepare(i2c_imx->clk); 1210 1211 pm_runtime_put_noidle(&pdev->dev); 1212 pm_runtime_disable(&pdev->dev); 1213 1214 return 0; 1215 } 1216 1217 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1218 { 1219 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1220 1221 clk_disable(i2c_imx->clk); 1222 1223 return 0; 1224 } 1225 1226 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1227 { 1228 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1229 int ret; 1230 1231 ret = clk_enable(i2c_imx->clk); 1232 if (ret) 1233 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1234 1235 return ret; 1236 } 1237 1238 static const struct dev_pm_ops i2c_imx_pm_ops = { 1239 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1240 i2c_imx_runtime_resume, NULL) 1241 }; 1242 1243 static struct platform_driver i2c_imx_driver = { 1244 .probe = i2c_imx_probe, 1245 .remove = i2c_imx_remove, 1246 .driver = { 1247 .name = DRIVER_NAME, 1248 .pm = &i2c_imx_pm_ops, 1249 .of_match_table = i2c_imx_dt_ids, 1250 }, 1251 .id_table = imx_i2c_devtype, 1252 }; 1253 1254 static int __init i2c_adap_imx_init(void) 1255 { 1256 return platform_driver_register(&i2c_imx_driver); 1257 } 1258 subsys_initcall(i2c_adap_imx_init); 1259 1260 static void __exit i2c_adap_imx_exit(void) 1261 { 1262 platform_driver_unregister(&i2c_imx_driver); 1263 } 1264 module_exit(i2c_adap_imx_exit); 1265 1266 MODULE_LICENSE("GPL"); 1267 MODULE_AUTHOR("Darius Augulis"); 1268 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1269 MODULE_ALIAS("platform:" DRIVER_NAME); 1270