1 /* 2 * Copyright (C) 2002 Motorola GSG-China 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * Author: 15 * Darius Augulis, Teltonika Inc. 16 * 17 * Desc.: 18 * Implementation of I2C Adapter/Algorithm Driver 19 * for I2C Bus integrated in Freescale i.MX/MXC processors 20 * 21 * Derived from Motorola GSG China I2C example driver 22 * 23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 25 * Copyright (C) 2007 RightHand Technologies, Inc. 26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 27 * 28 * Copyright 2013 Freescale Semiconductor, Inc. 29 * 30 */ 31 32 /** Includes ******************************************************************* 33 *******************************************************************************/ 34 35 #include <linux/clk.h> 36 #include <linux/completion.h> 37 #include <linux/delay.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dmapool.h> 41 #include <linux/err.h> 42 #include <linux/errno.h> 43 #include <linux/i2c.h> 44 #include <linux/init.h> 45 #include <linux/interrupt.h> 46 #include <linux/io.h> 47 #include <linux/kernel.h> 48 #include <linux/module.h> 49 #include <linux/of.h> 50 #include <linux/of_device.h> 51 #include <linux/of_dma.h> 52 #include <linux/platform_data/i2c-imx.h> 53 #include <linux/platform_device.h> 54 #include <linux/sched.h> 55 #include <linux/slab.h> 56 57 /** Defines ******************************************************************** 58 *******************************************************************************/ 59 60 /* This will be the driver name the kernel reports */ 61 #define DRIVER_NAME "imx-i2c" 62 63 /* Default value */ 64 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 65 66 /* 67 * Enable DMA if transfer byte size is bigger than this threshold. 68 * As the hardware request, it must bigger than 4 bytes.\ 69 * I have set '16' here, maybe it's not the best but I think it's 70 * the appropriate. 71 */ 72 #define DMA_THRESHOLD 16 73 #define DMA_TIMEOUT 1000 74 75 /* IMX I2C registers: 76 * the I2C register offset is different between SoCs, 77 * to provid support for all these chips, split the 78 * register offset into a fixed base address and a 79 * variable shift value, then the full register offset 80 * will be calculated by 81 * reg_off = ( reg_base_addr << reg_shift) 82 */ 83 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 84 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 85 #define IMX_I2C_I2CR 0x02 /* i2c control */ 86 #define IMX_I2C_I2SR 0x03 /* i2c status */ 87 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 88 89 #define IMX_I2C_REGSHIFT 2 90 #define VF610_I2C_REGSHIFT 0 91 92 /* Bits of IMX I2C registers */ 93 #define I2SR_RXAK 0x01 94 #define I2SR_IIF 0x02 95 #define I2SR_SRW 0x04 96 #define I2SR_IAL 0x10 97 #define I2SR_IBB 0x20 98 #define I2SR_IAAS 0x40 99 #define I2SR_ICF 0x80 100 #define I2CR_DMAEN 0x02 101 #define I2CR_RSTA 0x04 102 #define I2CR_TXAK 0x08 103 #define I2CR_MTX 0x10 104 #define I2CR_MSTA 0x20 105 #define I2CR_IIEN 0x40 106 #define I2CR_IEN 0x80 107 108 /* register bits different operating codes definition: 109 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 110 * - write zero to clear(w0c) INT flag on i.MX, 111 * - but write one to clear(w1c) INT flag on Vybrid. 112 * 2) I2CR: I2C module enable operation also differ between SoCs: 113 * - set I2CR_IEN bit enable the module on i.MX, 114 * - but clear I2CR_IEN bit enable the module on Vybrid. 115 */ 116 #define I2SR_CLR_OPCODE_W0C 0x0 117 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 118 #define I2CR_IEN_OPCODE_0 0x0 119 #define I2CR_IEN_OPCODE_1 I2CR_IEN 120 121 /** Variables ****************************************************************** 122 *******************************************************************************/ 123 124 /* 125 * sorted list of clock divider, register value pairs 126 * taken from table 26-5, p.26-9, Freescale i.MX 127 * Integrated Portable System Processor Reference Manual 128 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 129 * 130 * Duplicated divider values removed from list 131 */ 132 struct imx_i2c_clk_pair { 133 u16 div; 134 u16 val; 135 }; 136 137 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 138 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 139 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 140 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 141 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 142 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 143 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 144 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 145 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 146 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 147 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 148 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 149 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 150 { 3072, 0x1E }, { 3840, 0x1F } 151 }; 152 153 /* Vybrid VF610 clock divider, register value pairs */ 154 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 155 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 156 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 157 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 158 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 159 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 160 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 161 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 162 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 163 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 164 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 165 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 166 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 167 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 168 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 169 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 170 }; 171 172 enum imx_i2c_type { 173 IMX1_I2C, 174 IMX21_I2C, 175 VF610_I2C, 176 }; 177 178 struct imx_i2c_hwdata { 179 enum imx_i2c_type devtype; 180 unsigned regshift; 181 struct imx_i2c_clk_pair *clk_div; 182 unsigned ndivs; 183 unsigned i2sr_clr_opcode; 184 unsigned i2cr_ien_opcode; 185 }; 186 187 struct imx_i2c_dma { 188 struct dma_chan *chan_tx; 189 struct dma_chan *chan_rx; 190 struct dma_chan *chan_using; 191 struct completion cmd_complete; 192 dma_addr_t dma_buf; 193 unsigned int dma_len; 194 enum dma_transfer_direction dma_transfer_dir; 195 enum dma_data_direction dma_data_dir; 196 }; 197 198 struct imx_i2c_struct { 199 struct i2c_adapter adapter; 200 struct clk *clk; 201 void __iomem *base; 202 wait_queue_head_t queue; 203 unsigned long i2csr; 204 unsigned int disable_delay; 205 int stopped; 206 unsigned int ifdr; /* IMX_I2C_IFDR */ 207 unsigned int cur_clk; 208 unsigned int bitrate; 209 const struct imx_i2c_hwdata *hwdata; 210 211 struct imx_i2c_dma *dma; 212 }; 213 214 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 215 .devtype = IMX1_I2C, 216 .regshift = IMX_I2C_REGSHIFT, 217 .clk_div = imx_i2c_clk_div, 218 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 219 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 220 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 221 222 }; 223 224 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 225 .devtype = IMX21_I2C, 226 .regshift = IMX_I2C_REGSHIFT, 227 .clk_div = imx_i2c_clk_div, 228 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 229 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 230 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 231 232 }; 233 234 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 235 .devtype = VF610_I2C, 236 .regshift = VF610_I2C_REGSHIFT, 237 .clk_div = vf610_i2c_clk_div, 238 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 239 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 240 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 241 242 }; 243 244 static struct platform_device_id imx_i2c_devtype[] = { 245 { 246 .name = "imx1-i2c", 247 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 248 }, { 249 .name = "imx21-i2c", 250 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 251 }, { 252 /* sentinel */ 253 } 254 }; 255 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 256 257 static const struct of_device_id i2c_imx_dt_ids[] = { 258 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 259 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 260 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 261 { /* sentinel */ } 262 }; 263 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 264 265 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 266 { 267 return i2c_imx->hwdata->devtype == IMX1_I2C; 268 } 269 270 static inline void imx_i2c_write_reg(unsigned int val, 271 struct imx_i2c_struct *i2c_imx, unsigned int reg) 272 { 273 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 274 } 275 276 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 277 unsigned int reg) 278 { 279 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 280 } 281 282 /* Functions for DMA support */ 283 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 284 dma_addr_t phy_addr) 285 { 286 struct imx_i2c_dma *dma; 287 struct dma_slave_config dma_sconfig; 288 struct device *dev = &i2c_imx->adapter.dev; 289 int ret; 290 291 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 292 if (!dma) 293 return; 294 295 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 296 if (!dma->chan_tx) { 297 dev_dbg(dev, "can't request DMA tx channel\n"); 298 goto fail_al; 299 } 300 301 dma_sconfig.dst_addr = phy_addr + 302 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 303 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 304 dma_sconfig.dst_maxburst = 1; 305 dma_sconfig.direction = DMA_MEM_TO_DEV; 306 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 307 if (ret < 0) { 308 dev_dbg(dev, "can't configure tx channel\n"); 309 goto fail_tx; 310 } 311 312 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 313 if (!dma->chan_rx) { 314 dev_dbg(dev, "can't request DMA rx channel\n"); 315 goto fail_tx; 316 } 317 318 dma_sconfig.src_addr = phy_addr + 319 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 320 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 321 dma_sconfig.src_maxburst = 1; 322 dma_sconfig.direction = DMA_DEV_TO_MEM; 323 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 324 if (ret < 0) { 325 dev_dbg(dev, "can't configure rx channel\n"); 326 goto fail_rx; 327 } 328 329 i2c_imx->dma = dma; 330 init_completion(&dma->cmd_complete); 331 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 332 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 333 334 return; 335 336 fail_rx: 337 dma_release_channel(dma->chan_rx); 338 fail_tx: 339 dma_release_channel(dma->chan_tx); 340 fail_al: 341 devm_kfree(dev, dma); 342 dev_info(dev, "can't use DMA\n"); 343 } 344 345 static void i2c_imx_dma_callback(void *arg) 346 { 347 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 348 struct imx_i2c_dma *dma = i2c_imx->dma; 349 350 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 351 dma->dma_len, dma->dma_data_dir); 352 complete(&dma->cmd_complete); 353 } 354 355 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 356 struct i2c_msg *msgs) 357 { 358 struct imx_i2c_dma *dma = i2c_imx->dma; 359 struct dma_async_tx_descriptor *txdesc; 360 struct device *dev = &i2c_imx->adapter.dev; 361 struct device *chan_dev = dma->chan_using->device->dev; 362 363 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 364 dma->dma_len, dma->dma_data_dir); 365 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 366 dev_err(dev, "DMA mapping failed\n"); 367 goto err_map; 368 } 369 370 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 371 dma->dma_len, dma->dma_transfer_dir, 372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 373 if (!txdesc) { 374 dev_err(dev, "Not able to get desc for DMA xfer\n"); 375 goto err_desc; 376 } 377 378 txdesc->callback = i2c_imx_dma_callback; 379 txdesc->callback_param = i2c_imx; 380 if (dma_submit_error(dmaengine_submit(txdesc))) { 381 dev_err(dev, "DMA submit failed\n"); 382 goto err_submit; 383 } 384 385 dma_async_issue_pending(dma->chan_using); 386 return 0; 387 388 err_submit: 389 err_desc: 390 dma_unmap_single(chan_dev, dma->dma_buf, 391 dma->dma_len, dma->dma_data_dir); 392 err_map: 393 return -EINVAL; 394 } 395 396 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 397 { 398 struct imx_i2c_dma *dma = i2c_imx->dma; 399 400 dma->dma_buf = 0; 401 dma->dma_len = 0; 402 403 dma_release_channel(dma->chan_tx); 404 dma->chan_tx = NULL; 405 406 dma_release_channel(dma->chan_rx); 407 dma->chan_rx = NULL; 408 409 dma->chan_using = NULL; 410 } 411 412 /** Functions for IMX I2C adapter driver *************************************** 413 *******************************************************************************/ 414 415 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 416 { 417 unsigned long orig_jiffies = jiffies; 418 unsigned int temp; 419 420 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 421 422 while (1) { 423 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 424 425 /* check for arbitration lost */ 426 if (temp & I2SR_IAL) { 427 temp &= ~I2SR_IAL; 428 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 429 return -EAGAIN; 430 } 431 432 if (for_busy && (temp & I2SR_IBB)) 433 break; 434 if (!for_busy && !(temp & I2SR_IBB)) 435 break; 436 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 437 dev_dbg(&i2c_imx->adapter.dev, 438 "<%s> I2C bus is busy\n", __func__); 439 return -ETIMEDOUT; 440 } 441 schedule(); 442 } 443 444 return 0; 445 } 446 447 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 448 { 449 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 450 451 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 452 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 453 return -ETIMEDOUT; 454 } 455 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 456 i2c_imx->i2csr = 0; 457 return 0; 458 } 459 460 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 461 { 462 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 463 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 464 return -EIO; /* No ACK */ 465 } 466 467 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 468 return 0; 469 } 470 471 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx) 472 { 473 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 474 unsigned int i2c_clk_rate; 475 unsigned int div; 476 int i; 477 478 /* Divider value calculation */ 479 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 480 if (i2c_imx->cur_clk == i2c_clk_rate) 481 return; 482 483 i2c_imx->cur_clk = i2c_clk_rate; 484 485 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 486 if (div < i2c_clk_div[0].div) 487 i = 0; 488 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 489 i = i2c_imx->hwdata->ndivs - 1; 490 else 491 for (i = 0; i2c_clk_div[i].div < div; i++) 492 ; 493 494 /* Store divider value */ 495 i2c_imx->ifdr = i2c_clk_div[i].val; 496 497 /* 498 * There dummy delay is calculated. 499 * It should be about one I2C clock period long. 500 * This delay is used in I2C bus disable function 501 * to fix chip hardware bug. 502 */ 503 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 504 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 505 506 #ifdef CONFIG_I2C_DEBUG_BUS 507 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 508 i2c_clk_rate, div); 509 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 510 i2c_clk_div[i].val, i2c_clk_div[i].div); 511 #endif 512 } 513 514 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 515 { 516 unsigned int temp = 0; 517 int result; 518 519 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 520 521 i2c_imx_set_clk(i2c_imx); 522 523 result = clk_prepare_enable(i2c_imx->clk); 524 if (result) 525 return result; 526 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 527 /* Enable I2C controller */ 528 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 529 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 530 531 /* Wait controller to be stable */ 532 udelay(50); 533 534 /* Start I2C transaction */ 535 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 536 temp |= I2CR_MSTA; 537 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 538 result = i2c_imx_bus_busy(i2c_imx, 1); 539 if (result) 540 return result; 541 i2c_imx->stopped = 0; 542 543 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 544 temp &= ~I2CR_DMAEN; 545 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 546 return result; 547 } 548 549 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 550 { 551 unsigned int temp = 0; 552 553 if (!i2c_imx->stopped) { 554 /* Stop I2C transaction */ 555 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 556 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 557 temp &= ~(I2CR_MSTA | I2CR_MTX); 558 if (i2c_imx->dma) 559 temp &= ~I2CR_DMAEN; 560 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 561 } 562 if (is_imx1_i2c(i2c_imx)) { 563 /* 564 * This delay caused by an i.MXL hardware bug. 565 * If no (or too short) delay, no "STOP" bit will be generated. 566 */ 567 udelay(i2c_imx->disable_delay); 568 } 569 570 if (!i2c_imx->stopped) { 571 i2c_imx_bus_busy(i2c_imx, 0); 572 i2c_imx->stopped = 1; 573 } 574 575 /* Disable I2C controller */ 576 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 577 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 578 clk_disable_unprepare(i2c_imx->clk); 579 } 580 581 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 582 { 583 struct imx_i2c_struct *i2c_imx = dev_id; 584 unsigned int temp; 585 586 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 587 if (temp & I2SR_IIF) { 588 /* save status register */ 589 i2c_imx->i2csr = temp; 590 temp &= ~I2SR_IIF; 591 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 592 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 593 wake_up(&i2c_imx->queue); 594 return IRQ_HANDLED; 595 } 596 597 return IRQ_NONE; 598 } 599 600 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 601 struct i2c_msg *msgs) 602 { 603 int result; 604 unsigned int temp = 0; 605 unsigned long orig_jiffies = jiffies; 606 struct imx_i2c_dma *dma = i2c_imx->dma; 607 struct device *dev = &i2c_imx->adapter.dev; 608 609 dma->chan_using = dma->chan_tx; 610 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 611 dma->dma_data_dir = DMA_TO_DEVICE; 612 dma->dma_len = msgs->len - 1; 613 result = i2c_imx_dma_xfer(i2c_imx, msgs); 614 if (result) 615 return result; 616 617 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 618 temp |= I2CR_DMAEN; 619 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 620 621 /* 622 * Write slave address. 623 * The first byte must be transmitted by the CPU. 624 */ 625 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 626 reinit_completion(&i2c_imx->dma->cmd_complete); 627 result = wait_for_completion_timeout( 628 &i2c_imx->dma->cmd_complete, 629 msecs_to_jiffies(DMA_TIMEOUT)); 630 if (result == 0) { 631 dmaengine_terminate_all(dma->chan_using); 632 return -ETIMEDOUT; 633 } 634 635 /* Waiting for transfer complete. */ 636 while (1) { 637 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 638 if (temp & I2SR_ICF) 639 break; 640 if (time_after(jiffies, orig_jiffies + 641 msecs_to_jiffies(DMA_TIMEOUT))) { 642 dev_dbg(dev, "<%s> Timeout\n", __func__); 643 return -ETIMEDOUT; 644 } 645 schedule(); 646 } 647 648 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 649 temp &= ~I2CR_DMAEN; 650 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 651 652 /* The last data byte must be transferred by the CPU. */ 653 imx_i2c_write_reg(msgs->buf[msgs->len-1], 654 i2c_imx, IMX_I2C_I2DR); 655 result = i2c_imx_trx_complete(i2c_imx); 656 if (result) 657 return result; 658 659 return i2c_imx_acked(i2c_imx); 660 } 661 662 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 663 struct i2c_msg *msgs, bool is_lastmsg) 664 { 665 int result; 666 unsigned int temp; 667 unsigned long orig_jiffies = jiffies; 668 struct imx_i2c_dma *dma = i2c_imx->dma; 669 struct device *dev = &i2c_imx->adapter.dev; 670 671 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 672 temp |= I2CR_DMAEN; 673 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 674 675 dma->chan_using = dma->chan_rx; 676 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 677 dma->dma_data_dir = DMA_FROM_DEVICE; 678 /* The last two data bytes must be transferred by the CPU. */ 679 dma->dma_len = msgs->len - 2; 680 result = i2c_imx_dma_xfer(i2c_imx, msgs); 681 if (result) 682 return result; 683 684 reinit_completion(&i2c_imx->dma->cmd_complete); 685 result = wait_for_completion_timeout( 686 &i2c_imx->dma->cmd_complete, 687 msecs_to_jiffies(DMA_TIMEOUT)); 688 if (result == 0) { 689 dmaengine_terminate_all(dma->chan_using); 690 return -ETIMEDOUT; 691 } 692 693 /* waiting for transfer complete. */ 694 while (1) { 695 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 696 if (temp & I2SR_ICF) 697 break; 698 if (time_after(jiffies, orig_jiffies + 699 msecs_to_jiffies(DMA_TIMEOUT))) { 700 dev_dbg(dev, "<%s> Timeout\n", __func__); 701 return -ETIMEDOUT; 702 } 703 schedule(); 704 } 705 706 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 707 temp &= ~I2CR_DMAEN; 708 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 709 710 /* read n-1 byte data */ 711 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 712 temp |= I2CR_TXAK; 713 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 714 715 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 716 /* read n byte data */ 717 result = i2c_imx_trx_complete(i2c_imx); 718 if (result) 719 return result; 720 721 if (is_lastmsg) { 722 /* 723 * It must generate STOP before read I2DR to prevent 724 * controller from generating another clock cycle 725 */ 726 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 727 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 728 temp &= ~(I2CR_MSTA | I2CR_MTX); 729 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 730 i2c_imx_bus_busy(i2c_imx, 0); 731 i2c_imx->stopped = 1; 732 } else { 733 /* 734 * For i2c master receiver repeat restart operation like: 735 * read -> repeat MSTA -> read/write 736 * The controller must set MTX before read the last byte in 737 * the first read operation, otherwise the first read cost 738 * one extra clock cycle. 739 */ 740 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 741 temp |= I2CR_MTX; 742 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 743 } 744 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 745 746 return 0; 747 } 748 749 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 750 { 751 int i, result; 752 753 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 754 __func__, msgs->addr << 1); 755 756 /* write slave address */ 757 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 758 result = i2c_imx_trx_complete(i2c_imx); 759 if (result) 760 return result; 761 result = i2c_imx_acked(i2c_imx); 762 if (result) 763 return result; 764 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 765 766 /* write data */ 767 for (i = 0; i < msgs->len; i++) { 768 dev_dbg(&i2c_imx->adapter.dev, 769 "<%s> write byte: B%d=0x%X\n", 770 __func__, i, msgs->buf[i]); 771 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 772 result = i2c_imx_trx_complete(i2c_imx); 773 if (result) 774 return result; 775 result = i2c_imx_acked(i2c_imx); 776 if (result) 777 return result; 778 } 779 return 0; 780 } 781 782 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 783 { 784 int i, result; 785 unsigned int temp; 786 int block_data = msgs->flags & I2C_M_RECV_LEN; 787 788 dev_dbg(&i2c_imx->adapter.dev, 789 "<%s> write slave address: addr=0x%x\n", 790 __func__, (msgs->addr << 1) | 0x01); 791 792 /* write slave address */ 793 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); 794 result = i2c_imx_trx_complete(i2c_imx); 795 if (result) 796 return result; 797 result = i2c_imx_acked(i2c_imx); 798 if (result) 799 return result; 800 801 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 802 803 /* setup bus to read data */ 804 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 805 temp &= ~I2CR_MTX; 806 807 /* 808 * Reset the I2CR_TXAK flag initially for SMBus block read since the 809 * length is unknown 810 */ 811 if ((msgs->len - 1) || block_data) 812 temp &= ~I2CR_TXAK; 813 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 814 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 815 816 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 817 818 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data) 819 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 820 821 /* read data */ 822 for (i = 0; i < msgs->len; i++) { 823 u8 len = 0; 824 825 result = i2c_imx_trx_complete(i2c_imx); 826 if (result) 827 return result; 828 /* 829 * First byte is the length of remaining packet 830 * in the SMBus block data read. Add it to 831 * msgs->len. 832 */ 833 if ((!i) && block_data) { 834 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 835 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 836 return -EPROTO; 837 dev_dbg(&i2c_imx->adapter.dev, 838 "<%s> read length: 0x%X\n", 839 __func__, len); 840 msgs->len += len; 841 } 842 if (i == (msgs->len - 1)) { 843 if (is_lastmsg) { 844 /* 845 * It must generate STOP before read I2DR to prevent 846 * controller from generating another clock cycle 847 */ 848 dev_dbg(&i2c_imx->adapter.dev, 849 "<%s> clear MSTA\n", __func__); 850 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 851 temp &= ~(I2CR_MSTA | I2CR_MTX); 852 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 853 i2c_imx_bus_busy(i2c_imx, 0); 854 i2c_imx->stopped = 1; 855 } else { 856 /* 857 * For i2c master receiver repeat restart operation like: 858 * read -> repeat MSTA -> read/write 859 * The controller must set MTX before read the last byte in 860 * the first read operation, otherwise the first read cost 861 * one extra clock cycle. 862 */ 863 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 864 temp |= I2CR_MTX; 865 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 866 } 867 } else if (i == (msgs->len - 2)) { 868 dev_dbg(&i2c_imx->adapter.dev, 869 "<%s> set TXAK\n", __func__); 870 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 871 temp |= I2CR_TXAK; 872 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 873 } 874 if ((!i) && block_data) 875 msgs->buf[0] = len; 876 else 877 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 878 dev_dbg(&i2c_imx->adapter.dev, 879 "<%s> read byte: B%d=0x%X\n", 880 __func__, i, msgs->buf[i]); 881 } 882 return 0; 883 } 884 885 static int i2c_imx_xfer(struct i2c_adapter *adapter, 886 struct i2c_msg *msgs, int num) 887 { 888 unsigned int i, temp; 889 int result; 890 bool is_lastmsg = false; 891 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 892 893 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 894 895 /* Start I2C transfer */ 896 result = i2c_imx_start(i2c_imx); 897 if (result) 898 goto fail0; 899 900 /* read/write data */ 901 for (i = 0; i < num; i++) { 902 if (i == num - 1) 903 is_lastmsg = true; 904 905 if (i) { 906 dev_dbg(&i2c_imx->adapter.dev, 907 "<%s> repeated start\n", __func__); 908 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 909 temp |= I2CR_RSTA; 910 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 911 result = i2c_imx_bus_busy(i2c_imx, 1); 912 if (result) 913 goto fail0; 914 } 915 dev_dbg(&i2c_imx->adapter.dev, 916 "<%s> transfer message: %d\n", __func__, i); 917 /* write/read data */ 918 #ifdef CONFIG_I2C_DEBUG_BUS 919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 920 dev_dbg(&i2c_imx->adapter.dev, 921 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 922 __func__, 923 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 924 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 925 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 926 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 927 dev_dbg(&i2c_imx->adapter.dev, 928 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 929 __func__, 930 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 931 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 932 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 933 (temp & I2SR_RXAK ? 1 : 0)); 934 #endif 935 if (msgs[i].flags & I2C_M_RD) 936 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 937 else { 938 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 939 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 940 else 941 result = i2c_imx_write(i2c_imx, &msgs[i]); 942 } 943 if (result) 944 goto fail0; 945 } 946 947 fail0: 948 /* Stop I2C transfer */ 949 i2c_imx_stop(i2c_imx); 950 951 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 952 (result < 0) ? "error" : "success msg", 953 (result < 0) ? result : num); 954 return (result < 0) ? result : num; 955 } 956 957 static u32 i2c_imx_func(struct i2c_adapter *adapter) 958 { 959 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 960 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 961 } 962 963 static struct i2c_algorithm i2c_imx_algo = { 964 .master_xfer = i2c_imx_xfer, 965 .functionality = i2c_imx_func, 966 }; 967 968 static int i2c_imx_probe(struct platform_device *pdev) 969 { 970 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 971 &pdev->dev); 972 struct imx_i2c_struct *i2c_imx; 973 struct resource *res; 974 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 975 void __iomem *base; 976 int irq, ret; 977 dma_addr_t phy_addr; 978 979 dev_dbg(&pdev->dev, "<%s>\n", __func__); 980 981 irq = platform_get_irq(pdev, 0); 982 if (irq < 0) { 983 dev_err(&pdev->dev, "can't get irq number\n"); 984 return irq; 985 } 986 987 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 988 base = devm_ioremap_resource(&pdev->dev, res); 989 if (IS_ERR(base)) 990 return PTR_ERR(base); 991 992 phy_addr = (dma_addr_t)res->start; 993 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 994 if (!i2c_imx) 995 return -ENOMEM; 996 997 if (of_id) 998 i2c_imx->hwdata = of_id->data; 999 else 1000 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1001 platform_get_device_id(pdev)->driver_data; 1002 1003 /* Setup i2c_imx driver structure */ 1004 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1005 i2c_imx->adapter.owner = THIS_MODULE; 1006 i2c_imx->adapter.algo = &i2c_imx_algo; 1007 i2c_imx->adapter.dev.parent = &pdev->dev; 1008 i2c_imx->adapter.nr = pdev->id; 1009 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1010 i2c_imx->base = base; 1011 1012 /* Get I2C clock */ 1013 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1014 if (IS_ERR(i2c_imx->clk)) { 1015 dev_err(&pdev->dev, "can't get I2C clock\n"); 1016 return PTR_ERR(i2c_imx->clk); 1017 } 1018 1019 ret = clk_prepare_enable(i2c_imx->clk); 1020 if (ret) { 1021 dev_err(&pdev->dev, "can't enable I2C clock\n"); 1022 return ret; 1023 } 1024 /* Request IRQ */ 1025 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, 1026 pdev->name, i2c_imx); 1027 if (ret) { 1028 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1029 goto clk_disable; 1030 } 1031 1032 /* Init queue */ 1033 init_waitqueue_head(&i2c_imx->queue); 1034 1035 /* Set up adapter data */ 1036 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1037 1038 /* Set up clock divider */ 1039 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 1040 ret = of_property_read_u32(pdev->dev.of_node, 1041 "clock-frequency", &i2c_imx->bitrate); 1042 if (ret < 0 && pdata && pdata->bitrate) 1043 i2c_imx->bitrate = pdata->bitrate; 1044 1045 /* Set up chip registers to defaults */ 1046 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1047 i2c_imx, IMX_I2C_I2CR); 1048 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1049 1050 /* Add I2C adapter */ 1051 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1052 if (ret < 0) { 1053 dev_err(&pdev->dev, "registration failed\n"); 1054 goto clk_disable; 1055 } 1056 1057 /* Set up platform driver data */ 1058 platform_set_drvdata(pdev, i2c_imx); 1059 clk_disable_unprepare(i2c_imx->clk); 1060 1061 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1062 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1063 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1064 i2c_imx->adapter.name); 1065 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1066 1067 /* Init DMA config if supported */ 1068 i2c_imx_dma_request(i2c_imx, phy_addr); 1069 1070 return 0; /* Return OK */ 1071 1072 clk_disable: 1073 clk_disable_unprepare(i2c_imx->clk); 1074 return ret; 1075 } 1076 1077 static int i2c_imx_remove(struct platform_device *pdev) 1078 { 1079 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1080 1081 /* remove adapter */ 1082 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1083 i2c_del_adapter(&i2c_imx->adapter); 1084 1085 if (i2c_imx->dma) 1086 i2c_imx_dma_free(i2c_imx); 1087 1088 /* setup chip registers to defaults */ 1089 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1090 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1091 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1092 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1093 1094 return 0; 1095 } 1096 1097 static struct platform_driver i2c_imx_driver = { 1098 .probe = i2c_imx_probe, 1099 .remove = i2c_imx_remove, 1100 .driver = { 1101 .name = DRIVER_NAME, 1102 .of_match_table = i2c_imx_dt_ids, 1103 }, 1104 .id_table = imx_i2c_devtype, 1105 }; 1106 1107 static int __init i2c_adap_imx_init(void) 1108 { 1109 return platform_driver_register(&i2c_imx_driver); 1110 } 1111 subsys_initcall(i2c_adap_imx_init); 1112 1113 static void __exit i2c_adap_imx_exit(void) 1114 { 1115 platform_driver_unregister(&i2c_imx_driver); 1116 } 1117 module_exit(i2c_adap_imx_exit); 1118 1119 MODULE_LICENSE("GPL"); 1120 MODULE_AUTHOR("Darius Augulis"); 1121 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1122 MODULE_ALIAS("platform:" DRIVER_NAME); 1123