1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/of_dma.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/platform_data/i2c-imx.h> 46 #include <linux/platform_device.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/sched.h> 49 #include <linux/slab.h> 50 51 /* This will be the driver name the kernel reports */ 52 #define DRIVER_NAME "imx-i2c" 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 /* 78 * All of the layerscape series SoCs support IBIC register. 79 */ 80 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 81 82 #define IMX_I2C_REGSHIFT 2 83 #define VF610_I2C_REGSHIFT 0 84 85 /* Bits of IMX I2C registers */ 86 #define I2SR_RXAK 0x01 87 #define I2SR_IIF 0x02 88 #define I2SR_SRW 0x04 89 #define I2SR_IAL 0x10 90 #define I2SR_IBB 0x20 91 #define I2SR_IAAS 0x40 92 #define I2SR_ICF 0x80 93 #define I2CR_DMAEN 0x02 94 #define I2CR_RSTA 0x04 95 #define I2CR_TXAK 0x08 96 #define I2CR_MTX 0x10 97 #define I2CR_MSTA 0x20 98 #define I2CR_IIEN 0x40 99 #define I2CR_IEN 0x80 100 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 101 102 /* register bits different operating codes definition: 103 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 104 * - write zero to clear(w0c) INT flag on i.MX, 105 * - but write one to clear(w1c) INT flag on Vybrid. 106 * 2) I2CR: I2C module enable operation also differ between SoCs: 107 * - set I2CR_IEN bit enable the module on i.MX, 108 * - but clear I2CR_IEN bit enable the module on Vybrid. 109 */ 110 #define I2SR_CLR_OPCODE_W0C 0x0 111 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 112 #define I2CR_IEN_OPCODE_0 0x0 113 #define I2CR_IEN_OPCODE_1 I2CR_IEN 114 115 #define I2C_PM_TIMEOUT 10 /* ms */ 116 117 /* 118 * sorted list of clock divider, register value pairs 119 * taken from table 26-5, p.26-9, Freescale i.MX 120 * Integrated Portable System Processor Reference Manual 121 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 122 * 123 * Duplicated divider values removed from list 124 */ 125 struct imx_i2c_clk_pair { 126 u16 div; 127 u16 val; 128 }; 129 130 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 131 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 132 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 133 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 134 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 135 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 136 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 137 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 138 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 139 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 140 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 141 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 142 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 143 { 3072, 0x1E }, { 3840, 0x1F } 144 }; 145 146 /* Vybrid VF610 clock divider, register value pairs */ 147 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 148 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 149 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 150 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 151 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 152 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 153 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 154 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 155 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 156 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 157 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 158 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 159 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 160 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 161 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 162 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 163 }; 164 165 enum imx_i2c_type { 166 IMX1_I2C, 167 IMX21_I2C, 168 VF610_I2C, 169 }; 170 171 struct imx_i2c_hwdata { 172 enum imx_i2c_type devtype; 173 unsigned regshift; 174 struct imx_i2c_clk_pair *clk_div; 175 unsigned ndivs; 176 unsigned i2sr_clr_opcode; 177 unsigned i2cr_ien_opcode; 178 }; 179 180 struct imx_i2c_dma { 181 struct dma_chan *chan_tx; 182 struct dma_chan *chan_rx; 183 struct dma_chan *chan_using; 184 struct completion cmd_complete; 185 dma_addr_t dma_buf; 186 unsigned int dma_len; 187 enum dma_transfer_direction dma_transfer_dir; 188 enum dma_data_direction dma_data_dir; 189 }; 190 191 struct imx_i2c_struct { 192 struct i2c_adapter adapter; 193 struct clk *clk; 194 struct notifier_block clk_change_nb; 195 void __iomem *base; 196 wait_queue_head_t queue; 197 unsigned long i2csr; 198 unsigned int disable_delay; 199 int stopped; 200 unsigned int ifdr; /* IMX_I2C_IFDR */ 201 unsigned int cur_clk; 202 unsigned int bitrate; 203 const struct imx_i2c_hwdata *hwdata; 204 struct i2c_bus_recovery_info rinfo; 205 206 struct pinctrl *pinctrl; 207 struct pinctrl_state *pinctrl_pins_default; 208 struct pinctrl_state *pinctrl_pins_gpio; 209 210 struct imx_i2c_dma *dma; 211 struct i2c_client *slave; 212 enum i2c_slave_event last_slave_event; 213 }; 214 215 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 216 .devtype = IMX1_I2C, 217 .regshift = IMX_I2C_REGSHIFT, 218 .clk_div = imx_i2c_clk_div, 219 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 220 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 221 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 222 223 }; 224 225 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 226 .devtype = IMX21_I2C, 227 .regshift = IMX_I2C_REGSHIFT, 228 .clk_div = imx_i2c_clk_div, 229 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 230 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 231 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 232 233 }; 234 235 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 236 .devtype = VF610_I2C, 237 .regshift = VF610_I2C_REGSHIFT, 238 .clk_div = vf610_i2c_clk_div, 239 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 240 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 241 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 242 243 }; 244 245 static const struct platform_device_id imx_i2c_devtype[] = { 246 { 247 .name = "imx1-i2c", 248 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 249 }, { 250 .name = "imx21-i2c", 251 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 252 }, { 253 /* sentinel */ 254 } 255 }; 256 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 257 258 static const struct of_device_id i2c_imx_dt_ids[] = { 259 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 260 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 261 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 262 { /* sentinel */ } 263 }; 264 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 265 266 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 267 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 268 { } 269 }; 270 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 271 272 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 273 { 274 return i2c_imx->hwdata->devtype == IMX1_I2C; 275 } 276 277 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 278 { 279 return i2c_imx->hwdata->devtype == VF610_I2C; 280 } 281 282 static inline void imx_i2c_write_reg(unsigned int val, 283 struct imx_i2c_struct *i2c_imx, unsigned int reg) 284 { 285 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 286 } 287 288 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 289 unsigned int reg) 290 { 291 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 292 } 293 294 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 295 { 296 unsigned int temp; 297 298 /* 299 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 300 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 301 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 302 */ 303 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 304 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 305 } 306 307 /* Set up i2c controller register and i2c status register to default value. */ 308 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 309 { 310 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 311 i2c_imx, IMX_I2C_I2CR); 312 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 313 } 314 315 /* Functions for DMA support */ 316 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 317 dma_addr_t phy_addr) 318 { 319 struct imx_i2c_dma *dma; 320 struct dma_slave_config dma_sconfig; 321 struct device *dev = &i2c_imx->adapter.dev; 322 int ret; 323 324 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 325 if (!dma) 326 return; 327 328 dma->chan_tx = dma_request_chan(dev, "tx"); 329 if (IS_ERR(dma->chan_tx)) { 330 ret = PTR_ERR(dma->chan_tx); 331 if (ret != -ENODEV && ret != -EPROBE_DEFER) 332 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 333 goto fail_al; 334 } 335 336 dma_sconfig.dst_addr = phy_addr + 337 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 338 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 339 dma_sconfig.dst_maxburst = 1; 340 dma_sconfig.direction = DMA_MEM_TO_DEV; 341 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 342 if (ret < 0) { 343 dev_err(dev, "can't configure tx channel (%d)\n", ret); 344 goto fail_tx; 345 } 346 347 dma->chan_rx = dma_request_chan(dev, "rx"); 348 if (IS_ERR(dma->chan_rx)) { 349 ret = PTR_ERR(dma->chan_rx); 350 if (ret != -ENODEV && ret != -EPROBE_DEFER) 351 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 352 goto fail_tx; 353 } 354 355 dma_sconfig.src_addr = phy_addr + 356 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 357 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 358 dma_sconfig.src_maxburst = 1; 359 dma_sconfig.direction = DMA_DEV_TO_MEM; 360 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 361 if (ret < 0) { 362 dev_err(dev, "can't configure rx channel (%d)\n", ret); 363 goto fail_rx; 364 } 365 366 i2c_imx->dma = dma; 367 init_completion(&dma->cmd_complete); 368 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 369 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 370 371 return; 372 373 fail_rx: 374 dma_release_channel(dma->chan_rx); 375 fail_tx: 376 dma_release_channel(dma->chan_tx); 377 fail_al: 378 devm_kfree(dev, dma); 379 } 380 381 static void i2c_imx_dma_callback(void *arg) 382 { 383 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 384 struct imx_i2c_dma *dma = i2c_imx->dma; 385 386 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 387 dma->dma_len, dma->dma_data_dir); 388 complete(&dma->cmd_complete); 389 } 390 391 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 392 struct i2c_msg *msgs) 393 { 394 struct imx_i2c_dma *dma = i2c_imx->dma; 395 struct dma_async_tx_descriptor *txdesc; 396 struct device *dev = &i2c_imx->adapter.dev; 397 struct device *chan_dev = dma->chan_using->device->dev; 398 399 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 400 dma->dma_len, dma->dma_data_dir); 401 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 402 dev_err(dev, "DMA mapping failed\n"); 403 goto err_map; 404 } 405 406 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 407 dma->dma_len, dma->dma_transfer_dir, 408 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 409 if (!txdesc) { 410 dev_err(dev, "Not able to get desc for DMA xfer\n"); 411 goto err_desc; 412 } 413 414 reinit_completion(&dma->cmd_complete); 415 txdesc->callback = i2c_imx_dma_callback; 416 txdesc->callback_param = i2c_imx; 417 if (dma_submit_error(dmaengine_submit(txdesc))) { 418 dev_err(dev, "DMA submit failed\n"); 419 goto err_submit; 420 } 421 422 dma_async_issue_pending(dma->chan_using); 423 return 0; 424 425 err_submit: 426 dmaengine_terminate_all(dma->chan_using); 427 err_desc: 428 dma_unmap_single(chan_dev, dma->dma_buf, 429 dma->dma_len, dma->dma_data_dir); 430 err_map: 431 return -EINVAL; 432 } 433 434 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 435 { 436 struct imx_i2c_dma *dma = i2c_imx->dma; 437 438 dma->dma_buf = 0; 439 dma->dma_len = 0; 440 441 dma_release_channel(dma->chan_tx); 442 dma->chan_tx = NULL; 443 444 dma_release_channel(dma->chan_rx); 445 dma->chan_rx = NULL; 446 447 dma->chan_using = NULL; 448 } 449 450 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 451 { 452 unsigned long orig_jiffies = jiffies; 453 unsigned int temp; 454 455 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 456 457 while (1) { 458 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 459 460 /* check for arbitration lost */ 461 if (temp & I2SR_IAL) { 462 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 463 return -EAGAIN; 464 } 465 466 if (for_busy && (temp & I2SR_IBB)) { 467 i2c_imx->stopped = 0; 468 break; 469 } 470 if (!for_busy && !(temp & I2SR_IBB)) { 471 i2c_imx->stopped = 1; 472 break; 473 } 474 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 475 dev_dbg(&i2c_imx->adapter.dev, 476 "<%s> I2C bus is busy\n", __func__); 477 return -ETIMEDOUT; 478 } 479 if (atomic) 480 udelay(100); 481 else 482 schedule(); 483 } 484 485 return 0; 486 } 487 488 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 489 { 490 if (atomic) { 491 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 492 unsigned int regval; 493 494 /* 495 * The formula for the poll timeout is documented in the RM 496 * Rev.5 on page 1878: 497 * T_min = 10/F_scl 498 * Set the value hard as it is done for the non-atomic use-case. 499 * Use 10 kHz for the calculation since this is the minimum 500 * allowed SMBus frequency. Also add an offset of 100us since it 501 * turned out that the I2SR_IIF bit isn't set correctly within 502 * the minimum timeout in polling mode. 503 */ 504 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 505 i2c_imx->i2csr = regval; 506 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 507 } else { 508 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 509 } 510 511 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 512 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 513 return -ETIMEDOUT; 514 } 515 516 /* check for arbitration lost */ 517 if (i2c_imx->i2csr & I2SR_IAL) { 518 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 519 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 520 521 i2c_imx->i2csr = 0; 522 return -EAGAIN; 523 } 524 525 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 526 i2c_imx->i2csr = 0; 527 return 0; 528 } 529 530 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 531 { 532 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 533 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 534 return -ENXIO; /* No ACK */ 535 } 536 537 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 538 return 0; 539 } 540 541 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 542 unsigned int i2c_clk_rate) 543 { 544 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 545 unsigned int div; 546 int i; 547 548 /* Divider value calculation */ 549 if (i2c_imx->cur_clk == i2c_clk_rate) 550 return; 551 552 i2c_imx->cur_clk = i2c_clk_rate; 553 554 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 555 if (div < i2c_clk_div[0].div) 556 i = 0; 557 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 558 i = i2c_imx->hwdata->ndivs - 1; 559 else 560 for (i = 0; i2c_clk_div[i].div < div; i++) 561 ; 562 563 /* Store divider value */ 564 i2c_imx->ifdr = i2c_clk_div[i].val; 565 566 /* 567 * There dummy delay is calculated. 568 * It should be about one I2C clock period long. 569 * This delay is used in I2C bus disable function 570 * to fix chip hardware bug. 571 */ 572 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 573 i2c_clk_rate / 2); 574 575 #ifdef CONFIG_I2C_DEBUG_BUS 576 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 577 i2c_clk_rate, div); 578 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 579 i2c_clk_div[i].val, i2c_clk_div[i].div); 580 #endif 581 } 582 583 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 584 unsigned long action, void *data) 585 { 586 struct clk_notifier_data *ndata = data; 587 struct imx_i2c_struct *i2c_imx = container_of(nb, 588 struct imx_i2c_struct, 589 clk_change_nb); 590 591 if (action & POST_RATE_CHANGE) 592 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 593 594 return NOTIFY_OK; 595 } 596 597 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 598 { 599 unsigned int temp = 0; 600 int result; 601 602 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 603 604 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 605 /* Enable I2C controller */ 606 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 607 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 608 609 /* Wait controller to be stable */ 610 if (atomic) 611 udelay(50); 612 else 613 usleep_range(50, 150); 614 615 /* Start I2C transaction */ 616 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 617 temp |= I2CR_MSTA; 618 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 619 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 620 if (result) 621 return result; 622 623 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 624 if (atomic) 625 temp &= ~I2CR_IIEN; /* Disable interrupt */ 626 627 temp &= ~I2CR_DMAEN; 628 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 629 return result; 630 } 631 632 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 633 { 634 unsigned int temp = 0; 635 636 if (!i2c_imx->stopped) { 637 /* Stop I2C transaction */ 638 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 639 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 640 if (!(temp & I2CR_MSTA)) 641 i2c_imx->stopped = 1; 642 temp &= ~(I2CR_MSTA | I2CR_MTX); 643 if (i2c_imx->dma) 644 temp &= ~I2CR_DMAEN; 645 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 646 } 647 if (is_imx1_i2c(i2c_imx)) { 648 /* 649 * This delay caused by an i.MXL hardware bug. 650 * If no (or too short) delay, no "STOP" bit will be generated. 651 */ 652 udelay(i2c_imx->disable_delay); 653 } 654 655 if (!i2c_imx->stopped) 656 i2c_imx_bus_busy(i2c_imx, 0, atomic); 657 658 /* Disable I2C controller */ 659 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 660 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 661 } 662 663 /* 664 * Enable bus idle interrupts 665 * Note: IBIC register will be cleared after disabled i2c module. 666 * All of layerscape series SoCs support IBIC register. 667 */ 668 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 669 { 670 if (is_vf610_i2c(i2c_imx)) { 671 unsigned int temp; 672 673 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 674 temp |= IBIC_BIIE; 675 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 676 } 677 } 678 679 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 680 enum i2c_slave_event event, u8 *val) 681 { 682 i2c_slave_event(i2c_imx->slave, event, val); 683 i2c_imx->last_slave_event = event; 684 } 685 686 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 687 { 688 u8 val; 689 690 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 691 switch (i2c_imx->last_slave_event) { 692 case I2C_SLAVE_READ_REQUESTED: 693 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 694 &val); 695 break; 696 697 case I2C_SLAVE_WRITE_REQUESTED: 698 case I2C_SLAVE_READ_PROCESSED: 699 case I2C_SLAVE_WRITE_RECEIVED: 700 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 701 break; 702 703 case I2C_SLAVE_STOP: 704 break; 705 } 706 } 707 } 708 709 static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, 710 unsigned int status, unsigned int ctl) 711 { 712 u8 value; 713 714 if (status & I2SR_IAL) { /* Arbitration lost */ 715 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 716 if (!(status & I2SR_IAAS)) 717 return IRQ_HANDLED; 718 } 719 720 if (status & I2SR_IAAS) { /* Addressed as a slave */ 721 i2c_imx_slave_finish_op(i2c_imx); 722 if (status & I2SR_SRW) { /* Master wants to read from us*/ 723 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 724 i2c_imx_slave_event(i2c_imx, 725 I2C_SLAVE_READ_REQUESTED, &value); 726 727 /* Slave transmit */ 728 ctl |= I2CR_MTX; 729 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 730 731 /* Send data */ 732 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 733 } else { /* Master wants to write to us */ 734 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 735 i2c_imx_slave_event(i2c_imx, 736 I2C_SLAVE_WRITE_REQUESTED, &value); 737 738 /* Slave receive */ 739 ctl &= ~I2CR_MTX; 740 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 741 /* Dummy read */ 742 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 743 } 744 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 745 if (status & I2SR_IBB) { /* No STOP signal detected */ 746 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 747 i2c_imx_slave_event(i2c_imx, 748 I2C_SLAVE_WRITE_RECEIVED, &value); 749 } else { /* STOP signal is detected */ 750 dev_dbg(&i2c_imx->adapter.dev, 751 "STOP signal detected"); 752 i2c_imx_slave_event(i2c_imx, 753 I2C_SLAVE_STOP, &value); 754 } 755 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 756 ctl |= I2CR_MTX; 757 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 758 759 i2c_imx_slave_event(i2c_imx, 760 I2C_SLAVE_READ_PROCESSED, &value); 761 762 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 763 } else { /* Transmit mode received NAK */ 764 ctl &= ~I2CR_MTX; 765 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 766 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 767 } 768 769 return IRQ_HANDLED; 770 } 771 772 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 773 { 774 int temp; 775 776 /* Set slave addr. */ 777 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 778 779 i2c_imx_reset_regs(i2c_imx); 780 781 /* Enable module */ 782 temp = i2c_imx->hwdata->i2cr_ien_opcode; 783 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 784 785 /* Enable interrupt from i2c module */ 786 temp |= I2CR_IIEN; 787 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 788 789 i2c_imx_enable_bus_idle(i2c_imx); 790 } 791 792 static int i2c_imx_reg_slave(struct i2c_client *client) 793 { 794 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 795 int ret; 796 797 if (i2c_imx->slave) 798 return -EBUSY; 799 800 i2c_imx->slave = client; 801 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 802 803 /* Resume */ 804 ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 805 if (ret < 0) { 806 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 807 return ret; 808 } 809 810 i2c_imx_slave_init(i2c_imx); 811 812 return 0; 813 } 814 815 static int i2c_imx_unreg_slave(struct i2c_client *client) 816 { 817 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 818 int ret; 819 820 if (!i2c_imx->slave) 821 return -EINVAL; 822 823 /* Reset slave address. */ 824 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 825 826 i2c_imx_reset_regs(i2c_imx); 827 828 i2c_imx->slave = NULL; 829 830 /* Suspend */ 831 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 832 if (ret < 0) 833 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 834 835 return ret; 836 } 837 838 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 839 { 840 /* save status register */ 841 i2c_imx->i2csr = status; 842 wake_up(&i2c_imx->queue); 843 844 return IRQ_HANDLED; 845 } 846 847 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 848 { 849 struct imx_i2c_struct *i2c_imx = dev_id; 850 unsigned int ctl, status; 851 852 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 853 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 854 855 if (status & I2SR_IIF) { 856 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 857 if (i2c_imx->slave) { 858 if (!(ctl & I2CR_MSTA)) { 859 return i2c_imx_slave_isr(i2c_imx, status, ctl); 860 } else if (i2c_imx->last_slave_event != 861 I2C_SLAVE_STOP) { 862 i2c_imx_slave_finish_op(i2c_imx); 863 } 864 } 865 return i2c_imx_master_isr(i2c_imx, status); 866 } 867 868 return IRQ_NONE; 869 } 870 871 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 872 struct i2c_msg *msgs) 873 { 874 int result; 875 unsigned long time_left; 876 unsigned int temp = 0; 877 unsigned long orig_jiffies = jiffies; 878 struct imx_i2c_dma *dma = i2c_imx->dma; 879 struct device *dev = &i2c_imx->adapter.dev; 880 881 dma->chan_using = dma->chan_tx; 882 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 883 dma->dma_data_dir = DMA_TO_DEVICE; 884 dma->dma_len = msgs->len - 1; 885 result = i2c_imx_dma_xfer(i2c_imx, msgs); 886 if (result) 887 return result; 888 889 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 890 temp |= I2CR_DMAEN; 891 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 892 893 /* 894 * Write slave address. 895 * The first byte must be transmitted by the CPU. 896 */ 897 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 898 time_left = wait_for_completion_timeout( 899 &i2c_imx->dma->cmd_complete, 900 msecs_to_jiffies(DMA_TIMEOUT)); 901 if (time_left == 0) { 902 dmaengine_terminate_all(dma->chan_using); 903 return -ETIMEDOUT; 904 } 905 906 /* Waiting for transfer complete. */ 907 while (1) { 908 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 909 if (temp & I2SR_ICF) 910 break; 911 if (time_after(jiffies, orig_jiffies + 912 msecs_to_jiffies(DMA_TIMEOUT))) { 913 dev_dbg(dev, "<%s> Timeout\n", __func__); 914 return -ETIMEDOUT; 915 } 916 schedule(); 917 } 918 919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 920 temp &= ~I2CR_DMAEN; 921 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 922 923 /* The last data byte must be transferred by the CPU. */ 924 imx_i2c_write_reg(msgs->buf[msgs->len-1], 925 i2c_imx, IMX_I2C_I2DR); 926 result = i2c_imx_trx_complete(i2c_imx, false); 927 if (result) 928 return result; 929 930 return i2c_imx_acked(i2c_imx); 931 } 932 933 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 934 struct i2c_msg *msgs, bool is_lastmsg) 935 { 936 int result; 937 unsigned long time_left; 938 unsigned int temp; 939 unsigned long orig_jiffies = jiffies; 940 struct imx_i2c_dma *dma = i2c_imx->dma; 941 struct device *dev = &i2c_imx->adapter.dev; 942 943 944 dma->chan_using = dma->chan_rx; 945 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 946 dma->dma_data_dir = DMA_FROM_DEVICE; 947 /* The last two data bytes must be transferred by the CPU. */ 948 dma->dma_len = msgs->len - 2; 949 result = i2c_imx_dma_xfer(i2c_imx, msgs); 950 if (result) 951 return result; 952 953 time_left = wait_for_completion_timeout( 954 &i2c_imx->dma->cmd_complete, 955 msecs_to_jiffies(DMA_TIMEOUT)); 956 if (time_left == 0) { 957 dmaengine_terminate_all(dma->chan_using); 958 return -ETIMEDOUT; 959 } 960 961 /* waiting for transfer complete. */ 962 while (1) { 963 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 964 if (temp & I2SR_ICF) 965 break; 966 if (time_after(jiffies, orig_jiffies + 967 msecs_to_jiffies(DMA_TIMEOUT))) { 968 dev_dbg(dev, "<%s> Timeout\n", __func__); 969 return -ETIMEDOUT; 970 } 971 schedule(); 972 } 973 974 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 975 temp &= ~I2CR_DMAEN; 976 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 977 978 /* read n-1 byte data */ 979 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 980 temp |= I2CR_TXAK; 981 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 982 983 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 984 /* read n byte data */ 985 result = i2c_imx_trx_complete(i2c_imx, false); 986 if (result) 987 return result; 988 989 if (is_lastmsg) { 990 /* 991 * It must generate STOP before read I2DR to prevent 992 * controller from generating another clock cycle 993 */ 994 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 995 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 996 if (!(temp & I2CR_MSTA)) 997 i2c_imx->stopped = 1; 998 temp &= ~(I2CR_MSTA | I2CR_MTX); 999 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1000 if (!i2c_imx->stopped) 1001 i2c_imx_bus_busy(i2c_imx, 0, false); 1002 } else { 1003 /* 1004 * For i2c master receiver repeat restart operation like: 1005 * read -> repeat MSTA -> read/write 1006 * The controller must set MTX before read the last byte in 1007 * the first read operation, otherwise the first read cost 1008 * one extra clock cycle. 1009 */ 1010 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1011 temp |= I2CR_MTX; 1012 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1013 } 1014 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1015 1016 return 0; 1017 } 1018 1019 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1020 bool atomic) 1021 { 1022 int i, result; 1023 1024 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1025 __func__, i2c_8bit_addr_from_msg(msgs)); 1026 1027 /* write slave address */ 1028 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1029 result = i2c_imx_trx_complete(i2c_imx, atomic); 1030 if (result) 1031 return result; 1032 result = i2c_imx_acked(i2c_imx); 1033 if (result) 1034 return result; 1035 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1036 1037 /* write data */ 1038 for (i = 0; i < msgs->len; i++) { 1039 dev_dbg(&i2c_imx->adapter.dev, 1040 "<%s> write byte: B%d=0x%X\n", 1041 __func__, i, msgs->buf[i]); 1042 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1043 result = i2c_imx_trx_complete(i2c_imx, atomic); 1044 if (result) 1045 return result; 1046 result = i2c_imx_acked(i2c_imx); 1047 if (result) 1048 return result; 1049 } 1050 return 0; 1051 } 1052 1053 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1054 bool is_lastmsg, bool atomic) 1055 { 1056 int i, result; 1057 unsigned int temp; 1058 int block_data = msgs->flags & I2C_M_RECV_LEN; 1059 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 1060 1061 dev_dbg(&i2c_imx->adapter.dev, 1062 "<%s> write slave address: addr=0x%x\n", 1063 __func__, i2c_8bit_addr_from_msg(msgs)); 1064 1065 /* write slave address */ 1066 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1067 result = i2c_imx_trx_complete(i2c_imx, atomic); 1068 if (result) 1069 return result; 1070 result = i2c_imx_acked(i2c_imx); 1071 if (result) 1072 return result; 1073 1074 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1075 1076 /* setup bus to read data */ 1077 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1078 temp &= ~I2CR_MTX; 1079 1080 /* 1081 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1082 * length is unknown 1083 */ 1084 if ((msgs->len - 1) || block_data) 1085 temp &= ~I2CR_TXAK; 1086 if (use_dma) 1087 temp |= I2CR_DMAEN; 1088 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1089 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1090 1091 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1092 1093 if (use_dma) 1094 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 1095 1096 /* read data */ 1097 for (i = 0; i < msgs->len; i++) { 1098 u8 len = 0; 1099 1100 result = i2c_imx_trx_complete(i2c_imx, atomic); 1101 if (result) 1102 return result; 1103 /* 1104 * First byte is the length of remaining packet 1105 * in the SMBus block data read. Add it to 1106 * msgs->len. 1107 */ 1108 if ((!i) && block_data) { 1109 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1110 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1111 return -EPROTO; 1112 dev_dbg(&i2c_imx->adapter.dev, 1113 "<%s> read length: 0x%X\n", 1114 __func__, len); 1115 msgs->len += len; 1116 } 1117 if (i == (msgs->len - 1)) { 1118 if (is_lastmsg) { 1119 /* 1120 * It must generate STOP before read I2DR to prevent 1121 * controller from generating another clock cycle 1122 */ 1123 dev_dbg(&i2c_imx->adapter.dev, 1124 "<%s> clear MSTA\n", __func__); 1125 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1126 if (!(temp & I2CR_MSTA)) 1127 i2c_imx->stopped = 1; 1128 temp &= ~(I2CR_MSTA | I2CR_MTX); 1129 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1130 if (!i2c_imx->stopped) 1131 i2c_imx_bus_busy(i2c_imx, 0, atomic); 1132 } else { 1133 /* 1134 * For i2c master receiver repeat restart operation like: 1135 * read -> repeat MSTA -> read/write 1136 * The controller must set MTX before read the last byte in 1137 * the first read operation, otherwise the first read cost 1138 * one extra clock cycle. 1139 */ 1140 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1141 temp |= I2CR_MTX; 1142 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1143 } 1144 } else if (i == (msgs->len - 2)) { 1145 dev_dbg(&i2c_imx->adapter.dev, 1146 "<%s> set TXAK\n", __func__); 1147 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1148 temp |= I2CR_TXAK; 1149 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1150 } 1151 if ((!i) && block_data) 1152 msgs->buf[0] = len; 1153 else 1154 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1155 dev_dbg(&i2c_imx->adapter.dev, 1156 "<%s> read byte: B%d=0x%X\n", 1157 __func__, i, msgs->buf[i]); 1158 } 1159 return 0; 1160 } 1161 1162 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1163 struct i2c_msg *msgs, int num, bool atomic) 1164 { 1165 unsigned int i, temp; 1166 int result; 1167 bool is_lastmsg = false; 1168 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1169 1170 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 1171 1172 /* Start I2C transfer */ 1173 result = i2c_imx_start(i2c_imx, atomic); 1174 if (result) { 1175 /* 1176 * Bus recovery uses gpiod_get_value_cansleep() which is not 1177 * allowed within atomic context. 1178 */ 1179 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1180 i2c_recover_bus(&i2c_imx->adapter); 1181 result = i2c_imx_start(i2c_imx, atomic); 1182 } 1183 } 1184 1185 if (result) 1186 goto fail0; 1187 1188 /* read/write data */ 1189 for (i = 0; i < num; i++) { 1190 if (i == num - 1) 1191 is_lastmsg = true; 1192 1193 if (i) { 1194 dev_dbg(&i2c_imx->adapter.dev, 1195 "<%s> repeated start\n", __func__); 1196 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1197 temp |= I2CR_RSTA; 1198 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1199 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1200 if (result) 1201 goto fail0; 1202 } 1203 dev_dbg(&i2c_imx->adapter.dev, 1204 "<%s> transfer message: %d\n", __func__, i); 1205 /* write/read data */ 1206 #ifdef CONFIG_I2C_DEBUG_BUS 1207 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1208 dev_dbg(&i2c_imx->adapter.dev, 1209 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1210 __func__, 1211 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1212 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1213 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1214 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1215 dev_dbg(&i2c_imx->adapter.dev, 1216 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1217 __func__, 1218 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1219 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1220 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1221 (temp & I2SR_RXAK ? 1 : 0)); 1222 #endif 1223 if (msgs[i].flags & I2C_M_RD) { 1224 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1225 } else { 1226 if (!atomic && 1227 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 1228 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1229 else 1230 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1231 } 1232 if (result) 1233 goto fail0; 1234 } 1235 1236 fail0: 1237 /* Stop I2C transfer */ 1238 i2c_imx_stop(i2c_imx, atomic); 1239 1240 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1241 (result < 0) ? "error" : "success msg", 1242 (result < 0) ? result : num); 1243 /* After data is transferred, switch to slave mode(as a receiver) */ 1244 if (i2c_imx->slave) 1245 i2c_imx_slave_init(i2c_imx); 1246 1247 return (result < 0) ? result : num; 1248 } 1249 1250 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1251 struct i2c_msg *msgs, int num) 1252 { 1253 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1254 int result; 1255 1256 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 1257 if (result < 0) 1258 return result; 1259 1260 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1261 1262 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1263 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1264 1265 return result; 1266 } 1267 1268 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1269 struct i2c_msg *msgs, int num) 1270 { 1271 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1272 int result; 1273 1274 result = clk_enable(i2c_imx->clk); 1275 if (result) 1276 return result; 1277 1278 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1279 1280 clk_disable(i2c_imx->clk); 1281 1282 return result; 1283 } 1284 1285 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1286 { 1287 struct imx_i2c_struct *i2c_imx; 1288 1289 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1290 1291 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1292 } 1293 1294 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1295 { 1296 struct imx_i2c_struct *i2c_imx; 1297 1298 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1299 1300 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1301 } 1302 1303 /* 1304 * We switch SCL and SDA to their GPIO function and do some bitbanging 1305 * for bus recovery. These alternative pinmux settings can be 1306 * described in the device tree by a separate pinctrl state "gpio". If 1307 * this is missing this is not a big problem, the only implication is 1308 * that we can't do bus recovery. 1309 */ 1310 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1311 struct platform_device *pdev) 1312 { 1313 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1314 1315 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1316 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1317 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1318 return PTR_ERR(i2c_imx->pinctrl); 1319 } 1320 1321 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1322 PINCTRL_STATE_DEFAULT); 1323 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1324 "gpio"); 1325 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1326 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1327 1328 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1329 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1330 return -EPROBE_DEFER; 1331 } else if (IS_ERR(rinfo->sda_gpiod) || 1332 IS_ERR(rinfo->scl_gpiod) || 1333 IS_ERR(i2c_imx->pinctrl_pins_default) || 1334 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1335 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1336 return 0; 1337 } 1338 1339 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1340 rinfo->sda_gpiod ? ",sda" : ""); 1341 1342 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1343 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1344 rinfo->recover_bus = i2c_generic_scl_recovery; 1345 i2c_imx->adapter.bus_recovery_info = rinfo; 1346 1347 return 0; 1348 } 1349 1350 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1351 { 1352 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1353 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1354 } 1355 1356 static const struct i2c_algorithm i2c_imx_algo = { 1357 .master_xfer = i2c_imx_xfer, 1358 .master_xfer_atomic = i2c_imx_xfer_atomic, 1359 .functionality = i2c_imx_func, 1360 .reg_slave = i2c_imx_reg_slave, 1361 .unreg_slave = i2c_imx_unreg_slave, 1362 }; 1363 1364 static int i2c_imx_probe(struct platform_device *pdev) 1365 { 1366 struct imx_i2c_struct *i2c_imx; 1367 struct resource *res; 1368 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1369 void __iomem *base; 1370 int irq, ret; 1371 dma_addr_t phy_addr; 1372 const struct imx_i2c_hwdata *match; 1373 1374 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1375 1376 irq = platform_get_irq(pdev, 0); 1377 if (irq < 0) 1378 return irq; 1379 1380 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1381 base = devm_ioremap_resource(&pdev->dev, res); 1382 if (IS_ERR(base)) 1383 return PTR_ERR(base); 1384 1385 phy_addr = (dma_addr_t)res->start; 1386 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1387 if (!i2c_imx) 1388 return -ENOMEM; 1389 1390 match = device_get_match_data(&pdev->dev); 1391 if (match) 1392 i2c_imx->hwdata = match; 1393 else 1394 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1395 platform_get_device_id(pdev)->driver_data; 1396 1397 /* Setup i2c_imx driver structure */ 1398 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1399 i2c_imx->adapter.owner = THIS_MODULE; 1400 i2c_imx->adapter.algo = &i2c_imx_algo; 1401 i2c_imx->adapter.dev.parent = &pdev->dev; 1402 i2c_imx->adapter.nr = pdev->id; 1403 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1404 i2c_imx->base = base; 1405 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1406 1407 /* Get I2C clock */ 1408 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1409 if (IS_ERR(i2c_imx->clk)) 1410 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1411 "can't get I2C clock\n"); 1412 1413 ret = clk_prepare_enable(i2c_imx->clk); 1414 if (ret) { 1415 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1416 return ret; 1417 } 1418 1419 /* Init queue */ 1420 init_waitqueue_head(&i2c_imx->queue); 1421 1422 /* Set up adapter data */ 1423 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1424 1425 /* Set up platform driver data */ 1426 platform_set_drvdata(pdev, i2c_imx); 1427 1428 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1429 pm_runtime_use_autosuspend(&pdev->dev); 1430 pm_runtime_set_active(&pdev->dev); 1431 pm_runtime_enable(&pdev->dev); 1432 1433 ret = pm_runtime_get_sync(&pdev->dev); 1434 if (ret < 0) 1435 goto rpm_disable; 1436 1437 /* Request IRQ */ 1438 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1439 pdev->name, i2c_imx); 1440 if (ret) { 1441 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1442 goto rpm_disable; 1443 } 1444 1445 /* Set up clock divider */ 1446 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1447 ret = of_property_read_u32(pdev->dev.of_node, 1448 "clock-frequency", &i2c_imx->bitrate); 1449 if (ret < 0 && pdata && pdata->bitrate) 1450 i2c_imx->bitrate = pdata->bitrate; 1451 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1452 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1453 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1454 1455 i2c_imx_reset_regs(i2c_imx); 1456 1457 /* Init optional bus recovery function */ 1458 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1459 /* Give it another chance if pinctrl used is not ready yet */ 1460 if (ret == -EPROBE_DEFER) 1461 goto clk_notifier_unregister; 1462 1463 /* Add I2C adapter */ 1464 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1465 if (ret < 0) 1466 goto clk_notifier_unregister; 1467 1468 pm_runtime_mark_last_busy(&pdev->dev); 1469 pm_runtime_put_autosuspend(&pdev->dev); 1470 1471 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1472 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1473 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1474 i2c_imx->adapter.name); 1475 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1476 1477 /* Init DMA config if supported */ 1478 i2c_imx_dma_request(i2c_imx, phy_addr); 1479 1480 return 0; /* Return OK */ 1481 1482 clk_notifier_unregister: 1483 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1484 free_irq(irq, i2c_imx); 1485 rpm_disable: 1486 pm_runtime_put_noidle(&pdev->dev); 1487 pm_runtime_disable(&pdev->dev); 1488 pm_runtime_set_suspended(&pdev->dev); 1489 pm_runtime_dont_use_autosuspend(&pdev->dev); 1490 clk_disable_unprepare(i2c_imx->clk); 1491 return ret; 1492 } 1493 1494 static int i2c_imx_remove(struct platform_device *pdev) 1495 { 1496 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1497 int irq, ret; 1498 1499 ret = pm_runtime_get_sync(&pdev->dev); 1500 if (ret < 0) 1501 return ret; 1502 1503 /* remove adapter */ 1504 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1505 i2c_del_adapter(&i2c_imx->adapter); 1506 1507 if (i2c_imx->dma) 1508 i2c_imx_dma_free(i2c_imx); 1509 1510 /* setup chip registers to defaults */ 1511 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1512 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1513 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1514 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1515 1516 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1517 irq = platform_get_irq(pdev, 0); 1518 if (irq >= 0) 1519 free_irq(irq, i2c_imx); 1520 clk_disable_unprepare(i2c_imx->clk); 1521 1522 pm_runtime_put_noidle(&pdev->dev); 1523 pm_runtime_disable(&pdev->dev); 1524 1525 return 0; 1526 } 1527 1528 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1529 { 1530 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1531 1532 clk_disable(i2c_imx->clk); 1533 1534 return 0; 1535 } 1536 1537 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1538 { 1539 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1540 int ret; 1541 1542 ret = clk_enable(i2c_imx->clk); 1543 if (ret) 1544 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1545 1546 return ret; 1547 } 1548 1549 static const struct dev_pm_ops i2c_imx_pm_ops = { 1550 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1551 i2c_imx_runtime_resume, NULL) 1552 }; 1553 1554 static struct platform_driver i2c_imx_driver = { 1555 .probe = i2c_imx_probe, 1556 .remove = i2c_imx_remove, 1557 .driver = { 1558 .name = DRIVER_NAME, 1559 .pm = &i2c_imx_pm_ops, 1560 .of_match_table = i2c_imx_dt_ids, 1561 .acpi_match_table = i2c_imx_acpi_ids, 1562 }, 1563 .id_table = imx_i2c_devtype, 1564 }; 1565 1566 static int __init i2c_adap_imx_init(void) 1567 { 1568 return platform_driver_register(&i2c_imx_driver); 1569 } 1570 subsys_initcall(i2c_adap_imx_init); 1571 1572 static void __exit i2c_adap_imx_exit(void) 1573 { 1574 platform_driver_unregister(&i2c_imx_driver); 1575 } 1576 module_exit(i2c_adap_imx_exit); 1577 1578 MODULE_LICENSE("GPL"); 1579 MODULE_AUTHOR("Darius Augulis"); 1580 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1581 MODULE_ALIAS("platform:" DRIVER_NAME); 1582