1 /* 2 * Copyright (C) 2002 Motorola GSG-China 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, 17 * USA. 18 * 19 * Author: 20 * Darius Augulis, Teltonika Inc. 21 * 22 * Desc.: 23 * Implementation of I2C Adapter/Algorithm Driver 24 * for I2C Bus integrated in Freescale i.MX/MXC processors 25 * 26 * Derived from Motorola GSG China I2C example driver 27 * 28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 30 * Copyright (C) 2007 RightHand Technologies, Inc. 31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 32 * 33 * Copyright 2013 Freescale Semiconductor, Inc. 34 * 35 */ 36 37 /** Includes ******************************************************************* 38 *******************************************************************************/ 39 40 #include <linux/init.h> 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/errno.h> 44 #include <linux/err.h> 45 #include <linux/interrupt.h> 46 #include <linux/delay.h> 47 #include <linux/i2c.h> 48 #include <linux/io.h> 49 #include <linux/sched.h> 50 #include <linux/platform_device.h> 51 #include <linux/clk.h> 52 #include <linux/slab.h> 53 #include <linux/of.h> 54 #include <linux/of_device.h> 55 #include <linux/platform_data/i2c-imx.h> 56 57 /** Defines ******************************************************************** 58 *******************************************************************************/ 59 60 /* This will be the driver name the kernel reports */ 61 #define DRIVER_NAME "imx-i2c" 62 63 /* Default value */ 64 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 65 66 /* IMX I2C registers: 67 * the I2C register offset is different between SoCs, 68 * to provid support for all these chips, split the 69 * register offset into a fixed base address and a 70 * variable shift value, then the full register offset 71 * will be calculated by 72 * reg_off = ( reg_base_addr << reg_shift) 73 */ 74 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 76 #define IMX_I2C_I2CR 0x02 /* i2c control */ 77 #define IMX_I2C_I2SR 0x03 /* i2c status */ 78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 79 80 #define IMX_I2C_REGSHIFT 2 81 #define VF610_I2C_REGSHIFT 0 82 83 /* Bits of IMX I2C registers */ 84 #define I2SR_RXAK 0x01 85 #define I2SR_IIF 0x02 86 #define I2SR_SRW 0x04 87 #define I2SR_IAL 0x10 88 #define I2SR_IBB 0x20 89 #define I2SR_IAAS 0x40 90 #define I2SR_ICF 0x80 91 #define I2CR_RSTA 0x04 92 #define I2CR_TXAK 0x08 93 #define I2CR_MTX 0x10 94 #define I2CR_MSTA 0x20 95 #define I2CR_IIEN 0x40 96 #define I2CR_IEN 0x80 97 98 /* register bits different operating codes definition: 99 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 100 * - write zero to clear(w0c) INT flag on i.MX, 101 * - but write one to clear(w1c) INT flag on Vybrid. 102 * 2) I2CR: I2C module enable operation also differ between SoCs: 103 * - set I2CR_IEN bit enable the module on i.MX, 104 * - but clear I2CR_IEN bit enable the module on Vybrid. 105 */ 106 #define I2SR_CLR_OPCODE_W0C 0x0 107 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 108 #define I2CR_IEN_OPCODE_0 0x0 109 #define I2CR_IEN_OPCODE_1 I2CR_IEN 110 111 /** Variables ****************************************************************** 112 *******************************************************************************/ 113 114 /* 115 * sorted list of clock divider, register value pairs 116 * taken from table 26-5, p.26-9, Freescale i.MX 117 * Integrated Portable System Processor Reference Manual 118 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 119 * 120 * Duplicated divider values removed from list 121 */ 122 struct imx_i2c_clk_pair { 123 u16 div; 124 u16 val; 125 }; 126 127 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 128 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 129 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 130 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 131 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 132 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 133 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 134 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 135 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 136 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 137 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 138 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 139 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 140 { 3072, 0x1E }, { 3840, 0x1F } 141 }; 142 143 /* Vybrid VF610 clock divider, register value pairs */ 144 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 145 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 146 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 147 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 148 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 149 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 150 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 151 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 152 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 153 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 154 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 155 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 156 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 157 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 158 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 159 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 160 }; 161 162 enum imx_i2c_type { 163 IMX1_I2C, 164 IMX21_I2C, 165 VF610_I2C, 166 }; 167 168 struct imx_i2c_hwdata { 169 enum imx_i2c_type devtype; 170 unsigned regshift; 171 struct imx_i2c_clk_pair *clk_div; 172 unsigned ndivs; 173 unsigned i2sr_clr_opcode; 174 unsigned i2cr_ien_opcode; 175 }; 176 177 struct imx_i2c_struct { 178 struct i2c_adapter adapter; 179 struct clk *clk; 180 void __iomem *base; 181 wait_queue_head_t queue; 182 unsigned long i2csr; 183 unsigned int disable_delay; 184 int stopped; 185 unsigned int ifdr; /* IMX_I2C_IFDR */ 186 unsigned int cur_clk; 187 unsigned int bitrate; 188 const struct imx_i2c_hwdata *hwdata; 189 }; 190 191 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 192 .devtype = IMX1_I2C, 193 .regshift = IMX_I2C_REGSHIFT, 194 .clk_div = imx_i2c_clk_div, 195 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 196 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 197 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 198 199 }; 200 201 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 202 .devtype = IMX21_I2C, 203 .regshift = IMX_I2C_REGSHIFT, 204 .clk_div = imx_i2c_clk_div, 205 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 206 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 207 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 208 209 }; 210 211 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 212 .devtype = VF610_I2C, 213 .regshift = VF610_I2C_REGSHIFT, 214 .clk_div = vf610_i2c_clk_div, 215 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 216 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 217 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 218 219 }; 220 221 static struct platform_device_id imx_i2c_devtype[] = { 222 { 223 .name = "imx1-i2c", 224 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 225 }, { 226 .name = "imx21-i2c", 227 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 228 }, { 229 /* sentinel */ 230 } 231 }; 232 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 233 234 static const struct of_device_id i2c_imx_dt_ids[] = { 235 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 236 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 237 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 238 { /* sentinel */ } 239 }; 240 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 241 242 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 243 { 244 return i2c_imx->hwdata->devtype == IMX1_I2C; 245 } 246 247 static inline void imx_i2c_write_reg(unsigned int val, 248 struct imx_i2c_struct *i2c_imx, unsigned int reg) 249 { 250 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 251 } 252 253 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 254 unsigned int reg) 255 { 256 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 257 } 258 259 /** Functions for IMX I2C adapter driver *************************************** 260 *******************************************************************************/ 261 262 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 263 { 264 unsigned long orig_jiffies = jiffies; 265 unsigned int temp; 266 267 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 268 269 while (1) { 270 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 271 272 /* check for arbitration lost */ 273 if (temp & I2SR_IAL) { 274 temp &= ~I2SR_IAL; 275 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 276 return -EAGAIN; 277 } 278 279 if (for_busy && (temp & I2SR_IBB)) 280 break; 281 if (!for_busy && !(temp & I2SR_IBB)) 282 break; 283 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 284 dev_dbg(&i2c_imx->adapter.dev, 285 "<%s> I2C bus is busy\n", __func__); 286 return -ETIMEDOUT; 287 } 288 schedule(); 289 } 290 291 return 0; 292 } 293 294 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 295 { 296 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 297 298 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 299 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 300 return -ETIMEDOUT; 301 } 302 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 303 i2c_imx->i2csr = 0; 304 return 0; 305 } 306 307 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 308 { 309 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 310 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 311 return -EIO; /* No ACK */ 312 } 313 314 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 315 return 0; 316 } 317 318 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx) 319 { 320 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 321 unsigned int i2c_clk_rate; 322 unsigned int div; 323 int i; 324 325 /* Divider value calculation */ 326 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 327 if (i2c_imx->cur_clk == i2c_clk_rate) 328 return; 329 else 330 i2c_imx->cur_clk = i2c_clk_rate; 331 332 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 333 if (div < i2c_clk_div[0].div) 334 i = 0; 335 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 336 i = i2c_imx->hwdata->ndivs - 1; 337 else 338 for (i = 0; i2c_clk_div[i].div < div; i++); 339 340 /* Store divider value */ 341 i2c_imx->ifdr = i2c_clk_div[i].val; 342 343 /* 344 * There dummy delay is calculated. 345 * It should be about one I2C clock period long. 346 * This delay is used in I2C bus disable function 347 * to fix chip hardware bug. 348 */ 349 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 350 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 351 352 #ifdef CONFIG_I2C_DEBUG_BUS 353 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 354 i2c_clk_rate, div); 355 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 356 i2c_clk_div[i].val, i2c_clk_div[i].div); 357 #endif 358 } 359 360 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 361 { 362 unsigned int temp = 0; 363 int result; 364 365 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 366 367 i2c_imx_set_clk(i2c_imx); 368 369 result = clk_prepare_enable(i2c_imx->clk); 370 if (result) 371 return result; 372 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 373 /* Enable I2C controller */ 374 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 375 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 376 377 /* Wait controller to be stable */ 378 udelay(50); 379 380 /* Start I2C transaction */ 381 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 382 temp |= I2CR_MSTA; 383 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 384 result = i2c_imx_bus_busy(i2c_imx, 1); 385 if (result) 386 return result; 387 i2c_imx->stopped = 0; 388 389 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 390 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 391 return result; 392 } 393 394 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 395 { 396 unsigned int temp = 0; 397 398 if (!i2c_imx->stopped) { 399 /* Stop I2C transaction */ 400 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 401 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 402 temp &= ~(I2CR_MSTA | I2CR_MTX); 403 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 404 } 405 if (is_imx1_i2c(i2c_imx)) { 406 /* 407 * This delay caused by an i.MXL hardware bug. 408 * If no (or too short) delay, no "STOP" bit will be generated. 409 */ 410 udelay(i2c_imx->disable_delay); 411 } 412 413 if (!i2c_imx->stopped) { 414 i2c_imx_bus_busy(i2c_imx, 0); 415 i2c_imx->stopped = 1; 416 } 417 418 /* Disable I2C controller */ 419 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 420 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 421 clk_disable_unprepare(i2c_imx->clk); 422 } 423 424 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 425 { 426 struct imx_i2c_struct *i2c_imx = dev_id; 427 unsigned int temp; 428 429 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 430 if (temp & I2SR_IIF) { 431 /* save status register */ 432 i2c_imx->i2csr = temp; 433 temp &= ~I2SR_IIF; 434 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 435 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 436 wake_up(&i2c_imx->queue); 437 return IRQ_HANDLED; 438 } 439 440 return IRQ_NONE; 441 } 442 443 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 444 { 445 int i, result; 446 447 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 448 __func__, msgs->addr << 1); 449 450 /* write slave address */ 451 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 452 result = i2c_imx_trx_complete(i2c_imx); 453 if (result) 454 return result; 455 result = i2c_imx_acked(i2c_imx); 456 if (result) 457 return result; 458 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 459 460 /* write data */ 461 for (i = 0; i < msgs->len; i++) { 462 dev_dbg(&i2c_imx->adapter.dev, 463 "<%s> write byte: B%d=0x%X\n", 464 __func__, i, msgs->buf[i]); 465 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 466 result = i2c_imx_trx_complete(i2c_imx); 467 if (result) 468 return result; 469 result = i2c_imx_acked(i2c_imx); 470 if (result) 471 return result; 472 } 473 return 0; 474 } 475 476 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 477 { 478 int i, result; 479 unsigned int temp; 480 int block_data = msgs->flags & I2C_M_RECV_LEN; 481 482 dev_dbg(&i2c_imx->adapter.dev, 483 "<%s> write slave address: addr=0x%x\n", 484 __func__, (msgs->addr << 1) | 0x01); 485 486 /* write slave address */ 487 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); 488 result = i2c_imx_trx_complete(i2c_imx); 489 if (result) 490 return result; 491 result = i2c_imx_acked(i2c_imx); 492 if (result) 493 return result; 494 495 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 496 497 /* setup bus to read data */ 498 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 499 temp &= ~I2CR_MTX; 500 501 /* 502 * Reset the I2CR_TXAK flag initially for SMBus block read since the 503 * length is unknown 504 */ 505 if ((msgs->len - 1) || block_data) 506 temp &= ~I2CR_TXAK; 507 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 508 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 509 510 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 511 512 /* read data */ 513 for (i = 0; i < msgs->len; i++) { 514 u8 len = 0; 515 result = i2c_imx_trx_complete(i2c_imx); 516 if (result) 517 return result; 518 /* 519 * First byte is the length of remaining packet 520 * in the SMBus block data read. Add it to 521 * msgs->len. 522 */ 523 if ((!i) && block_data) { 524 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 525 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 526 return -EPROTO; 527 dev_dbg(&i2c_imx->adapter.dev, 528 "<%s> read length: 0x%X\n", 529 __func__, len); 530 msgs->len += len; 531 } 532 if (i == (msgs->len - 1)) { 533 if (is_lastmsg) { 534 /* 535 * It must generate STOP before read I2DR to prevent 536 * controller from generating another clock cycle 537 */ 538 dev_dbg(&i2c_imx->adapter.dev, 539 "<%s> clear MSTA\n", __func__); 540 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 541 temp &= ~(I2CR_MSTA | I2CR_MTX); 542 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 543 i2c_imx_bus_busy(i2c_imx, 0); 544 i2c_imx->stopped = 1; 545 } else { 546 /* 547 * For i2c master receiver repeat restart operation like: 548 * read -> repeat MSTA -> read/write 549 * The controller must set MTX before read the last byte in 550 * the first read operation, otherwise the first read cost 551 * one extra clock cycle. 552 */ 553 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 554 temp |= I2CR_MTX; 555 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 556 } 557 } else if (i == (msgs->len - 2)) { 558 dev_dbg(&i2c_imx->adapter.dev, 559 "<%s> set TXAK\n", __func__); 560 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 561 temp |= I2CR_TXAK; 562 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 563 } 564 if ((!i) && block_data) 565 msgs->buf[0] = len; 566 else 567 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 568 dev_dbg(&i2c_imx->adapter.dev, 569 "<%s> read byte: B%d=0x%X\n", 570 __func__, i, msgs->buf[i]); 571 } 572 return 0; 573 } 574 575 static int i2c_imx_xfer(struct i2c_adapter *adapter, 576 struct i2c_msg *msgs, int num) 577 { 578 unsigned int i, temp; 579 int result; 580 bool is_lastmsg = false; 581 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 582 583 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 584 585 /* Start I2C transfer */ 586 result = i2c_imx_start(i2c_imx); 587 if (result) 588 goto fail0; 589 590 /* read/write data */ 591 for (i = 0; i < num; i++) { 592 if (i == num - 1) 593 is_lastmsg = true; 594 595 if (i) { 596 dev_dbg(&i2c_imx->adapter.dev, 597 "<%s> repeated start\n", __func__); 598 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 599 temp |= I2CR_RSTA; 600 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 601 result = i2c_imx_bus_busy(i2c_imx, 1); 602 if (result) 603 goto fail0; 604 } 605 dev_dbg(&i2c_imx->adapter.dev, 606 "<%s> transfer message: %d\n", __func__, i); 607 /* write/read data */ 608 #ifdef CONFIG_I2C_DEBUG_BUS 609 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 610 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " 611 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, 612 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 613 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 614 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 615 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 616 dev_dbg(&i2c_imx->adapter.dev, 617 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " 618 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, 619 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 620 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 621 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 622 (temp & I2SR_RXAK ? 1 : 0)); 623 #endif 624 if (msgs[i].flags & I2C_M_RD) 625 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 626 else 627 result = i2c_imx_write(i2c_imx, &msgs[i]); 628 if (result) 629 goto fail0; 630 } 631 632 fail0: 633 /* Stop I2C transfer */ 634 i2c_imx_stop(i2c_imx); 635 636 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 637 (result < 0) ? "error" : "success msg", 638 (result < 0) ? result : num); 639 return (result < 0) ? result : num; 640 } 641 642 static u32 i2c_imx_func(struct i2c_adapter *adapter) 643 { 644 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 645 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 646 } 647 648 static struct i2c_algorithm i2c_imx_algo = { 649 .master_xfer = i2c_imx_xfer, 650 .functionality = i2c_imx_func, 651 }; 652 653 static int i2c_imx_probe(struct platform_device *pdev) 654 { 655 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 656 &pdev->dev); 657 struct imx_i2c_struct *i2c_imx; 658 struct resource *res; 659 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 660 void __iomem *base; 661 int irq, ret; 662 663 dev_dbg(&pdev->dev, "<%s>\n", __func__); 664 665 irq = platform_get_irq(pdev, 0); 666 if (irq < 0) { 667 dev_err(&pdev->dev, "can't get irq number\n"); 668 return irq; 669 } 670 671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 672 base = devm_ioremap_resource(&pdev->dev, res); 673 if (IS_ERR(base)) 674 return PTR_ERR(base); 675 676 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct), 677 GFP_KERNEL); 678 if (!i2c_imx) 679 return -ENOMEM; 680 681 if (of_id) 682 i2c_imx->hwdata = of_id->data; 683 else 684 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 685 platform_get_device_id(pdev)->driver_data; 686 687 /* Setup i2c_imx driver structure */ 688 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 689 i2c_imx->adapter.owner = THIS_MODULE; 690 i2c_imx->adapter.algo = &i2c_imx_algo; 691 i2c_imx->adapter.dev.parent = &pdev->dev; 692 i2c_imx->adapter.nr = pdev->id; 693 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 694 i2c_imx->base = base; 695 696 /* Get I2C clock */ 697 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 698 if (IS_ERR(i2c_imx->clk)) { 699 dev_err(&pdev->dev, "can't get I2C clock\n"); 700 return PTR_ERR(i2c_imx->clk); 701 } 702 703 ret = clk_prepare_enable(i2c_imx->clk); 704 if (ret) { 705 dev_err(&pdev->dev, "can't enable I2C clock\n"); 706 return ret; 707 } 708 /* Request IRQ */ 709 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, 710 pdev->name, i2c_imx); 711 if (ret) { 712 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 713 goto clk_disable; 714 } 715 716 /* Init queue */ 717 init_waitqueue_head(&i2c_imx->queue); 718 719 /* Set up adapter data */ 720 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 721 722 /* Set up clock divider */ 723 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 724 ret = of_property_read_u32(pdev->dev.of_node, 725 "clock-frequency", &i2c_imx->bitrate); 726 if (ret < 0 && pdata && pdata->bitrate) 727 i2c_imx->bitrate = pdata->bitrate; 728 729 /* Set up chip registers to defaults */ 730 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 731 i2c_imx, IMX_I2C_I2CR); 732 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 733 734 /* Add I2C adapter */ 735 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 736 if (ret < 0) { 737 dev_err(&pdev->dev, "registration failed\n"); 738 goto clk_disable; 739 } 740 741 /* Set up platform driver data */ 742 platform_set_drvdata(pdev, i2c_imx); 743 clk_disable_unprepare(i2c_imx->clk); 744 745 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 746 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 747 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 748 i2c_imx->adapter.name); 749 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 750 751 return 0; /* Return OK */ 752 753 clk_disable: 754 clk_disable_unprepare(i2c_imx->clk); 755 return ret; 756 } 757 758 static int i2c_imx_remove(struct platform_device *pdev) 759 { 760 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 761 762 /* remove adapter */ 763 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 764 i2c_del_adapter(&i2c_imx->adapter); 765 766 /* setup chip registers to defaults */ 767 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 768 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 769 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 770 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 771 772 return 0; 773 } 774 775 static struct platform_driver i2c_imx_driver = { 776 .probe = i2c_imx_probe, 777 .remove = i2c_imx_remove, 778 .driver = { 779 .name = DRIVER_NAME, 780 .owner = THIS_MODULE, 781 .of_match_table = i2c_imx_dt_ids, 782 }, 783 .id_table = imx_i2c_devtype, 784 }; 785 786 static int __init i2c_adap_imx_init(void) 787 { 788 return platform_driver_register(&i2c_imx_driver); 789 } 790 subsys_initcall(i2c_adap_imx_init); 791 792 static void __exit i2c_adap_imx_exit(void) 793 { 794 platform_driver_unregister(&i2c_imx_driver); 795 } 796 module_exit(i2c_adap_imx_exit); 797 798 MODULE_LICENSE("GPL"); 799 MODULE_AUTHOR("Darius Augulis"); 800 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 801 MODULE_ALIAS("platform:" DRIVER_NAME); 802