1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/spinlock.h> 41 #include <linux/hrtimer.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/of_dma.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/platform_data/i2c-imx.h> 48 #include <linux/platform_device.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/sched.h> 51 #include <linux/slab.h> 52 53 /* This will be the driver name the kernel reports */ 54 #define DRIVER_NAME "imx-i2c" 55 56 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 57 58 /* 59 * Enable DMA if transfer byte size is bigger than this threshold. 60 * As the hardware request, it must bigger than 4 bytes.\ 61 * I have set '16' here, maybe it's not the best but I think it's 62 * the appropriate. 63 */ 64 #define DMA_THRESHOLD 16 65 #define DMA_TIMEOUT 1000 66 67 /* IMX I2C registers: 68 * the I2C register offset is different between SoCs, 69 * to provid support for all these chips, split the 70 * register offset into a fixed base address and a 71 * variable shift value, then the full register offset 72 * will be calculated by 73 * reg_off = ( reg_base_addr << reg_shift) 74 */ 75 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 76 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 77 #define IMX_I2C_I2CR 0x02 /* i2c control */ 78 #define IMX_I2C_I2SR 0x03 /* i2c status */ 79 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 80 81 /* 82 * All of the layerscape series SoCs support IBIC register. 83 */ 84 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 85 86 #define IMX_I2C_REGSHIFT 2 87 #define VF610_I2C_REGSHIFT 0 88 89 /* Bits of IMX I2C registers */ 90 #define I2SR_RXAK 0x01 91 #define I2SR_IIF 0x02 92 #define I2SR_SRW 0x04 93 #define I2SR_IAL 0x10 94 #define I2SR_IBB 0x20 95 #define I2SR_IAAS 0x40 96 #define I2SR_ICF 0x80 97 #define I2CR_DMAEN 0x02 98 #define I2CR_RSTA 0x04 99 #define I2CR_TXAK 0x08 100 #define I2CR_MTX 0x10 101 #define I2CR_MSTA 0x20 102 #define I2CR_IIEN 0x40 103 #define I2CR_IEN 0x80 104 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 105 106 /* register bits different operating codes definition: 107 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 108 * - write zero to clear(w0c) INT flag on i.MX, 109 * - but write one to clear(w1c) INT flag on Vybrid. 110 * 2) I2CR: I2C module enable operation also differ between SoCs: 111 * - set I2CR_IEN bit enable the module on i.MX, 112 * - but clear I2CR_IEN bit enable the module on Vybrid. 113 */ 114 #define I2SR_CLR_OPCODE_W0C 0x0 115 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 116 #define I2CR_IEN_OPCODE_0 0x0 117 #define I2CR_IEN_OPCODE_1 I2CR_IEN 118 119 #define I2C_PM_TIMEOUT 10 /* ms */ 120 121 /* 122 * sorted list of clock divider, register value pairs 123 * taken from table 26-5, p.26-9, Freescale i.MX 124 * Integrated Portable System Processor Reference Manual 125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 126 * 127 * Duplicated divider values removed from list 128 */ 129 struct imx_i2c_clk_pair { 130 u16 div; 131 u16 val; 132 }; 133 134 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 147 { 3072, 0x1E }, { 3840, 0x1F } 148 }; 149 150 /* Vybrid VF610 clock divider, register value pairs */ 151 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 167 }; 168 169 enum imx_i2c_type { 170 IMX1_I2C, 171 IMX21_I2C, 172 VF610_I2C, 173 }; 174 175 struct imx_i2c_hwdata { 176 enum imx_i2c_type devtype; 177 unsigned int regshift; 178 struct imx_i2c_clk_pair *clk_div; 179 unsigned int ndivs; 180 unsigned int i2sr_clr_opcode; 181 unsigned int i2cr_ien_opcode; 182 }; 183 184 struct imx_i2c_dma { 185 struct dma_chan *chan_tx; 186 struct dma_chan *chan_rx; 187 struct dma_chan *chan_using; 188 struct completion cmd_complete; 189 dma_addr_t dma_buf; 190 unsigned int dma_len; 191 enum dma_transfer_direction dma_transfer_dir; 192 enum dma_data_direction dma_data_dir; 193 }; 194 195 struct imx_i2c_struct { 196 struct i2c_adapter adapter; 197 struct clk *clk; 198 struct notifier_block clk_change_nb; 199 void __iomem *base; 200 wait_queue_head_t queue; 201 unsigned long i2csr; 202 unsigned int disable_delay; 203 int stopped; 204 unsigned int ifdr; /* IMX_I2C_IFDR */ 205 unsigned int cur_clk; 206 unsigned int bitrate; 207 const struct imx_i2c_hwdata *hwdata; 208 struct i2c_bus_recovery_info rinfo; 209 210 struct pinctrl *pinctrl; 211 struct pinctrl_state *pinctrl_pins_default; 212 struct pinctrl_state *pinctrl_pins_gpio; 213 214 struct imx_i2c_dma *dma; 215 struct i2c_client *slave; 216 enum i2c_slave_event last_slave_event; 217 218 /* For checking slave events. */ 219 spinlock_t slave_lock; 220 struct hrtimer slave_timer; 221 }; 222 223 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 224 .devtype = IMX1_I2C, 225 .regshift = IMX_I2C_REGSHIFT, 226 .clk_div = imx_i2c_clk_div, 227 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 228 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 229 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 230 231 }; 232 233 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 234 .devtype = IMX21_I2C, 235 .regshift = IMX_I2C_REGSHIFT, 236 .clk_div = imx_i2c_clk_div, 237 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 238 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 239 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 240 241 }; 242 243 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 244 .devtype = VF610_I2C, 245 .regshift = VF610_I2C_REGSHIFT, 246 .clk_div = vf610_i2c_clk_div, 247 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 248 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 249 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 250 251 }; 252 253 static const struct platform_device_id imx_i2c_devtype[] = { 254 { 255 .name = "imx1-i2c", 256 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 257 }, { 258 .name = "imx21-i2c", 259 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 260 }, { 261 /* sentinel */ 262 } 263 }; 264 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 265 266 static const struct of_device_id i2c_imx_dt_ids[] = { 267 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 268 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 269 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 270 { /* sentinel */ } 271 }; 272 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 273 274 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 275 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 276 { } 277 }; 278 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 279 280 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 281 { 282 return i2c_imx->hwdata->devtype == IMX1_I2C; 283 } 284 285 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 286 { 287 return i2c_imx->hwdata->devtype == VF610_I2C; 288 } 289 290 static inline void imx_i2c_write_reg(unsigned int val, 291 struct imx_i2c_struct *i2c_imx, unsigned int reg) 292 { 293 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 294 } 295 296 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 297 unsigned int reg) 298 { 299 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 300 } 301 302 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 303 { 304 unsigned int temp; 305 306 /* 307 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 308 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 309 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 310 */ 311 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 312 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 313 } 314 315 /* Set up i2c controller register and i2c status register to default value. */ 316 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 317 { 318 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 319 i2c_imx, IMX_I2C_I2CR); 320 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 321 } 322 323 /* Functions for DMA support */ 324 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 325 dma_addr_t phy_addr) 326 { 327 struct imx_i2c_dma *dma; 328 struct dma_slave_config dma_sconfig; 329 struct device *dev = &i2c_imx->adapter.dev; 330 int ret; 331 332 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 333 if (!dma) 334 return; 335 336 dma->chan_tx = dma_request_chan(dev, "tx"); 337 if (IS_ERR(dma->chan_tx)) { 338 ret = PTR_ERR(dma->chan_tx); 339 if (ret != -ENODEV && ret != -EPROBE_DEFER) 340 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 341 goto fail_al; 342 } 343 344 dma_sconfig.dst_addr = phy_addr + 345 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 346 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 347 dma_sconfig.dst_maxburst = 1; 348 dma_sconfig.direction = DMA_MEM_TO_DEV; 349 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 350 if (ret < 0) { 351 dev_err(dev, "can't configure tx channel (%d)\n", ret); 352 goto fail_tx; 353 } 354 355 dma->chan_rx = dma_request_chan(dev, "rx"); 356 if (IS_ERR(dma->chan_rx)) { 357 ret = PTR_ERR(dma->chan_rx); 358 if (ret != -ENODEV && ret != -EPROBE_DEFER) 359 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 360 goto fail_tx; 361 } 362 363 dma_sconfig.src_addr = phy_addr + 364 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 365 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 366 dma_sconfig.src_maxburst = 1; 367 dma_sconfig.direction = DMA_DEV_TO_MEM; 368 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 369 if (ret < 0) { 370 dev_err(dev, "can't configure rx channel (%d)\n", ret); 371 goto fail_rx; 372 } 373 374 i2c_imx->dma = dma; 375 init_completion(&dma->cmd_complete); 376 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 377 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 378 379 return; 380 381 fail_rx: 382 dma_release_channel(dma->chan_rx); 383 fail_tx: 384 dma_release_channel(dma->chan_tx); 385 fail_al: 386 devm_kfree(dev, dma); 387 } 388 389 static void i2c_imx_dma_callback(void *arg) 390 { 391 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 392 struct imx_i2c_dma *dma = i2c_imx->dma; 393 394 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 395 dma->dma_len, dma->dma_data_dir); 396 complete(&dma->cmd_complete); 397 } 398 399 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 400 struct i2c_msg *msgs) 401 { 402 struct imx_i2c_dma *dma = i2c_imx->dma; 403 struct dma_async_tx_descriptor *txdesc; 404 struct device *dev = &i2c_imx->adapter.dev; 405 struct device *chan_dev = dma->chan_using->device->dev; 406 407 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 408 dma->dma_len, dma->dma_data_dir); 409 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 410 dev_err(dev, "DMA mapping failed\n"); 411 goto err_map; 412 } 413 414 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 415 dma->dma_len, dma->dma_transfer_dir, 416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 417 if (!txdesc) { 418 dev_err(dev, "Not able to get desc for DMA xfer\n"); 419 goto err_desc; 420 } 421 422 reinit_completion(&dma->cmd_complete); 423 txdesc->callback = i2c_imx_dma_callback; 424 txdesc->callback_param = i2c_imx; 425 if (dma_submit_error(dmaengine_submit(txdesc))) { 426 dev_err(dev, "DMA submit failed\n"); 427 goto err_submit; 428 } 429 430 dma_async_issue_pending(dma->chan_using); 431 return 0; 432 433 err_submit: 434 dmaengine_terminate_sync(dma->chan_using); 435 err_desc: 436 dma_unmap_single(chan_dev, dma->dma_buf, 437 dma->dma_len, dma->dma_data_dir); 438 err_map: 439 return -EINVAL; 440 } 441 442 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 443 { 444 struct imx_i2c_dma *dma = i2c_imx->dma; 445 446 dma->dma_buf = 0; 447 dma->dma_len = 0; 448 449 dma_release_channel(dma->chan_tx); 450 dma->chan_tx = NULL; 451 452 dma_release_channel(dma->chan_rx); 453 dma->chan_rx = NULL; 454 455 dma->chan_using = NULL; 456 } 457 458 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 459 { 460 unsigned long orig_jiffies = jiffies; 461 unsigned int temp; 462 463 while (1) { 464 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 465 466 /* check for arbitration lost */ 467 if (temp & I2SR_IAL) { 468 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 469 return -EAGAIN; 470 } 471 472 if (for_busy && (temp & I2SR_IBB)) { 473 i2c_imx->stopped = 0; 474 break; 475 } 476 if (!for_busy && !(temp & I2SR_IBB)) { 477 i2c_imx->stopped = 1; 478 break; 479 } 480 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 481 dev_dbg(&i2c_imx->adapter.dev, 482 "<%s> I2C bus is busy\n", __func__); 483 return -ETIMEDOUT; 484 } 485 if (atomic) 486 udelay(100); 487 else 488 schedule(); 489 } 490 491 return 0; 492 } 493 494 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 495 { 496 if (atomic) { 497 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 498 unsigned int regval; 499 500 /* 501 * The formula for the poll timeout is documented in the RM 502 * Rev.5 on page 1878: 503 * T_min = 10/F_scl 504 * Set the value hard as it is done for the non-atomic use-case. 505 * Use 10 kHz for the calculation since this is the minimum 506 * allowed SMBus frequency. Also add an offset of 100us since it 507 * turned out that the I2SR_IIF bit isn't set correctly within 508 * the minimum timeout in polling mode. 509 */ 510 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 511 i2c_imx->i2csr = regval; 512 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 513 } else { 514 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 515 } 516 517 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 518 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 519 return -ETIMEDOUT; 520 } 521 522 /* check for arbitration lost */ 523 if (i2c_imx->i2csr & I2SR_IAL) { 524 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 525 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 526 527 i2c_imx->i2csr = 0; 528 return -EAGAIN; 529 } 530 531 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 532 i2c_imx->i2csr = 0; 533 return 0; 534 } 535 536 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 537 { 538 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 539 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 540 return -ENXIO; /* No ACK */ 541 } 542 543 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 544 return 0; 545 } 546 547 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 548 unsigned int i2c_clk_rate) 549 { 550 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 551 unsigned int div; 552 int i; 553 554 /* Divider value calculation */ 555 if (i2c_imx->cur_clk == i2c_clk_rate) 556 return; 557 558 i2c_imx->cur_clk = i2c_clk_rate; 559 560 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 561 if (div < i2c_clk_div[0].div) 562 i = 0; 563 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 564 i = i2c_imx->hwdata->ndivs - 1; 565 else 566 for (i = 0; i2c_clk_div[i].div < div; i++) 567 ; 568 569 /* Store divider value */ 570 i2c_imx->ifdr = i2c_clk_div[i].val; 571 572 /* 573 * There dummy delay is calculated. 574 * It should be about one I2C clock period long. 575 * This delay is used in I2C bus disable function 576 * to fix chip hardware bug. 577 */ 578 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 579 i2c_clk_rate / 2); 580 581 #ifdef CONFIG_I2C_DEBUG_BUS 582 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 583 i2c_clk_rate, div); 584 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 585 i2c_clk_div[i].val, i2c_clk_div[i].div); 586 #endif 587 } 588 589 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 590 unsigned long action, void *data) 591 { 592 struct clk_notifier_data *ndata = data; 593 struct imx_i2c_struct *i2c_imx = container_of(nb, 594 struct imx_i2c_struct, 595 clk_change_nb); 596 597 if (action & POST_RATE_CHANGE) 598 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 599 600 return NOTIFY_OK; 601 } 602 603 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 604 { 605 unsigned int temp = 0; 606 int result; 607 608 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 609 /* Enable I2C controller */ 610 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 611 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 612 613 /* Wait controller to be stable */ 614 if (atomic) 615 udelay(50); 616 else 617 usleep_range(50, 150); 618 619 /* Start I2C transaction */ 620 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 621 temp |= I2CR_MSTA; 622 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 623 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 624 if (result) 625 return result; 626 627 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 628 if (atomic) 629 temp &= ~I2CR_IIEN; /* Disable interrupt */ 630 631 temp &= ~I2CR_DMAEN; 632 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 633 return result; 634 } 635 636 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 637 { 638 unsigned int temp = 0; 639 640 if (!i2c_imx->stopped) { 641 /* Stop I2C transaction */ 642 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 643 if (!(temp & I2CR_MSTA)) 644 i2c_imx->stopped = 1; 645 temp &= ~(I2CR_MSTA | I2CR_MTX); 646 if (i2c_imx->dma) 647 temp &= ~I2CR_DMAEN; 648 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 649 } 650 if (is_imx1_i2c(i2c_imx)) { 651 /* 652 * This delay caused by an i.MXL hardware bug. 653 * If no (or too short) delay, no "STOP" bit will be generated. 654 */ 655 udelay(i2c_imx->disable_delay); 656 } 657 658 if (!i2c_imx->stopped) 659 i2c_imx_bus_busy(i2c_imx, 0, atomic); 660 661 /* Disable I2C controller */ 662 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 663 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 664 } 665 666 /* 667 * Enable bus idle interrupts 668 * Note: IBIC register will be cleared after disabled i2c module. 669 * All of layerscape series SoCs support IBIC register. 670 */ 671 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 672 { 673 if (is_vf610_i2c(i2c_imx)) { 674 unsigned int temp; 675 676 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 677 temp |= IBIC_BIIE; 678 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 679 } 680 } 681 682 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 683 enum i2c_slave_event event, u8 *val) 684 { 685 i2c_slave_event(i2c_imx->slave, event, val); 686 i2c_imx->last_slave_event = event; 687 } 688 689 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 690 { 691 u8 val = 0; 692 693 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 694 switch (i2c_imx->last_slave_event) { 695 case I2C_SLAVE_READ_REQUESTED: 696 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 697 &val); 698 break; 699 700 case I2C_SLAVE_WRITE_REQUESTED: 701 case I2C_SLAVE_READ_PROCESSED: 702 case I2C_SLAVE_WRITE_RECEIVED: 703 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 704 break; 705 706 case I2C_SLAVE_STOP: 707 break; 708 } 709 } 710 } 711 712 /* Returns true if the timer should be restarted, false if not. */ 713 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 714 unsigned int status, unsigned int ctl) 715 { 716 u8 value = 0; 717 718 if (status & I2SR_IAL) { /* Arbitration lost */ 719 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 720 if (!(status & I2SR_IAAS)) 721 return IRQ_HANDLED; 722 } 723 724 if (!(status & I2SR_IBB)) { 725 /* No master on the bus, that could mean a stop condition. */ 726 i2c_imx_slave_finish_op(i2c_imx); 727 return IRQ_HANDLED; 728 } 729 730 if (!(status & I2SR_ICF)) 731 /* Data transfer still in progress, ignore this. */ 732 goto out; 733 734 if (status & I2SR_IAAS) { /* Addressed as a slave */ 735 i2c_imx_slave_finish_op(i2c_imx); 736 if (status & I2SR_SRW) { /* Master wants to read from us*/ 737 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 738 i2c_imx_slave_event(i2c_imx, 739 I2C_SLAVE_READ_REQUESTED, &value); 740 741 /* Slave transmit */ 742 ctl |= I2CR_MTX; 743 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 744 745 /* Send data */ 746 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 747 } else { /* Master wants to write to us */ 748 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 749 i2c_imx_slave_event(i2c_imx, 750 I2C_SLAVE_WRITE_REQUESTED, &value); 751 752 /* Slave receive */ 753 ctl &= ~I2CR_MTX; 754 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 755 /* Dummy read */ 756 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 757 } 758 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 759 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 760 i2c_imx_slave_event(i2c_imx, 761 I2C_SLAVE_WRITE_RECEIVED, &value); 762 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 763 ctl |= I2CR_MTX; 764 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 765 766 i2c_imx_slave_event(i2c_imx, 767 I2C_SLAVE_READ_PROCESSED, &value); 768 769 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 770 } else { /* Transmit mode received NAK, operation is done */ 771 ctl &= ~I2CR_MTX; 772 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 773 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 774 i2c_imx_slave_finish_op(i2c_imx); 775 return IRQ_HANDLED; 776 } 777 778 out: 779 /* 780 * No need to check the return value here. If it returns 0 or 781 * 1, then everything is fine. If it returns -1, then the 782 * timer is running in the handler. This will still work, 783 * though it may be redone (or already have been done) by the 784 * timer function. 785 */ 786 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 787 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 788 hrtimer_restart(&i2c_imx->slave_timer); 789 return IRQ_HANDLED; 790 } 791 792 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 793 { 794 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 795 slave_timer); 796 unsigned int ctl, status; 797 unsigned long flags; 798 799 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 800 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 801 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 802 i2c_imx_slave_handle(i2c_imx, status, ctl); 803 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 804 return HRTIMER_NORESTART; 805 } 806 807 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 808 { 809 int temp; 810 811 /* Set slave addr. */ 812 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 813 814 i2c_imx_reset_regs(i2c_imx); 815 816 /* Enable module */ 817 temp = i2c_imx->hwdata->i2cr_ien_opcode; 818 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 819 820 /* Enable interrupt from i2c module */ 821 temp |= I2CR_IIEN; 822 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 823 824 i2c_imx_enable_bus_idle(i2c_imx); 825 } 826 827 static int i2c_imx_reg_slave(struct i2c_client *client) 828 { 829 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 830 int ret; 831 832 if (i2c_imx->slave) 833 return -EBUSY; 834 835 i2c_imx->slave = client; 836 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 837 838 /* Resume */ 839 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 840 if (ret < 0) { 841 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 842 return ret; 843 } 844 845 i2c_imx_slave_init(i2c_imx); 846 847 return 0; 848 } 849 850 static int i2c_imx_unreg_slave(struct i2c_client *client) 851 { 852 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 853 int ret; 854 855 if (!i2c_imx->slave) 856 return -EINVAL; 857 858 /* Reset slave address. */ 859 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 860 861 i2c_imx_reset_regs(i2c_imx); 862 863 i2c_imx->slave = NULL; 864 865 /* Suspend */ 866 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 867 if (ret < 0) 868 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 869 870 return ret; 871 } 872 873 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 874 { 875 /* save status register */ 876 i2c_imx->i2csr = status; 877 wake_up(&i2c_imx->queue); 878 879 return IRQ_HANDLED; 880 } 881 882 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 883 { 884 struct imx_i2c_struct *i2c_imx = dev_id; 885 unsigned int ctl, status; 886 unsigned long flags; 887 888 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 889 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 890 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 891 892 if (status & I2SR_IIF) { 893 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 894 if (i2c_imx->slave) { 895 if (!(ctl & I2CR_MSTA)) { 896 irqreturn_t ret; 897 898 ret = i2c_imx_slave_handle(i2c_imx, 899 status, ctl); 900 spin_unlock_irqrestore(&i2c_imx->slave_lock, 901 flags); 902 return ret; 903 } 904 i2c_imx_slave_finish_op(i2c_imx); 905 } 906 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 907 return i2c_imx_master_isr(i2c_imx, status); 908 } 909 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 910 911 return IRQ_NONE; 912 } 913 914 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 915 struct i2c_msg *msgs) 916 { 917 int result; 918 unsigned long time_left; 919 unsigned int temp = 0; 920 unsigned long orig_jiffies = jiffies; 921 struct imx_i2c_dma *dma = i2c_imx->dma; 922 struct device *dev = &i2c_imx->adapter.dev; 923 924 dma->chan_using = dma->chan_tx; 925 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 926 dma->dma_data_dir = DMA_TO_DEVICE; 927 dma->dma_len = msgs->len - 1; 928 result = i2c_imx_dma_xfer(i2c_imx, msgs); 929 if (result) 930 return result; 931 932 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 933 temp |= I2CR_DMAEN; 934 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 935 936 /* 937 * Write slave address. 938 * The first byte must be transmitted by the CPU. 939 */ 940 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 941 time_left = wait_for_completion_timeout( 942 &i2c_imx->dma->cmd_complete, 943 msecs_to_jiffies(DMA_TIMEOUT)); 944 if (time_left == 0) { 945 dmaengine_terminate_sync(dma->chan_using); 946 return -ETIMEDOUT; 947 } 948 949 /* Waiting for transfer complete. */ 950 while (1) { 951 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 952 if (temp & I2SR_ICF) 953 break; 954 if (time_after(jiffies, orig_jiffies + 955 msecs_to_jiffies(DMA_TIMEOUT))) { 956 dev_dbg(dev, "<%s> Timeout\n", __func__); 957 return -ETIMEDOUT; 958 } 959 schedule(); 960 } 961 962 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 963 temp &= ~I2CR_DMAEN; 964 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 965 966 /* The last data byte must be transferred by the CPU. */ 967 imx_i2c_write_reg(msgs->buf[msgs->len-1], 968 i2c_imx, IMX_I2C_I2DR); 969 result = i2c_imx_trx_complete(i2c_imx, false); 970 if (result) 971 return result; 972 973 return i2c_imx_acked(i2c_imx); 974 } 975 976 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 977 struct i2c_msg *msgs, bool is_lastmsg) 978 { 979 int result; 980 unsigned long time_left; 981 unsigned int temp; 982 unsigned long orig_jiffies = jiffies; 983 struct imx_i2c_dma *dma = i2c_imx->dma; 984 struct device *dev = &i2c_imx->adapter.dev; 985 986 987 dma->chan_using = dma->chan_rx; 988 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 989 dma->dma_data_dir = DMA_FROM_DEVICE; 990 /* The last two data bytes must be transferred by the CPU. */ 991 dma->dma_len = msgs->len - 2; 992 result = i2c_imx_dma_xfer(i2c_imx, msgs); 993 if (result) 994 return result; 995 996 time_left = wait_for_completion_timeout( 997 &i2c_imx->dma->cmd_complete, 998 msecs_to_jiffies(DMA_TIMEOUT)); 999 if (time_left == 0) { 1000 dmaengine_terminate_sync(dma->chan_using); 1001 return -ETIMEDOUT; 1002 } 1003 1004 /* waiting for transfer complete. */ 1005 while (1) { 1006 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1007 if (temp & I2SR_ICF) 1008 break; 1009 if (time_after(jiffies, orig_jiffies + 1010 msecs_to_jiffies(DMA_TIMEOUT))) { 1011 dev_dbg(dev, "<%s> Timeout\n", __func__); 1012 return -ETIMEDOUT; 1013 } 1014 schedule(); 1015 } 1016 1017 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1018 temp &= ~I2CR_DMAEN; 1019 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1020 1021 /* read n-1 byte data */ 1022 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1023 temp |= I2CR_TXAK; 1024 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1025 1026 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1027 /* read n byte data */ 1028 result = i2c_imx_trx_complete(i2c_imx, false); 1029 if (result) 1030 return result; 1031 1032 if (is_lastmsg) { 1033 /* 1034 * It must generate STOP before read I2DR to prevent 1035 * controller from generating another clock cycle 1036 */ 1037 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1038 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1039 if (!(temp & I2CR_MSTA)) 1040 i2c_imx->stopped = 1; 1041 temp &= ~(I2CR_MSTA | I2CR_MTX); 1042 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1043 if (!i2c_imx->stopped) 1044 i2c_imx_bus_busy(i2c_imx, 0, false); 1045 } else { 1046 /* 1047 * For i2c master receiver repeat restart operation like: 1048 * read -> repeat MSTA -> read/write 1049 * The controller must set MTX before read the last byte in 1050 * the first read operation, otherwise the first read cost 1051 * one extra clock cycle. 1052 */ 1053 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1054 temp |= I2CR_MTX; 1055 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1056 } 1057 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1058 1059 return 0; 1060 } 1061 1062 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1063 bool atomic) 1064 { 1065 int i, result; 1066 1067 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1068 __func__, i2c_8bit_addr_from_msg(msgs)); 1069 1070 /* write slave address */ 1071 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1072 result = i2c_imx_trx_complete(i2c_imx, atomic); 1073 if (result) 1074 return result; 1075 result = i2c_imx_acked(i2c_imx); 1076 if (result) 1077 return result; 1078 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1079 1080 /* write data */ 1081 for (i = 0; i < msgs->len; i++) { 1082 dev_dbg(&i2c_imx->adapter.dev, 1083 "<%s> write byte: B%d=0x%X\n", 1084 __func__, i, msgs->buf[i]); 1085 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1086 result = i2c_imx_trx_complete(i2c_imx, atomic); 1087 if (result) 1088 return result; 1089 result = i2c_imx_acked(i2c_imx); 1090 if (result) 1091 return result; 1092 } 1093 return 0; 1094 } 1095 1096 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1097 bool is_lastmsg, bool atomic) 1098 { 1099 int i, result; 1100 unsigned int temp; 1101 int block_data = msgs->flags & I2C_M_RECV_LEN; 1102 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 1103 1104 dev_dbg(&i2c_imx->adapter.dev, 1105 "<%s> write slave address: addr=0x%x\n", 1106 __func__, i2c_8bit_addr_from_msg(msgs)); 1107 1108 /* write slave address */ 1109 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1110 result = i2c_imx_trx_complete(i2c_imx, atomic); 1111 if (result) 1112 return result; 1113 result = i2c_imx_acked(i2c_imx); 1114 if (result) 1115 return result; 1116 1117 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1118 1119 /* setup bus to read data */ 1120 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1121 temp &= ~I2CR_MTX; 1122 1123 /* 1124 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1125 * length is unknown 1126 */ 1127 if ((msgs->len - 1) || block_data) 1128 temp &= ~I2CR_TXAK; 1129 if (use_dma) 1130 temp |= I2CR_DMAEN; 1131 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1132 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1133 1134 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1135 1136 if (use_dma) 1137 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 1138 1139 /* read data */ 1140 for (i = 0; i < msgs->len; i++) { 1141 u8 len = 0; 1142 1143 result = i2c_imx_trx_complete(i2c_imx, atomic); 1144 if (result) 1145 return result; 1146 /* 1147 * First byte is the length of remaining packet 1148 * in the SMBus block data read. Add it to 1149 * msgs->len. 1150 */ 1151 if ((!i) && block_data) { 1152 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1153 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1154 return -EPROTO; 1155 dev_dbg(&i2c_imx->adapter.dev, 1156 "<%s> read length: 0x%X\n", 1157 __func__, len); 1158 msgs->len += len; 1159 } 1160 if (i == (msgs->len - 1)) { 1161 if (is_lastmsg) { 1162 /* 1163 * It must generate STOP before read I2DR to prevent 1164 * controller from generating another clock cycle 1165 */ 1166 dev_dbg(&i2c_imx->adapter.dev, 1167 "<%s> clear MSTA\n", __func__); 1168 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1169 if (!(temp & I2CR_MSTA)) 1170 i2c_imx->stopped = 1; 1171 temp &= ~(I2CR_MSTA | I2CR_MTX); 1172 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1173 if (!i2c_imx->stopped) 1174 i2c_imx_bus_busy(i2c_imx, 0, atomic); 1175 } else { 1176 /* 1177 * For i2c master receiver repeat restart operation like: 1178 * read -> repeat MSTA -> read/write 1179 * The controller must set MTX before read the last byte in 1180 * the first read operation, otherwise the first read cost 1181 * one extra clock cycle. 1182 */ 1183 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1184 temp |= I2CR_MTX; 1185 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1186 } 1187 } else if (i == (msgs->len - 2)) { 1188 dev_dbg(&i2c_imx->adapter.dev, 1189 "<%s> set TXAK\n", __func__); 1190 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1191 temp |= I2CR_TXAK; 1192 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1193 } 1194 if ((!i) && block_data) 1195 msgs->buf[0] = len; 1196 else 1197 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1198 dev_dbg(&i2c_imx->adapter.dev, 1199 "<%s> read byte: B%d=0x%X\n", 1200 __func__, i, msgs->buf[i]); 1201 } 1202 return 0; 1203 } 1204 1205 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1206 struct i2c_msg *msgs, int num, bool atomic) 1207 { 1208 unsigned int i, temp; 1209 int result; 1210 bool is_lastmsg = false; 1211 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1212 1213 /* Start I2C transfer */ 1214 result = i2c_imx_start(i2c_imx, atomic); 1215 if (result) { 1216 /* 1217 * Bus recovery uses gpiod_get_value_cansleep() which is not 1218 * allowed within atomic context. 1219 */ 1220 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1221 i2c_recover_bus(&i2c_imx->adapter); 1222 result = i2c_imx_start(i2c_imx, atomic); 1223 } 1224 } 1225 1226 if (result) 1227 goto fail0; 1228 1229 /* read/write data */ 1230 for (i = 0; i < num; i++) { 1231 if (i == num - 1) 1232 is_lastmsg = true; 1233 1234 if (i) { 1235 dev_dbg(&i2c_imx->adapter.dev, 1236 "<%s> repeated start\n", __func__); 1237 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1238 temp |= I2CR_RSTA; 1239 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1240 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1241 if (result) 1242 goto fail0; 1243 } 1244 dev_dbg(&i2c_imx->adapter.dev, 1245 "<%s> transfer message: %d\n", __func__, i); 1246 /* write/read data */ 1247 #ifdef CONFIG_I2C_DEBUG_BUS 1248 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1249 dev_dbg(&i2c_imx->adapter.dev, 1250 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1251 __func__, 1252 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1253 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1254 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1255 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1256 dev_dbg(&i2c_imx->adapter.dev, 1257 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1258 __func__, 1259 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1260 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1261 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1262 (temp & I2SR_RXAK ? 1 : 0)); 1263 #endif 1264 if (msgs[i].flags & I2C_M_RD) { 1265 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1266 } else { 1267 if (!atomic && 1268 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 1269 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1270 else 1271 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1272 } 1273 if (result) 1274 goto fail0; 1275 } 1276 1277 fail0: 1278 /* Stop I2C transfer */ 1279 i2c_imx_stop(i2c_imx, atomic); 1280 1281 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1282 (result < 0) ? "error" : "success msg", 1283 (result < 0) ? result : num); 1284 /* After data is transferred, switch to slave mode(as a receiver) */ 1285 if (i2c_imx->slave) 1286 i2c_imx_slave_init(i2c_imx); 1287 1288 return (result < 0) ? result : num; 1289 } 1290 1291 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1292 struct i2c_msg *msgs, int num) 1293 { 1294 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1295 int result; 1296 1297 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1298 if (result < 0) 1299 return result; 1300 1301 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1302 1303 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1304 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1305 1306 return result; 1307 } 1308 1309 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1310 struct i2c_msg *msgs, int num) 1311 { 1312 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1313 int result; 1314 1315 result = clk_enable(i2c_imx->clk); 1316 if (result) 1317 return result; 1318 1319 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1320 1321 clk_disable(i2c_imx->clk); 1322 1323 return result; 1324 } 1325 1326 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1327 { 1328 struct imx_i2c_struct *i2c_imx; 1329 1330 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1331 1332 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1333 } 1334 1335 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1336 { 1337 struct imx_i2c_struct *i2c_imx; 1338 1339 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1340 1341 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1342 } 1343 1344 /* 1345 * We switch SCL and SDA to their GPIO function and do some bitbanging 1346 * for bus recovery. These alternative pinmux settings can be 1347 * described in the device tree by a separate pinctrl state "gpio". If 1348 * this is missing this is not a big problem, the only implication is 1349 * that we can't do bus recovery. 1350 */ 1351 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1352 struct platform_device *pdev) 1353 { 1354 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1355 1356 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1357 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1358 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1359 return PTR_ERR(i2c_imx->pinctrl); 1360 } 1361 1362 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1363 PINCTRL_STATE_DEFAULT); 1364 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1365 "gpio"); 1366 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1367 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1368 1369 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1370 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1371 return -EPROBE_DEFER; 1372 } else if (IS_ERR(rinfo->sda_gpiod) || 1373 IS_ERR(rinfo->scl_gpiod) || 1374 IS_ERR(i2c_imx->pinctrl_pins_default) || 1375 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1376 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1377 return 0; 1378 } 1379 1380 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1381 rinfo->sda_gpiod ? ",sda" : ""); 1382 1383 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1384 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1385 rinfo->recover_bus = i2c_generic_scl_recovery; 1386 i2c_imx->adapter.bus_recovery_info = rinfo; 1387 1388 return 0; 1389 } 1390 1391 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1392 { 1393 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1394 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1395 } 1396 1397 static const struct i2c_algorithm i2c_imx_algo = { 1398 .master_xfer = i2c_imx_xfer, 1399 .master_xfer_atomic = i2c_imx_xfer_atomic, 1400 .functionality = i2c_imx_func, 1401 .reg_slave = i2c_imx_reg_slave, 1402 .unreg_slave = i2c_imx_unreg_slave, 1403 }; 1404 1405 static int i2c_imx_probe(struct platform_device *pdev) 1406 { 1407 struct imx_i2c_struct *i2c_imx; 1408 struct resource *res; 1409 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1410 void __iomem *base; 1411 int irq, ret; 1412 dma_addr_t phy_addr; 1413 const struct imx_i2c_hwdata *match; 1414 1415 irq = platform_get_irq(pdev, 0); 1416 if (irq < 0) 1417 return irq; 1418 1419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1420 base = devm_ioremap_resource(&pdev->dev, res); 1421 if (IS_ERR(base)) 1422 return PTR_ERR(base); 1423 1424 phy_addr = (dma_addr_t)res->start; 1425 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1426 if (!i2c_imx) 1427 return -ENOMEM; 1428 1429 spin_lock_init(&i2c_imx->slave_lock); 1430 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 1431 i2c_imx->slave_timer.function = i2c_imx_slave_timeout; 1432 1433 match = device_get_match_data(&pdev->dev); 1434 if (match) 1435 i2c_imx->hwdata = match; 1436 else 1437 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1438 platform_get_device_id(pdev)->driver_data; 1439 1440 /* Setup i2c_imx driver structure */ 1441 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1442 i2c_imx->adapter.owner = THIS_MODULE; 1443 i2c_imx->adapter.algo = &i2c_imx_algo; 1444 i2c_imx->adapter.dev.parent = &pdev->dev; 1445 i2c_imx->adapter.nr = pdev->id; 1446 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1447 i2c_imx->base = base; 1448 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1449 1450 /* Get I2C clock */ 1451 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1452 if (IS_ERR(i2c_imx->clk)) 1453 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1454 "can't get I2C clock\n"); 1455 1456 ret = clk_prepare_enable(i2c_imx->clk); 1457 if (ret) { 1458 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1459 return ret; 1460 } 1461 1462 /* Init queue */ 1463 init_waitqueue_head(&i2c_imx->queue); 1464 1465 /* Set up adapter data */ 1466 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1467 1468 /* Set up platform driver data */ 1469 platform_set_drvdata(pdev, i2c_imx); 1470 1471 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1472 pm_runtime_use_autosuspend(&pdev->dev); 1473 pm_runtime_set_active(&pdev->dev); 1474 pm_runtime_enable(&pdev->dev); 1475 1476 ret = pm_runtime_get_sync(&pdev->dev); 1477 if (ret < 0) 1478 goto rpm_disable; 1479 1480 /* Request IRQ */ 1481 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1482 pdev->name, i2c_imx); 1483 if (ret) { 1484 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1485 goto rpm_disable; 1486 } 1487 1488 /* Set up clock divider */ 1489 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1490 ret = of_property_read_u32(pdev->dev.of_node, 1491 "clock-frequency", &i2c_imx->bitrate); 1492 if (ret < 0 && pdata && pdata->bitrate) 1493 i2c_imx->bitrate = pdata->bitrate; 1494 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1495 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1496 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1497 1498 i2c_imx_reset_regs(i2c_imx); 1499 1500 /* Init optional bus recovery function */ 1501 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1502 /* Give it another chance if pinctrl used is not ready yet */ 1503 if (ret == -EPROBE_DEFER) 1504 goto clk_notifier_unregister; 1505 1506 /* Add I2C adapter */ 1507 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1508 if (ret < 0) 1509 goto clk_notifier_unregister; 1510 1511 pm_runtime_mark_last_busy(&pdev->dev); 1512 pm_runtime_put_autosuspend(&pdev->dev); 1513 1514 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1515 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1516 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1517 i2c_imx->adapter.name); 1518 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1519 1520 /* Init DMA config if supported */ 1521 i2c_imx_dma_request(i2c_imx, phy_addr); 1522 1523 return 0; /* Return OK */ 1524 1525 clk_notifier_unregister: 1526 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1527 free_irq(irq, i2c_imx); 1528 rpm_disable: 1529 pm_runtime_put_noidle(&pdev->dev); 1530 pm_runtime_disable(&pdev->dev); 1531 pm_runtime_set_suspended(&pdev->dev); 1532 pm_runtime_dont_use_autosuspend(&pdev->dev); 1533 clk_disable_unprepare(i2c_imx->clk); 1534 return ret; 1535 } 1536 1537 static int i2c_imx_remove(struct platform_device *pdev) 1538 { 1539 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1540 int irq, ret; 1541 1542 ret = pm_runtime_resume_and_get(&pdev->dev); 1543 if (ret < 0) 1544 return ret; 1545 1546 hrtimer_cancel(&i2c_imx->slave_timer); 1547 1548 /* remove adapter */ 1549 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1550 i2c_del_adapter(&i2c_imx->adapter); 1551 1552 if (i2c_imx->dma) 1553 i2c_imx_dma_free(i2c_imx); 1554 1555 /* setup chip registers to defaults */ 1556 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1557 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1558 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1559 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1560 1561 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1562 irq = platform_get_irq(pdev, 0); 1563 if (irq >= 0) 1564 free_irq(irq, i2c_imx); 1565 clk_disable_unprepare(i2c_imx->clk); 1566 1567 pm_runtime_put_noidle(&pdev->dev); 1568 pm_runtime_disable(&pdev->dev); 1569 1570 return 0; 1571 } 1572 1573 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1574 { 1575 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1576 1577 clk_disable(i2c_imx->clk); 1578 1579 return 0; 1580 } 1581 1582 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1583 { 1584 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1585 int ret; 1586 1587 ret = clk_enable(i2c_imx->clk); 1588 if (ret) 1589 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1590 1591 return ret; 1592 } 1593 1594 static const struct dev_pm_ops i2c_imx_pm_ops = { 1595 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1596 i2c_imx_runtime_resume, NULL) 1597 }; 1598 1599 static struct platform_driver i2c_imx_driver = { 1600 .probe = i2c_imx_probe, 1601 .remove = i2c_imx_remove, 1602 .driver = { 1603 .name = DRIVER_NAME, 1604 .pm = &i2c_imx_pm_ops, 1605 .of_match_table = i2c_imx_dt_ids, 1606 .acpi_match_table = i2c_imx_acpi_ids, 1607 }, 1608 .id_table = imx_i2c_devtype, 1609 }; 1610 1611 static int __init i2c_adap_imx_init(void) 1612 { 1613 return platform_driver_register(&i2c_imx_driver); 1614 } 1615 subsys_initcall(i2c_adap_imx_init); 1616 1617 static void __exit i2c_adap_imx_exit(void) 1618 { 1619 platform_driver_unregister(&i2c_imx_driver); 1620 } 1621 module_exit(i2c_adap_imx_exit); 1622 1623 MODULE_LICENSE("GPL"); 1624 MODULE_AUTHOR("Darius Augulis"); 1625 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1626 MODULE_ALIAS("platform:" DRIVER_NAME); 1627