1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/of_dma.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/platform_data/i2c-imx.h> 46 #include <linux/platform_device.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/sched.h> 49 #include <linux/slab.h> 50 51 /* This will be the driver name the kernel reports */ 52 #define DRIVER_NAME "imx-i2c" 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 /* 78 * All of the layerscape series SoCs support IBIC register. 79 */ 80 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 81 82 #define IMX_I2C_REGSHIFT 2 83 #define VF610_I2C_REGSHIFT 0 84 85 /* Bits of IMX I2C registers */ 86 #define I2SR_RXAK 0x01 87 #define I2SR_IIF 0x02 88 #define I2SR_SRW 0x04 89 #define I2SR_IAL 0x10 90 #define I2SR_IBB 0x20 91 #define I2SR_IAAS 0x40 92 #define I2SR_ICF 0x80 93 #define I2CR_DMAEN 0x02 94 #define I2CR_RSTA 0x04 95 #define I2CR_TXAK 0x08 96 #define I2CR_MTX 0x10 97 #define I2CR_MSTA 0x20 98 #define I2CR_IIEN 0x40 99 #define I2CR_IEN 0x80 100 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 101 102 /* register bits different operating codes definition: 103 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 104 * - write zero to clear(w0c) INT flag on i.MX, 105 * - but write one to clear(w1c) INT flag on Vybrid. 106 * 2) I2CR: I2C module enable operation also differ between SoCs: 107 * - set I2CR_IEN bit enable the module on i.MX, 108 * - but clear I2CR_IEN bit enable the module on Vybrid. 109 */ 110 #define I2SR_CLR_OPCODE_W0C 0x0 111 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 112 #define I2CR_IEN_OPCODE_0 0x0 113 #define I2CR_IEN_OPCODE_1 I2CR_IEN 114 115 #define I2C_PM_TIMEOUT 10 /* ms */ 116 117 /* 118 * sorted list of clock divider, register value pairs 119 * taken from table 26-5, p.26-9, Freescale i.MX 120 * Integrated Portable System Processor Reference Manual 121 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 122 * 123 * Duplicated divider values removed from list 124 */ 125 struct imx_i2c_clk_pair { 126 u16 div; 127 u16 val; 128 }; 129 130 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 131 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 132 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 133 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 134 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 135 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 136 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 137 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 138 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 139 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 140 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 141 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 142 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 143 { 3072, 0x1E }, { 3840, 0x1F } 144 }; 145 146 /* Vybrid VF610 clock divider, register value pairs */ 147 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 148 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 149 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 150 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 151 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 152 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 153 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 154 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 155 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 156 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 157 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 158 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 159 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 160 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 161 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 162 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 163 }; 164 165 enum imx_i2c_type { 166 IMX1_I2C, 167 IMX21_I2C, 168 VF610_I2C, 169 }; 170 171 struct imx_i2c_hwdata { 172 enum imx_i2c_type devtype; 173 unsigned int regshift; 174 struct imx_i2c_clk_pair *clk_div; 175 unsigned int ndivs; 176 unsigned int i2sr_clr_opcode; 177 unsigned int i2cr_ien_opcode; 178 }; 179 180 struct imx_i2c_dma { 181 struct dma_chan *chan_tx; 182 struct dma_chan *chan_rx; 183 struct dma_chan *chan_using; 184 struct completion cmd_complete; 185 dma_addr_t dma_buf; 186 unsigned int dma_len; 187 enum dma_transfer_direction dma_transfer_dir; 188 enum dma_data_direction dma_data_dir; 189 }; 190 191 struct imx_i2c_struct { 192 struct i2c_adapter adapter; 193 struct clk *clk; 194 struct notifier_block clk_change_nb; 195 void __iomem *base; 196 wait_queue_head_t queue; 197 unsigned long i2csr; 198 unsigned int disable_delay; 199 int stopped; 200 unsigned int ifdr; /* IMX_I2C_IFDR */ 201 unsigned int cur_clk; 202 unsigned int bitrate; 203 const struct imx_i2c_hwdata *hwdata; 204 struct i2c_bus_recovery_info rinfo; 205 206 struct pinctrl *pinctrl; 207 struct pinctrl_state *pinctrl_pins_default; 208 struct pinctrl_state *pinctrl_pins_gpio; 209 210 struct imx_i2c_dma *dma; 211 struct i2c_client *slave; 212 enum i2c_slave_event last_slave_event; 213 }; 214 215 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 216 .devtype = IMX1_I2C, 217 .regshift = IMX_I2C_REGSHIFT, 218 .clk_div = imx_i2c_clk_div, 219 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 220 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 221 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 222 223 }; 224 225 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 226 .devtype = IMX21_I2C, 227 .regshift = IMX_I2C_REGSHIFT, 228 .clk_div = imx_i2c_clk_div, 229 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 230 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 231 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 232 233 }; 234 235 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 236 .devtype = VF610_I2C, 237 .regshift = VF610_I2C_REGSHIFT, 238 .clk_div = vf610_i2c_clk_div, 239 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 240 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 241 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 242 243 }; 244 245 static const struct platform_device_id imx_i2c_devtype[] = { 246 { 247 .name = "imx1-i2c", 248 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 249 }, { 250 .name = "imx21-i2c", 251 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 252 }, { 253 /* sentinel */ 254 } 255 }; 256 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 257 258 static const struct of_device_id i2c_imx_dt_ids[] = { 259 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 260 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 261 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 262 { /* sentinel */ } 263 }; 264 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 265 266 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 267 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 268 { } 269 }; 270 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 271 272 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 273 { 274 return i2c_imx->hwdata->devtype == IMX1_I2C; 275 } 276 277 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 278 { 279 return i2c_imx->hwdata->devtype == VF610_I2C; 280 } 281 282 static inline void imx_i2c_write_reg(unsigned int val, 283 struct imx_i2c_struct *i2c_imx, unsigned int reg) 284 { 285 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 286 } 287 288 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 289 unsigned int reg) 290 { 291 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 292 } 293 294 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 295 { 296 unsigned int temp; 297 298 /* 299 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 300 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 301 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 302 */ 303 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 304 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 305 } 306 307 /* Set up i2c controller register and i2c status register to default value. */ 308 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 309 { 310 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 311 i2c_imx, IMX_I2C_I2CR); 312 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 313 } 314 315 /* Functions for DMA support */ 316 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 317 dma_addr_t phy_addr) 318 { 319 struct imx_i2c_dma *dma; 320 struct dma_slave_config dma_sconfig; 321 struct device *dev = &i2c_imx->adapter.dev; 322 int ret; 323 324 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 325 if (!dma) 326 return; 327 328 dma->chan_tx = dma_request_chan(dev, "tx"); 329 if (IS_ERR(dma->chan_tx)) { 330 ret = PTR_ERR(dma->chan_tx); 331 if (ret != -ENODEV && ret != -EPROBE_DEFER) 332 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 333 goto fail_al; 334 } 335 336 dma_sconfig.dst_addr = phy_addr + 337 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 338 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 339 dma_sconfig.dst_maxburst = 1; 340 dma_sconfig.direction = DMA_MEM_TO_DEV; 341 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 342 if (ret < 0) { 343 dev_err(dev, "can't configure tx channel (%d)\n", ret); 344 goto fail_tx; 345 } 346 347 dma->chan_rx = dma_request_chan(dev, "rx"); 348 if (IS_ERR(dma->chan_rx)) { 349 ret = PTR_ERR(dma->chan_rx); 350 if (ret != -ENODEV && ret != -EPROBE_DEFER) 351 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 352 goto fail_tx; 353 } 354 355 dma_sconfig.src_addr = phy_addr + 356 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 357 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 358 dma_sconfig.src_maxburst = 1; 359 dma_sconfig.direction = DMA_DEV_TO_MEM; 360 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 361 if (ret < 0) { 362 dev_err(dev, "can't configure rx channel (%d)\n", ret); 363 goto fail_rx; 364 } 365 366 i2c_imx->dma = dma; 367 init_completion(&dma->cmd_complete); 368 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 369 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 370 371 return; 372 373 fail_rx: 374 dma_release_channel(dma->chan_rx); 375 fail_tx: 376 dma_release_channel(dma->chan_tx); 377 fail_al: 378 devm_kfree(dev, dma); 379 } 380 381 static void i2c_imx_dma_callback(void *arg) 382 { 383 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 384 struct imx_i2c_dma *dma = i2c_imx->dma; 385 386 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 387 dma->dma_len, dma->dma_data_dir); 388 complete(&dma->cmd_complete); 389 } 390 391 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 392 struct i2c_msg *msgs) 393 { 394 struct imx_i2c_dma *dma = i2c_imx->dma; 395 struct dma_async_tx_descriptor *txdesc; 396 struct device *dev = &i2c_imx->adapter.dev; 397 struct device *chan_dev = dma->chan_using->device->dev; 398 399 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 400 dma->dma_len, dma->dma_data_dir); 401 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 402 dev_err(dev, "DMA mapping failed\n"); 403 goto err_map; 404 } 405 406 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 407 dma->dma_len, dma->dma_transfer_dir, 408 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 409 if (!txdesc) { 410 dev_err(dev, "Not able to get desc for DMA xfer\n"); 411 goto err_desc; 412 } 413 414 reinit_completion(&dma->cmd_complete); 415 txdesc->callback = i2c_imx_dma_callback; 416 txdesc->callback_param = i2c_imx; 417 if (dma_submit_error(dmaengine_submit(txdesc))) { 418 dev_err(dev, "DMA submit failed\n"); 419 goto err_submit; 420 } 421 422 dma_async_issue_pending(dma->chan_using); 423 return 0; 424 425 err_submit: 426 dmaengine_terminate_sync(dma->chan_using); 427 err_desc: 428 dma_unmap_single(chan_dev, dma->dma_buf, 429 dma->dma_len, dma->dma_data_dir); 430 err_map: 431 return -EINVAL; 432 } 433 434 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 435 { 436 struct imx_i2c_dma *dma = i2c_imx->dma; 437 438 dma->dma_buf = 0; 439 dma->dma_len = 0; 440 441 dma_release_channel(dma->chan_tx); 442 dma->chan_tx = NULL; 443 444 dma_release_channel(dma->chan_rx); 445 dma->chan_rx = NULL; 446 447 dma->chan_using = NULL; 448 } 449 450 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 451 { 452 unsigned long orig_jiffies = jiffies; 453 unsigned int temp; 454 455 while (1) { 456 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 457 458 /* check for arbitration lost */ 459 if (temp & I2SR_IAL) { 460 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 461 return -EAGAIN; 462 } 463 464 if (for_busy && (temp & I2SR_IBB)) { 465 i2c_imx->stopped = 0; 466 break; 467 } 468 if (!for_busy && !(temp & I2SR_IBB)) { 469 i2c_imx->stopped = 1; 470 break; 471 } 472 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 473 dev_dbg(&i2c_imx->adapter.dev, 474 "<%s> I2C bus is busy\n", __func__); 475 return -ETIMEDOUT; 476 } 477 if (atomic) 478 udelay(100); 479 else 480 schedule(); 481 } 482 483 return 0; 484 } 485 486 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 487 { 488 if (atomic) { 489 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 490 unsigned int regval; 491 492 /* 493 * The formula for the poll timeout is documented in the RM 494 * Rev.5 on page 1878: 495 * T_min = 10/F_scl 496 * Set the value hard as it is done for the non-atomic use-case. 497 * Use 10 kHz for the calculation since this is the minimum 498 * allowed SMBus frequency. Also add an offset of 100us since it 499 * turned out that the I2SR_IIF bit isn't set correctly within 500 * the minimum timeout in polling mode. 501 */ 502 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 503 i2c_imx->i2csr = regval; 504 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 505 } else { 506 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 507 } 508 509 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 510 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 511 return -ETIMEDOUT; 512 } 513 514 /* check for arbitration lost */ 515 if (i2c_imx->i2csr & I2SR_IAL) { 516 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 517 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 518 519 i2c_imx->i2csr = 0; 520 return -EAGAIN; 521 } 522 523 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 524 i2c_imx->i2csr = 0; 525 return 0; 526 } 527 528 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 529 { 530 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 531 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 532 return -ENXIO; /* No ACK */ 533 } 534 535 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 536 return 0; 537 } 538 539 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 540 unsigned int i2c_clk_rate) 541 { 542 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 543 unsigned int div; 544 int i; 545 546 /* Divider value calculation */ 547 if (i2c_imx->cur_clk == i2c_clk_rate) 548 return; 549 550 i2c_imx->cur_clk = i2c_clk_rate; 551 552 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 553 if (div < i2c_clk_div[0].div) 554 i = 0; 555 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 556 i = i2c_imx->hwdata->ndivs - 1; 557 else 558 for (i = 0; i2c_clk_div[i].div < div; i++) 559 ; 560 561 /* Store divider value */ 562 i2c_imx->ifdr = i2c_clk_div[i].val; 563 564 /* 565 * There dummy delay is calculated. 566 * It should be about one I2C clock period long. 567 * This delay is used in I2C bus disable function 568 * to fix chip hardware bug. 569 */ 570 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 571 i2c_clk_rate / 2); 572 573 #ifdef CONFIG_I2C_DEBUG_BUS 574 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 575 i2c_clk_rate, div); 576 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 577 i2c_clk_div[i].val, i2c_clk_div[i].div); 578 #endif 579 } 580 581 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 582 unsigned long action, void *data) 583 { 584 struct clk_notifier_data *ndata = data; 585 struct imx_i2c_struct *i2c_imx = container_of(nb, 586 struct imx_i2c_struct, 587 clk_change_nb); 588 589 if (action & POST_RATE_CHANGE) 590 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 591 592 return NOTIFY_OK; 593 } 594 595 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 596 { 597 unsigned int temp = 0; 598 int result; 599 600 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 601 /* Enable I2C controller */ 602 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 603 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 604 605 /* Wait controller to be stable */ 606 if (atomic) 607 udelay(50); 608 else 609 usleep_range(50, 150); 610 611 /* Start I2C transaction */ 612 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 613 temp |= I2CR_MSTA; 614 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 615 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 616 if (result) 617 return result; 618 619 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 620 if (atomic) 621 temp &= ~I2CR_IIEN; /* Disable interrupt */ 622 623 temp &= ~I2CR_DMAEN; 624 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 625 return result; 626 } 627 628 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 629 { 630 unsigned int temp = 0; 631 632 if (!i2c_imx->stopped) { 633 /* Stop I2C transaction */ 634 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 635 if (!(temp & I2CR_MSTA)) 636 i2c_imx->stopped = 1; 637 temp &= ~(I2CR_MSTA | I2CR_MTX); 638 if (i2c_imx->dma) 639 temp &= ~I2CR_DMAEN; 640 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 641 } 642 if (is_imx1_i2c(i2c_imx)) { 643 /* 644 * This delay caused by an i.MXL hardware bug. 645 * If no (or too short) delay, no "STOP" bit will be generated. 646 */ 647 udelay(i2c_imx->disable_delay); 648 } 649 650 if (!i2c_imx->stopped) 651 i2c_imx_bus_busy(i2c_imx, 0, atomic); 652 653 /* Disable I2C controller */ 654 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 655 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 656 } 657 658 /* 659 * Enable bus idle interrupts 660 * Note: IBIC register will be cleared after disabled i2c module. 661 * All of layerscape series SoCs support IBIC register. 662 */ 663 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 664 { 665 if (is_vf610_i2c(i2c_imx)) { 666 unsigned int temp; 667 668 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 669 temp |= IBIC_BIIE; 670 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 671 } 672 } 673 674 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 675 enum i2c_slave_event event, u8 *val) 676 { 677 i2c_slave_event(i2c_imx->slave, event, val); 678 i2c_imx->last_slave_event = event; 679 } 680 681 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 682 { 683 u8 val; 684 685 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 686 switch (i2c_imx->last_slave_event) { 687 case I2C_SLAVE_READ_REQUESTED: 688 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 689 &val); 690 break; 691 692 case I2C_SLAVE_WRITE_REQUESTED: 693 case I2C_SLAVE_READ_PROCESSED: 694 case I2C_SLAVE_WRITE_RECEIVED: 695 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 696 break; 697 698 case I2C_SLAVE_STOP: 699 break; 700 } 701 } 702 } 703 704 static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, 705 unsigned int status, unsigned int ctl) 706 { 707 u8 value; 708 709 if (status & I2SR_IAL) { /* Arbitration lost */ 710 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 711 if (!(status & I2SR_IAAS)) 712 return IRQ_HANDLED; 713 } 714 715 if (status & I2SR_IAAS) { /* Addressed as a slave */ 716 i2c_imx_slave_finish_op(i2c_imx); 717 if (status & I2SR_SRW) { /* Master wants to read from us*/ 718 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 719 i2c_imx_slave_event(i2c_imx, 720 I2C_SLAVE_READ_REQUESTED, &value); 721 722 /* Slave transmit */ 723 ctl |= I2CR_MTX; 724 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 725 726 /* Send data */ 727 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 728 } else { /* Master wants to write to us */ 729 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 730 i2c_imx_slave_event(i2c_imx, 731 I2C_SLAVE_WRITE_REQUESTED, &value); 732 733 /* Slave receive */ 734 ctl &= ~I2CR_MTX; 735 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 736 /* Dummy read */ 737 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 738 } 739 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 740 if (status & I2SR_IBB) { /* No STOP signal detected */ 741 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 742 i2c_imx_slave_event(i2c_imx, 743 I2C_SLAVE_WRITE_RECEIVED, &value); 744 } else { /* STOP signal is detected */ 745 dev_dbg(&i2c_imx->adapter.dev, 746 "STOP signal detected"); 747 i2c_imx_slave_event(i2c_imx, 748 I2C_SLAVE_STOP, &value); 749 } 750 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 751 ctl |= I2CR_MTX; 752 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 753 754 i2c_imx_slave_event(i2c_imx, 755 I2C_SLAVE_READ_PROCESSED, &value); 756 757 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 758 } else { /* Transmit mode received NAK */ 759 ctl &= ~I2CR_MTX; 760 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 761 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 762 } 763 764 return IRQ_HANDLED; 765 } 766 767 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 768 { 769 int temp; 770 771 /* Set slave addr. */ 772 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 773 774 i2c_imx_reset_regs(i2c_imx); 775 776 /* Enable module */ 777 temp = i2c_imx->hwdata->i2cr_ien_opcode; 778 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 779 780 /* Enable interrupt from i2c module */ 781 temp |= I2CR_IIEN; 782 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 783 784 i2c_imx_enable_bus_idle(i2c_imx); 785 } 786 787 static int i2c_imx_reg_slave(struct i2c_client *client) 788 { 789 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 790 int ret; 791 792 if (i2c_imx->slave) 793 return -EBUSY; 794 795 i2c_imx->slave = client; 796 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 797 798 /* Resume */ 799 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 800 if (ret < 0) { 801 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 802 return ret; 803 } 804 805 i2c_imx_slave_init(i2c_imx); 806 807 return 0; 808 } 809 810 static int i2c_imx_unreg_slave(struct i2c_client *client) 811 { 812 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 813 int ret; 814 815 if (!i2c_imx->slave) 816 return -EINVAL; 817 818 /* Reset slave address. */ 819 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 820 821 i2c_imx_reset_regs(i2c_imx); 822 823 i2c_imx->slave = NULL; 824 825 /* Suspend */ 826 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 827 if (ret < 0) 828 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 829 830 return ret; 831 } 832 833 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 834 { 835 /* save status register */ 836 i2c_imx->i2csr = status; 837 wake_up(&i2c_imx->queue); 838 839 return IRQ_HANDLED; 840 } 841 842 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 843 { 844 struct imx_i2c_struct *i2c_imx = dev_id; 845 unsigned int ctl, status; 846 847 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 848 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 849 850 if (status & I2SR_IIF) { 851 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 852 if (i2c_imx->slave) { 853 if (!(ctl & I2CR_MSTA)) { 854 return i2c_imx_slave_isr(i2c_imx, status, ctl); 855 } else if (i2c_imx->last_slave_event != 856 I2C_SLAVE_STOP) { 857 i2c_imx_slave_finish_op(i2c_imx); 858 } 859 } 860 return i2c_imx_master_isr(i2c_imx, status); 861 } 862 863 return IRQ_NONE; 864 } 865 866 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 867 struct i2c_msg *msgs) 868 { 869 int result; 870 unsigned long time_left; 871 unsigned int temp = 0; 872 unsigned long orig_jiffies = jiffies; 873 struct imx_i2c_dma *dma = i2c_imx->dma; 874 struct device *dev = &i2c_imx->adapter.dev; 875 876 dma->chan_using = dma->chan_tx; 877 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 878 dma->dma_data_dir = DMA_TO_DEVICE; 879 dma->dma_len = msgs->len - 1; 880 result = i2c_imx_dma_xfer(i2c_imx, msgs); 881 if (result) 882 return result; 883 884 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 885 temp |= I2CR_DMAEN; 886 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 887 888 /* 889 * Write slave address. 890 * The first byte must be transmitted by the CPU. 891 */ 892 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 893 time_left = wait_for_completion_timeout( 894 &i2c_imx->dma->cmd_complete, 895 msecs_to_jiffies(DMA_TIMEOUT)); 896 if (time_left == 0) { 897 dmaengine_terminate_sync(dma->chan_using); 898 return -ETIMEDOUT; 899 } 900 901 /* Waiting for transfer complete. */ 902 while (1) { 903 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 904 if (temp & I2SR_ICF) 905 break; 906 if (time_after(jiffies, orig_jiffies + 907 msecs_to_jiffies(DMA_TIMEOUT))) { 908 dev_dbg(dev, "<%s> Timeout\n", __func__); 909 return -ETIMEDOUT; 910 } 911 schedule(); 912 } 913 914 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 915 temp &= ~I2CR_DMAEN; 916 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 917 918 /* The last data byte must be transferred by the CPU. */ 919 imx_i2c_write_reg(msgs->buf[msgs->len-1], 920 i2c_imx, IMX_I2C_I2DR); 921 result = i2c_imx_trx_complete(i2c_imx, false); 922 if (result) 923 return result; 924 925 return i2c_imx_acked(i2c_imx); 926 } 927 928 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 929 struct i2c_msg *msgs, bool is_lastmsg) 930 { 931 int result; 932 unsigned long time_left; 933 unsigned int temp; 934 unsigned long orig_jiffies = jiffies; 935 struct imx_i2c_dma *dma = i2c_imx->dma; 936 struct device *dev = &i2c_imx->adapter.dev; 937 938 939 dma->chan_using = dma->chan_rx; 940 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 941 dma->dma_data_dir = DMA_FROM_DEVICE; 942 /* The last two data bytes must be transferred by the CPU. */ 943 dma->dma_len = msgs->len - 2; 944 result = i2c_imx_dma_xfer(i2c_imx, msgs); 945 if (result) 946 return result; 947 948 time_left = wait_for_completion_timeout( 949 &i2c_imx->dma->cmd_complete, 950 msecs_to_jiffies(DMA_TIMEOUT)); 951 if (time_left == 0) { 952 dmaengine_terminate_sync(dma->chan_using); 953 return -ETIMEDOUT; 954 } 955 956 /* waiting for transfer complete. */ 957 while (1) { 958 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 959 if (temp & I2SR_ICF) 960 break; 961 if (time_after(jiffies, orig_jiffies + 962 msecs_to_jiffies(DMA_TIMEOUT))) { 963 dev_dbg(dev, "<%s> Timeout\n", __func__); 964 return -ETIMEDOUT; 965 } 966 schedule(); 967 } 968 969 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 970 temp &= ~I2CR_DMAEN; 971 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 972 973 /* read n-1 byte data */ 974 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 975 temp |= I2CR_TXAK; 976 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 977 978 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 979 /* read n byte data */ 980 result = i2c_imx_trx_complete(i2c_imx, false); 981 if (result) 982 return result; 983 984 if (is_lastmsg) { 985 /* 986 * It must generate STOP before read I2DR to prevent 987 * controller from generating another clock cycle 988 */ 989 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 990 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 991 if (!(temp & I2CR_MSTA)) 992 i2c_imx->stopped = 1; 993 temp &= ~(I2CR_MSTA | I2CR_MTX); 994 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 995 if (!i2c_imx->stopped) 996 i2c_imx_bus_busy(i2c_imx, 0, false); 997 } else { 998 /* 999 * For i2c master receiver repeat restart operation like: 1000 * read -> repeat MSTA -> read/write 1001 * The controller must set MTX before read the last byte in 1002 * the first read operation, otherwise the first read cost 1003 * one extra clock cycle. 1004 */ 1005 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1006 temp |= I2CR_MTX; 1007 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1008 } 1009 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1010 1011 return 0; 1012 } 1013 1014 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1015 bool atomic) 1016 { 1017 int i, result; 1018 1019 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1020 __func__, i2c_8bit_addr_from_msg(msgs)); 1021 1022 /* write slave address */ 1023 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1024 result = i2c_imx_trx_complete(i2c_imx, atomic); 1025 if (result) 1026 return result; 1027 result = i2c_imx_acked(i2c_imx); 1028 if (result) 1029 return result; 1030 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1031 1032 /* write data */ 1033 for (i = 0; i < msgs->len; i++) { 1034 dev_dbg(&i2c_imx->adapter.dev, 1035 "<%s> write byte: B%d=0x%X\n", 1036 __func__, i, msgs->buf[i]); 1037 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1038 result = i2c_imx_trx_complete(i2c_imx, atomic); 1039 if (result) 1040 return result; 1041 result = i2c_imx_acked(i2c_imx); 1042 if (result) 1043 return result; 1044 } 1045 return 0; 1046 } 1047 1048 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1049 bool is_lastmsg, bool atomic) 1050 { 1051 int i, result; 1052 unsigned int temp; 1053 int block_data = msgs->flags & I2C_M_RECV_LEN; 1054 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 1055 1056 dev_dbg(&i2c_imx->adapter.dev, 1057 "<%s> write slave address: addr=0x%x\n", 1058 __func__, i2c_8bit_addr_from_msg(msgs)); 1059 1060 /* write slave address */ 1061 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1062 result = i2c_imx_trx_complete(i2c_imx, atomic); 1063 if (result) 1064 return result; 1065 result = i2c_imx_acked(i2c_imx); 1066 if (result) 1067 return result; 1068 1069 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1070 1071 /* setup bus to read data */ 1072 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1073 temp &= ~I2CR_MTX; 1074 1075 /* 1076 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1077 * length is unknown 1078 */ 1079 if ((msgs->len - 1) || block_data) 1080 temp &= ~I2CR_TXAK; 1081 if (use_dma) 1082 temp |= I2CR_DMAEN; 1083 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1084 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1085 1086 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1087 1088 if (use_dma) 1089 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 1090 1091 /* read data */ 1092 for (i = 0; i < msgs->len; i++) { 1093 u8 len = 0; 1094 1095 result = i2c_imx_trx_complete(i2c_imx, atomic); 1096 if (result) 1097 return result; 1098 /* 1099 * First byte is the length of remaining packet 1100 * in the SMBus block data read. Add it to 1101 * msgs->len. 1102 */ 1103 if ((!i) && block_data) { 1104 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1105 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1106 return -EPROTO; 1107 dev_dbg(&i2c_imx->adapter.dev, 1108 "<%s> read length: 0x%X\n", 1109 __func__, len); 1110 msgs->len += len; 1111 } 1112 if (i == (msgs->len - 1)) { 1113 if (is_lastmsg) { 1114 /* 1115 * It must generate STOP before read I2DR to prevent 1116 * controller from generating another clock cycle 1117 */ 1118 dev_dbg(&i2c_imx->adapter.dev, 1119 "<%s> clear MSTA\n", __func__); 1120 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1121 if (!(temp & I2CR_MSTA)) 1122 i2c_imx->stopped = 1; 1123 temp &= ~(I2CR_MSTA | I2CR_MTX); 1124 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1125 if (!i2c_imx->stopped) 1126 i2c_imx_bus_busy(i2c_imx, 0, atomic); 1127 } else { 1128 /* 1129 * For i2c master receiver repeat restart operation like: 1130 * read -> repeat MSTA -> read/write 1131 * The controller must set MTX before read the last byte in 1132 * the first read operation, otherwise the first read cost 1133 * one extra clock cycle. 1134 */ 1135 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1136 temp |= I2CR_MTX; 1137 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1138 } 1139 } else if (i == (msgs->len - 2)) { 1140 dev_dbg(&i2c_imx->adapter.dev, 1141 "<%s> set TXAK\n", __func__); 1142 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1143 temp |= I2CR_TXAK; 1144 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1145 } 1146 if ((!i) && block_data) 1147 msgs->buf[0] = len; 1148 else 1149 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1150 dev_dbg(&i2c_imx->adapter.dev, 1151 "<%s> read byte: B%d=0x%X\n", 1152 __func__, i, msgs->buf[i]); 1153 } 1154 return 0; 1155 } 1156 1157 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1158 struct i2c_msg *msgs, int num, bool atomic) 1159 { 1160 unsigned int i, temp; 1161 int result; 1162 bool is_lastmsg = false; 1163 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1164 1165 /* Start I2C transfer */ 1166 result = i2c_imx_start(i2c_imx, atomic); 1167 if (result) { 1168 /* 1169 * Bus recovery uses gpiod_get_value_cansleep() which is not 1170 * allowed within atomic context. 1171 */ 1172 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1173 i2c_recover_bus(&i2c_imx->adapter); 1174 result = i2c_imx_start(i2c_imx, atomic); 1175 } 1176 } 1177 1178 if (result) 1179 goto fail0; 1180 1181 /* read/write data */ 1182 for (i = 0; i < num; i++) { 1183 if (i == num - 1) 1184 is_lastmsg = true; 1185 1186 if (i) { 1187 dev_dbg(&i2c_imx->adapter.dev, 1188 "<%s> repeated start\n", __func__); 1189 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1190 temp |= I2CR_RSTA; 1191 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1192 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1193 if (result) 1194 goto fail0; 1195 } 1196 dev_dbg(&i2c_imx->adapter.dev, 1197 "<%s> transfer message: %d\n", __func__, i); 1198 /* write/read data */ 1199 #ifdef CONFIG_I2C_DEBUG_BUS 1200 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1201 dev_dbg(&i2c_imx->adapter.dev, 1202 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1203 __func__, 1204 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1205 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1206 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1207 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1208 dev_dbg(&i2c_imx->adapter.dev, 1209 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1210 __func__, 1211 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1212 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1213 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1214 (temp & I2SR_RXAK ? 1 : 0)); 1215 #endif 1216 if (msgs[i].flags & I2C_M_RD) { 1217 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1218 } else { 1219 if (!atomic && 1220 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 1221 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1222 else 1223 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1224 } 1225 if (result) 1226 goto fail0; 1227 } 1228 1229 fail0: 1230 /* Stop I2C transfer */ 1231 i2c_imx_stop(i2c_imx, atomic); 1232 1233 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1234 (result < 0) ? "error" : "success msg", 1235 (result < 0) ? result : num); 1236 /* After data is transferred, switch to slave mode(as a receiver) */ 1237 if (i2c_imx->slave) 1238 i2c_imx_slave_init(i2c_imx); 1239 1240 return (result < 0) ? result : num; 1241 } 1242 1243 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1244 struct i2c_msg *msgs, int num) 1245 { 1246 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1247 int result; 1248 1249 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1250 if (result < 0) 1251 return result; 1252 1253 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1254 1255 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1256 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1257 1258 return result; 1259 } 1260 1261 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1262 struct i2c_msg *msgs, int num) 1263 { 1264 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1265 int result; 1266 1267 result = clk_enable(i2c_imx->clk); 1268 if (result) 1269 return result; 1270 1271 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1272 1273 clk_disable(i2c_imx->clk); 1274 1275 return result; 1276 } 1277 1278 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1279 { 1280 struct imx_i2c_struct *i2c_imx; 1281 1282 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1283 1284 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1285 } 1286 1287 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1288 { 1289 struct imx_i2c_struct *i2c_imx; 1290 1291 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1292 1293 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1294 } 1295 1296 /* 1297 * We switch SCL and SDA to their GPIO function and do some bitbanging 1298 * for bus recovery. These alternative pinmux settings can be 1299 * described in the device tree by a separate pinctrl state "gpio". If 1300 * this is missing this is not a big problem, the only implication is 1301 * that we can't do bus recovery. 1302 */ 1303 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1304 struct platform_device *pdev) 1305 { 1306 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1307 1308 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1309 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1310 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1311 return PTR_ERR(i2c_imx->pinctrl); 1312 } 1313 1314 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1315 PINCTRL_STATE_DEFAULT); 1316 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1317 "gpio"); 1318 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1319 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1320 1321 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1322 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1323 return -EPROBE_DEFER; 1324 } else if (IS_ERR(rinfo->sda_gpiod) || 1325 IS_ERR(rinfo->scl_gpiod) || 1326 IS_ERR(i2c_imx->pinctrl_pins_default) || 1327 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1328 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1329 return 0; 1330 } 1331 1332 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1333 rinfo->sda_gpiod ? ",sda" : ""); 1334 1335 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1336 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1337 rinfo->recover_bus = i2c_generic_scl_recovery; 1338 i2c_imx->adapter.bus_recovery_info = rinfo; 1339 1340 return 0; 1341 } 1342 1343 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1344 { 1345 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1346 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1347 } 1348 1349 static const struct i2c_algorithm i2c_imx_algo = { 1350 .master_xfer = i2c_imx_xfer, 1351 .master_xfer_atomic = i2c_imx_xfer_atomic, 1352 .functionality = i2c_imx_func, 1353 .reg_slave = i2c_imx_reg_slave, 1354 .unreg_slave = i2c_imx_unreg_slave, 1355 }; 1356 1357 static int i2c_imx_probe(struct platform_device *pdev) 1358 { 1359 struct imx_i2c_struct *i2c_imx; 1360 struct resource *res; 1361 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1362 void __iomem *base; 1363 int irq, ret; 1364 dma_addr_t phy_addr; 1365 const struct imx_i2c_hwdata *match; 1366 1367 irq = platform_get_irq(pdev, 0); 1368 if (irq < 0) 1369 return irq; 1370 1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1372 base = devm_ioremap_resource(&pdev->dev, res); 1373 if (IS_ERR(base)) 1374 return PTR_ERR(base); 1375 1376 phy_addr = (dma_addr_t)res->start; 1377 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1378 if (!i2c_imx) 1379 return -ENOMEM; 1380 1381 match = device_get_match_data(&pdev->dev); 1382 if (match) 1383 i2c_imx->hwdata = match; 1384 else 1385 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1386 platform_get_device_id(pdev)->driver_data; 1387 1388 /* Setup i2c_imx driver structure */ 1389 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1390 i2c_imx->adapter.owner = THIS_MODULE; 1391 i2c_imx->adapter.algo = &i2c_imx_algo; 1392 i2c_imx->adapter.dev.parent = &pdev->dev; 1393 i2c_imx->adapter.nr = pdev->id; 1394 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1395 i2c_imx->base = base; 1396 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1397 1398 /* Get I2C clock */ 1399 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1400 if (IS_ERR(i2c_imx->clk)) 1401 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1402 "can't get I2C clock\n"); 1403 1404 ret = clk_prepare_enable(i2c_imx->clk); 1405 if (ret) { 1406 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1407 return ret; 1408 } 1409 1410 /* Init queue */ 1411 init_waitqueue_head(&i2c_imx->queue); 1412 1413 /* Set up adapter data */ 1414 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1415 1416 /* Set up platform driver data */ 1417 platform_set_drvdata(pdev, i2c_imx); 1418 1419 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1420 pm_runtime_use_autosuspend(&pdev->dev); 1421 pm_runtime_set_active(&pdev->dev); 1422 pm_runtime_enable(&pdev->dev); 1423 1424 ret = pm_runtime_get_sync(&pdev->dev); 1425 if (ret < 0) 1426 goto rpm_disable; 1427 1428 /* Request IRQ */ 1429 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1430 pdev->name, i2c_imx); 1431 if (ret) { 1432 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1433 goto rpm_disable; 1434 } 1435 1436 /* Set up clock divider */ 1437 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1438 ret = of_property_read_u32(pdev->dev.of_node, 1439 "clock-frequency", &i2c_imx->bitrate); 1440 if (ret < 0 && pdata && pdata->bitrate) 1441 i2c_imx->bitrate = pdata->bitrate; 1442 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1443 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1444 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1445 1446 i2c_imx_reset_regs(i2c_imx); 1447 1448 /* Init optional bus recovery function */ 1449 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1450 /* Give it another chance if pinctrl used is not ready yet */ 1451 if (ret == -EPROBE_DEFER) 1452 goto clk_notifier_unregister; 1453 1454 /* Add I2C adapter */ 1455 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1456 if (ret < 0) 1457 goto clk_notifier_unregister; 1458 1459 pm_runtime_mark_last_busy(&pdev->dev); 1460 pm_runtime_put_autosuspend(&pdev->dev); 1461 1462 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1463 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1464 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1465 i2c_imx->adapter.name); 1466 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1467 1468 /* Init DMA config if supported */ 1469 i2c_imx_dma_request(i2c_imx, phy_addr); 1470 1471 return 0; /* Return OK */ 1472 1473 clk_notifier_unregister: 1474 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1475 free_irq(irq, i2c_imx); 1476 rpm_disable: 1477 pm_runtime_put_noidle(&pdev->dev); 1478 pm_runtime_disable(&pdev->dev); 1479 pm_runtime_set_suspended(&pdev->dev); 1480 pm_runtime_dont_use_autosuspend(&pdev->dev); 1481 clk_disable_unprepare(i2c_imx->clk); 1482 return ret; 1483 } 1484 1485 static int i2c_imx_remove(struct platform_device *pdev) 1486 { 1487 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1488 int irq, ret; 1489 1490 ret = pm_runtime_resume_and_get(&pdev->dev); 1491 if (ret < 0) 1492 return ret; 1493 1494 /* remove adapter */ 1495 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1496 i2c_del_adapter(&i2c_imx->adapter); 1497 1498 if (i2c_imx->dma) 1499 i2c_imx_dma_free(i2c_imx); 1500 1501 /* setup chip registers to defaults */ 1502 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1503 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1504 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1505 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1506 1507 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1508 irq = platform_get_irq(pdev, 0); 1509 if (irq >= 0) 1510 free_irq(irq, i2c_imx); 1511 clk_disable_unprepare(i2c_imx->clk); 1512 1513 pm_runtime_put_noidle(&pdev->dev); 1514 pm_runtime_disable(&pdev->dev); 1515 1516 return 0; 1517 } 1518 1519 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1520 { 1521 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1522 1523 clk_disable(i2c_imx->clk); 1524 1525 return 0; 1526 } 1527 1528 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1529 { 1530 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1531 int ret; 1532 1533 ret = clk_enable(i2c_imx->clk); 1534 if (ret) 1535 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1536 1537 return ret; 1538 } 1539 1540 static const struct dev_pm_ops i2c_imx_pm_ops = { 1541 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1542 i2c_imx_runtime_resume, NULL) 1543 }; 1544 1545 static struct platform_driver i2c_imx_driver = { 1546 .probe = i2c_imx_probe, 1547 .remove = i2c_imx_remove, 1548 .driver = { 1549 .name = DRIVER_NAME, 1550 .pm = &i2c_imx_pm_ops, 1551 .of_match_table = i2c_imx_dt_ids, 1552 .acpi_match_table = i2c_imx_acpi_ids, 1553 }, 1554 .id_table = imx_i2c_devtype, 1555 }; 1556 1557 static int __init i2c_adap_imx_init(void) 1558 { 1559 return platform_driver_register(&i2c_imx_driver); 1560 } 1561 subsys_initcall(i2c_adap_imx_init); 1562 1563 static void __exit i2c_adap_imx_exit(void) 1564 { 1565 platform_driver_unregister(&i2c_imx_driver); 1566 } 1567 module_exit(i2c_adap_imx_exit); 1568 1569 MODULE_LICENSE("GPL"); 1570 MODULE_AUTHOR("Darius Augulis"); 1571 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1572 MODULE_ALIAS("platform:" DRIVER_NAME); 1573