1 /* 2 * Copyright (C) 2002 Motorola GSG-China 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, 17 * USA. 18 * 19 * Author: 20 * Darius Augulis, Teltonika Inc. 21 * 22 * Desc.: 23 * Implementation of I2C Adapter/Algorithm Driver 24 * for I2C Bus integrated in Freescale i.MX/MXC processors 25 * 26 * Derived from Motorola GSG China I2C example driver 27 * 28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 30 * Copyright (C) 2007 RightHand Technologies, Inc. 31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 32 * 33 */ 34 35 /** Includes ******************************************************************* 36 *******************************************************************************/ 37 38 #include <linux/init.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/errno.h> 42 #include <linux/err.h> 43 #include <linux/interrupt.h> 44 #include <linux/delay.h> 45 #include <linux/i2c.h> 46 #include <linux/io.h> 47 #include <linux/sched.h> 48 #include <linux/platform_device.h> 49 #include <linux/clk.h> 50 #include <linux/slab.h> 51 #include <linux/of.h> 52 #include <linux/of_device.h> 53 #include <linux/of_i2c.h> 54 55 #include <mach/irqs.h> 56 #include <mach/hardware.h> 57 #include <mach/i2c.h> 58 59 /** Defines ******************************************************************** 60 *******************************************************************************/ 61 62 /* This will be the driver name the kernel reports */ 63 #define DRIVER_NAME "imx-i2c" 64 65 /* Default value */ 66 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 67 68 /* IMX I2C registers */ 69 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 70 #define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ 71 #define IMX_I2C_I2CR 0x08 /* i2c control */ 72 #define IMX_I2C_I2SR 0x0C /* i2c status */ 73 #define IMX_I2C_I2DR 0x10 /* i2c transfer data */ 74 75 /* Bits of IMX I2C registers */ 76 #define I2SR_RXAK 0x01 77 #define I2SR_IIF 0x02 78 #define I2SR_SRW 0x04 79 #define I2SR_IAL 0x10 80 #define I2SR_IBB 0x20 81 #define I2SR_IAAS 0x40 82 #define I2SR_ICF 0x80 83 #define I2CR_RSTA 0x04 84 #define I2CR_TXAK 0x08 85 #define I2CR_MTX 0x10 86 #define I2CR_MSTA 0x20 87 #define I2CR_IIEN 0x40 88 #define I2CR_IEN 0x80 89 90 /** Variables ****************************************************************** 91 *******************************************************************************/ 92 93 /* 94 * sorted list of clock divider, register value pairs 95 * taken from table 26-5, p.26-9, Freescale i.MX 96 * Integrated Portable System Processor Reference Manual 97 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 98 * 99 * Duplicated divider values removed from list 100 */ 101 102 static u16 __initdata i2c_clk_div[50][2] = { 103 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 104 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 105 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 106 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 107 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 108 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 109 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 110 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 111 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 112 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 113 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 114 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 115 { 3072, 0x1E }, { 3840, 0x1F } 116 }; 117 118 struct imx_i2c_struct { 119 struct i2c_adapter adapter; 120 struct resource *res; 121 struct clk *clk; 122 void __iomem *base; 123 int irq; 124 wait_queue_head_t queue; 125 unsigned long i2csr; 126 unsigned int disable_delay; 127 int stopped; 128 unsigned int ifdr; /* IMX_I2C_IFDR */ 129 }; 130 131 static const struct of_device_id i2c_imx_dt_ids[] = { 132 { .compatible = "fsl,imx1-i2c", }, 133 { /* sentinel */ } 134 }; 135 136 /** Functions for IMX I2C adapter driver *************************************** 137 *******************************************************************************/ 138 139 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 140 { 141 unsigned long orig_jiffies = jiffies; 142 unsigned int temp; 143 144 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 145 146 while (1) { 147 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 148 if (for_busy && (temp & I2SR_IBB)) 149 break; 150 if (!for_busy && !(temp & I2SR_IBB)) 151 break; 152 if (signal_pending(current)) { 153 dev_dbg(&i2c_imx->adapter.dev, 154 "<%s> I2C Interrupted\n", __func__); 155 return -EINTR; 156 } 157 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 158 dev_dbg(&i2c_imx->adapter.dev, 159 "<%s> I2C bus is busy\n", __func__); 160 return -ETIMEDOUT; 161 } 162 schedule(); 163 } 164 165 return 0; 166 } 167 168 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 169 { 170 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 171 172 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 173 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 174 return -ETIMEDOUT; 175 } 176 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 177 i2c_imx->i2csr = 0; 178 return 0; 179 } 180 181 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 182 { 183 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) { 184 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 185 return -EIO; /* No ACK */ 186 } 187 188 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 189 return 0; 190 } 191 192 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 193 { 194 unsigned int temp = 0; 195 int result; 196 197 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 198 199 clk_enable(i2c_imx->clk); 200 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR); 201 /* Enable I2C controller */ 202 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 203 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); 204 205 /* Wait controller to be stable */ 206 udelay(50); 207 208 /* Start I2C transaction */ 209 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 210 temp |= I2CR_MSTA; 211 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 212 result = i2c_imx_bus_busy(i2c_imx, 1); 213 if (result) 214 return result; 215 i2c_imx->stopped = 0; 216 217 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 218 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 219 return result; 220 } 221 222 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 223 { 224 unsigned int temp = 0; 225 226 if (!i2c_imx->stopped) { 227 /* Stop I2C transaction */ 228 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 229 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 230 temp &= ~(I2CR_MSTA | I2CR_MTX); 231 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 232 } 233 if (cpu_is_mx1()) { 234 /* 235 * This delay caused by an i.MXL hardware bug. 236 * If no (or too short) delay, no "STOP" bit will be generated. 237 */ 238 udelay(i2c_imx->disable_delay); 239 } 240 241 if (!i2c_imx->stopped) { 242 i2c_imx_bus_busy(i2c_imx, 0); 243 i2c_imx->stopped = 1; 244 } 245 246 /* Disable I2C controller */ 247 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 248 clk_disable(i2c_imx->clk); 249 } 250 251 static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 252 unsigned int rate) 253 { 254 unsigned int i2c_clk_rate; 255 unsigned int div; 256 int i; 257 258 /* Divider value calculation */ 259 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 260 div = (i2c_clk_rate + rate - 1) / rate; 261 if (div < i2c_clk_div[0][0]) 262 i = 0; 263 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 264 i = ARRAY_SIZE(i2c_clk_div) - 1; 265 else 266 for (i = 0; i2c_clk_div[i][0] < div; i++); 267 268 /* Store divider value */ 269 i2c_imx->ifdr = i2c_clk_div[i][1]; 270 271 /* 272 * There dummy delay is calculated. 273 * It should be about one I2C clock period long. 274 * This delay is used in I2C bus disable function 275 * to fix chip hardware bug. 276 */ 277 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0] 278 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 279 280 /* dev_dbg() can't be used, because adapter is not yet registered */ 281 #ifdef CONFIG_I2C_DEBUG_BUS 282 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n", 283 __func__, i2c_clk_rate, div); 284 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n", 285 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]); 286 #endif 287 } 288 289 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 290 { 291 struct imx_i2c_struct *i2c_imx = dev_id; 292 unsigned int temp; 293 294 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 295 if (temp & I2SR_IIF) { 296 /* save status register */ 297 i2c_imx->i2csr = temp; 298 temp &= ~I2SR_IIF; 299 writeb(temp, i2c_imx->base + IMX_I2C_I2SR); 300 wake_up(&i2c_imx->queue); 301 return IRQ_HANDLED; 302 } 303 304 return IRQ_NONE; 305 } 306 307 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 308 { 309 int i, result; 310 311 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 312 __func__, msgs->addr << 1); 313 314 /* write slave address */ 315 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR); 316 result = i2c_imx_trx_complete(i2c_imx); 317 if (result) 318 return result; 319 result = i2c_imx_acked(i2c_imx); 320 if (result) 321 return result; 322 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 323 324 /* write data */ 325 for (i = 0; i < msgs->len; i++) { 326 dev_dbg(&i2c_imx->adapter.dev, 327 "<%s> write byte: B%d=0x%X\n", 328 __func__, i, msgs->buf[i]); 329 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR); 330 result = i2c_imx_trx_complete(i2c_imx); 331 if (result) 332 return result; 333 result = i2c_imx_acked(i2c_imx); 334 if (result) 335 return result; 336 } 337 return 0; 338 } 339 340 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 341 { 342 int i, result; 343 unsigned int temp; 344 345 dev_dbg(&i2c_imx->adapter.dev, 346 "<%s> write slave address: addr=0x%x\n", 347 __func__, (msgs->addr << 1) | 0x01); 348 349 /* write slave address */ 350 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR); 351 result = i2c_imx_trx_complete(i2c_imx); 352 if (result) 353 return result; 354 result = i2c_imx_acked(i2c_imx); 355 if (result) 356 return result; 357 358 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 359 360 /* setup bus to read data */ 361 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 362 temp &= ~I2CR_MTX; 363 if (msgs->len - 1) 364 temp &= ~I2CR_TXAK; 365 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 366 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */ 367 368 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 369 370 /* read data */ 371 for (i = 0; i < msgs->len; i++) { 372 result = i2c_imx_trx_complete(i2c_imx); 373 if (result) 374 return result; 375 if (i == (msgs->len - 1)) { 376 /* It must generate STOP before read I2DR to prevent 377 controller from generating another clock cycle */ 378 dev_dbg(&i2c_imx->adapter.dev, 379 "<%s> clear MSTA\n", __func__); 380 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 381 temp &= ~(I2CR_MSTA | I2CR_MTX); 382 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 383 i2c_imx_bus_busy(i2c_imx, 0); 384 i2c_imx->stopped = 1; 385 } else if (i == (msgs->len - 2)) { 386 dev_dbg(&i2c_imx->adapter.dev, 387 "<%s> set TXAK\n", __func__); 388 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 389 temp |= I2CR_TXAK; 390 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 391 } 392 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR); 393 dev_dbg(&i2c_imx->adapter.dev, 394 "<%s> read byte: B%d=0x%X\n", 395 __func__, i, msgs->buf[i]); 396 } 397 return 0; 398 } 399 400 static int i2c_imx_xfer(struct i2c_adapter *adapter, 401 struct i2c_msg *msgs, int num) 402 { 403 unsigned int i, temp; 404 int result; 405 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 406 407 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 408 409 /* Start I2C transfer */ 410 result = i2c_imx_start(i2c_imx); 411 if (result) 412 goto fail0; 413 414 /* read/write data */ 415 for (i = 0; i < num; i++) { 416 if (i) { 417 dev_dbg(&i2c_imx->adapter.dev, 418 "<%s> repeated start\n", __func__); 419 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 420 temp |= I2CR_RSTA; 421 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 422 result = i2c_imx_bus_busy(i2c_imx, 1); 423 if (result) 424 goto fail0; 425 } 426 dev_dbg(&i2c_imx->adapter.dev, 427 "<%s> transfer message: %d\n", __func__, i); 428 /* write/read data */ 429 #ifdef CONFIG_I2C_DEBUG_BUS 430 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 431 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " 432 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, 433 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 434 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 435 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 436 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 437 dev_dbg(&i2c_imx->adapter.dev, 438 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " 439 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, 440 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 441 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 442 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 443 (temp & I2SR_RXAK ? 1 : 0)); 444 #endif 445 if (msgs[i].flags & I2C_M_RD) 446 result = i2c_imx_read(i2c_imx, &msgs[i]); 447 else 448 result = i2c_imx_write(i2c_imx, &msgs[i]); 449 if (result) 450 goto fail0; 451 } 452 453 fail0: 454 /* Stop I2C transfer */ 455 i2c_imx_stop(i2c_imx); 456 457 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 458 (result < 0) ? "error" : "success msg", 459 (result < 0) ? result : num); 460 return (result < 0) ? result : num; 461 } 462 463 static u32 i2c_imx_func(struct i2c_adapter *adapter) 464 { 465 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 466 } 467 468 static struct i2c_algorithm i2c_imx_algo = { 469 .master_xfer = i2c_imx_xfer, 470 .functionality = i2c_imx_func, 471 }; 472 473 static int __init i2c_imx_probe(struct platform_device *pdev) 474 { 475 struct imx_i2c_struct *i2c_imx; 476 struct resource *res; 477 struct imxi2c_platform_data *pdata = pdev->dev.platform_data; 478 void __iomem *base; 479 resource_size_t res_size; 480 int irq, bitrate; 481 int ret; 482 483 dev_dbg(&pdev->dev, "<%s>\n", __func__); 484 485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 486 if (!res) { 487 dev_err(&pdev->dev, "can't get device resources\n"); 488 return -ENOENT; 489 } 490 irq = platform_get_irq(pdev, 0); 491 if (irq < 0) { 492 dev_err(&pdev->dev, "can't get irq number\n"); 493 return -ENOENT; 494 } 495 496 res_size = resource_size(res); 497 498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) { 499 dev_err(&pdev->dev, "request_mem_region failed\n"); 500 return -EBUSY; 501 } 502 503 base = ioremap(res->start, res_size); 504 if (!base) { 505 dev_err(&pdev->dev, "ioremap failed\n"); 506 ret = -EIO; 507 goto fail1; 508 } 509 510 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL); 511 if (!i2c_imx) { 512 dev_err(&pdev->dev, "can't allocate interface\n"); 513 ret = -ENOMEM; 514 goto fail2; 515 } 516 517 /* Setup i2c_imx driver structure */ 518 strcpy(i2c_imx->adapter.name, pdev->name); 519 i2c_imx->adapter.owner = THIS_MODULE; 520 i2c_imx->adapter.algo = &i2c_imx_algo; 521 i2c_imx->adapter.dev.parent = &pdev->dev; 522 i2c_imx->adapter.nr = pdev->id; 523 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 524 i2c_imx->irq = irq; 525 i2c_imx->base = base; 526 i2c_imx->res = res; 527 528 /* Get I2C clock */ 529 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); 530 if (IS_ERR(i2c_imx->clk)) { 531 ret = PTR_ERR(i2c_imx->clk); 532 dev_err(&pdev->dev, "can't get I2C clock\n"); 533 goto fail3; 534 } 535 536 /* Request IRQ */ 537 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx); 538 if (ret) { 539 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq); 540 goto fail4; 541 } 542 543 /* Init queue */ 544 init_waitqueue_head(&i2c_imx->queue); 545 546 /* Set up adapter data */ 547 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 548 549 /* Set up clock divider */ 550 bitrate = IMX_I2C_BIT_RATE; 551 ret = of_property_read_u32(pdev->dev.of_node, 552 "clock-frequency", &bitrate); 553 if (ret < 0 && pdata && pdata->bitrate) 554 bitrate = pdata->bitrate; 555 i2c_imx_set_clk(i2c_imx, bitrate); 556 557 /* Set up chip registers to defaults */ 558 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 559 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 560 561 /* Add I2C adapter */ 562 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 563 if (ret < 0) { 564 dev_err(&pdev->dev, "registration failed\n"); 565 goto fail5; 566 } 567 568 of_i2c_register_devices(&i2c_imx->adapter); 569 570 /* Set up platform driver data */ 571 platform_set_drvdata(pdev, i2c_imx); 572 573 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq); 574 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", 575 i2c_imx->res->start, i2c_imx->res->end); 576 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n", 577 res_size, i2c_imx->res->start); 578 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 579 i2c_imx->adapter.name); 580 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 581 582 return 0; /* Return OK */ 583 584 fail5: 585 free_irq(i2c_imx->irq, i2c_imx); 586 fail4: 587 clk_put(i2c_imx->clk); 588 fail3: 589 kfree(i2c_imx); 590 fail2: 591 iounmap(base); 592 fail1: 593 release_mem_region(res->start, resource_size(res)); 594 return ret; /* Return error number */ 595 } 596 597 static int __exit i2c_imx_remove(struct platform_device *pdev) 598 { 599 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 600 601 /* remove adapter */ 602 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 603 i2c_del_adapter(&i2c_imx->adapter); 604 platform_set_drvdata(pdev, NULL); 605 606 /* free interrupt */ 607 free_irq(i2c_imx->irq, i2c_imx); 608 609 /* setup chip registers to defaults */ 610 writeb(0, i2c_imx->base + IMX_I2C_IADR); 611 writeb(0, i2c_imx->base + IMX_I2C_IFDR); 612 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 613 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 614 615 clk_put(i2c_imx->clk); 616 617 iounmap(i2c_imx->base); 618 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res)); 619 kfree(i2c_imx); 620 return 0; 621 } 622 623 static struct platform_driver i2c_imx_driver = { 624 .remove = __exit_p(i2c_imx_remove), 625 .driver = { 626 .name = DRIVER_NAME, 627 .owner = THIS_MODULE, 628 .of_match_table = i2c_imx_dt_ids, 629 } 630 }; 631 632 static int __init i2c_adap_imx_init(void) 633 { 634 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); 635 } 636 subsys_initcall(i2c_adap_imx_init); 637 638 static void __exit i2c_adap_imx_exit(void) 639 { 640 platform_driver_unregister(&i2c_imx_driver); 641 } 642 module_exit(i2c_adap_imx_exit); 643 644 MODULE_LICENSE("GPL"); 645 MODULE_AUTHOR("Darius Augulis"); 646 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 647 MODULE_ALIAS("platform:" DRIVER_NAME); 648