1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/completion.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/errno.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/i2c.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/io.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_dma.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/platform_data/i2c-imx.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/sched.h> 46 #include <linux/slab.h> 47 48 /* This will be the driver name the kernel reports */ 49 #define DRIVER_NAME "imx-i2c" 50 51 /* Default value */ 52 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 #define IMX_I2C_REGSHIFT 2 78 #define VF610_I2C_REGSHIFT 0 79 80 /* Bits of IMX I2C registers */ 81 #define I2SR_RXAK 0x01 82 #define I2SR_IIF 0x02 83 #define I2SR_SRW 0x04 84 #define I2SR_IAL 0x10 85 #define I2SR_IBB 0x20 86 #define I2SR_IAAS 0x40 87 #define I2SR_ICF 0x80 88 #define I2CR_DMAEN 0x02 89 #define I2CR_RSTA 0x04 90 #define I2CR_TXAK 0x08 91 #define I2CR_MTX 0x10 92 #define I2CR_MSTA 0x20 93 #define I2CR_IIEN 0x40 94 #define I2CR_IEN 0x80 95 96 /* register bits different operating codes definition: 97 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 98 * - write zero to clear(w0c) INT flag on i.MX, 99 * - but write one to clear(w1c) INT flag on Vybrid. 100 * 2) I2CR: I2C module enable operation also differ between SoCs: 101 * - set I2CR_IEN bit enable the module on i.MX, 102 * - but clear I2CR_IEN bit enable the module on Vybrid. 103 */ 104 #define I2SR_CLR_OPCODE_W0C 0x0 105 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 106 #define I2CR_IEN_OPCODE_0 0x0 107 #define I2CR_IEN_OPCODE_1 I2CR_IEN 108 109 #define I2C_PM_TIMEOUT 10 /* ms */ 110 111 /* 112 * sorted list of clock divider, register value pairs 113 * taken from table 26-5, p.26-9, Freescale i.MX 114 * Integrated Portable System Processor Reference Manual 115 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 116 * 117 * Duplicated divider values removed from list 118 */ 119 struct imx_i2c_clk_pair { 120 u16 div; 121 u16 val; 122 }; 123 124 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 125 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 126 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 127 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 128 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 129 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 130 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 131 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 132 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 133 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 134 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 135 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 136 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 137 { 3072, 0x1E }, { 3840, 0x1F } 138 }; 139 140 /* Vybrid VF610 clock divider, register value pairs */ 141 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 142 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 143 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 144 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 145 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 146 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 147 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 148 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 149 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 150 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 151 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 152 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 153 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 154 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 155 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 156 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 157 }; 158 159 enum imx_i2c_type { 160 IMX1_I2C, 161 IMX21_I2C, 162 VF610_I2C, 163 }; 164 165 struct imx_i2c_hwdata { 166 enum imx_i2c_type devtype; 167 unsigned regshift; 168 struct imx_i2c_clk_pair *clk_div; 169 unsigned ndivs; 170 unsigned i2sr_clr_opcode; 171 unsigned i2cr_ien_opcode; 172 }; 173 174 struct imx_i2c_dma { 175 struct dma_chan *chan_tx; 176 struct dma_chan *chan_rx; 177 struct dma_chan *chan_using; 178 struct completion cmd_complete; 179 dma_addr_t dma_buf; 180 unsigned int dma_len; 181 enum dma_transfer_direction dma_transfer_dir; 182 enum dma_data_direction dma_data_dir; 183 }; 184 185 struct imx_i2c_struct { 186 struct i2c_adapter adapter; 187 struct clk *clk; 188 struct notifier_block clk_change_nb; 189 void __iomem *base; 190 wait_queue_head_t queue; 191 unsigned long i2csr; 192 unsigned int disable_delay; 193 int stopped; 194 unsigned int ifdr; /* IMX_I2C_IFDR */ 195 unsigned int cur_clk; 196 unsigned int bitrate; 197 const struct imx_i2c_hwdata *hwdata; 198 struct i2c_bus_recovery_info rinfo; 199 200 struct pinctrl *pinctrl; 201 struct pinctrl_state *pinctrl_pins_default; 202 struct pinctrl_state *pinctrl_pins_gpio; 203 204 struct imx_i2c_dma *dma; 205 }; 206 207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 208 .devtype = IMX1_I2C, 209 .regshift = IMX_I2C_REGSHIFT, 210 .clk_div = imx_i2c_clk_div, 211 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 212 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 213 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 214 215 }; 216 217 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 218 .devtype = IMX21_I2C, 219 .regshift = IMX_I2C_REGSHIFT, 220 .clk_div = imx_i2c_clk_div, 221 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 222 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 223 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 224 225 }; 226 227 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 228 .devtype = VF610_I2C, 229 .regshift = VF610_I2C_REGSHIFT, 230 .clk_div = vf610_i2c_clk_div, 231 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 232 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 233 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 234 235 }; 236 237 static const struct platform_device_id imx_i2c_devtype[] = { 238 { 239 .name = "imx1-i2c", 240 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 241 }, { 242 .name = "imx21-i2c", 243 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 244 }, { 245 /* sentinel */ 246 } 247 }; 248 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 249 250 static const struct of_device_id i2c_imx_dt_ids[] = { 251 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 252 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 253 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 254 { /* sentinel */ } 255 }; 256 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 257 258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 259 { 260 return i2c_imx->hwdata->devtype == IMX1_I2C; 261 } 262 263 static inline void imx_i2c_write_reg(unsigned int val, 264 struct imx_i2c_struct *i2c_imx, unsigned int reg) 265 { 266 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 267 } 268 269 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 270 unsigned int reg) 271 { 272 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 273 } 274 275 /* Functions for DMA support */ 276 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 277 dma_addr_t phy_addr) 278 { 279 struct imx_i2c_dma *dma; 280 struct dma_slave_config dma_sconfig; 281 struct device *dev = &i2c_imx->adapter.dev; 282 int ret; 283 284 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 285 if (!dma) 286 return; 287 288 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 289 if (!dma->chan_tx) { 290 dev_dbg(dev, "can't request DMA tx channel\n"); 291 goto fail_al; 292 } 293 294 dma_sconfig.dst_addr = phy_addr + 295 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 296 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 297 dma_sconfig.dst_maxburst = 1; 298 dma_sconfig.direction = DMA_MEM_TO_DEV; 299 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 300 if (ret < 0) { 301 dev_dbg(dev, "can't configure tx channel\n"); 302 goto fail_tx; 303 } 304 305 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 306 if (!dma->chan_rx) { 307 dev_dbg(dev, "can't request DMA rx channel\n"); 308 goto fail_tx; 309 } 310 311 dma_sconfig.src_addr = phy_addr + 312 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 313 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 314 dma_sconfig.src_maxburst = 1; 315 dma_sconfig.direction = DMA_DEV_TO_MEM; 316 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 317 if (ret < 0) { 318 dev_dbg(dev, "can't configure rx channel\n"); 319 goto fail_rx; 320 } 321 322 i2c_imx->dma = dma; 323 init_completion(&dma->cmd_complete); 324 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 325 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 326 327 return; 328 329 fail_rx: 330 dma_release_channel(dma->chan_rx); 331 fail_tx: 332 dma_release_channel(dma->chan_tx); 333 fail_al: 334 devm_kfree(dev, dma); 335 dev_info(dev, "can't use DMA, using PIO instead.\n"); 336 } 337 338 static void i2c_imx_dma_callback(void *arg) 339 { 340 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 341 struct imx_i2c_dma *dma = i2c_imx->dma; 342 343 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 344 dma->dma_len, dma->dma_data_dir); 345 complete(&dma->cmd_complete); 346 } 347 348 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 349 struct i2c_msg *msgs) 350 { 351 struct imx_i2c_dma *dma = i2c_imx->dma; 352 struct dma_async_tx_descriptor *txdesc; 353 struct device *dev = &i2c_imx->adapter.dev; 354 struct device *chan_dev = dma->chan_using->device->dev; 355 356 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 357 dma->dma_len, dma->dma_data_dir); 358 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 359 dev_err(dev, "DMA mapping failed\n"); 360 goto err_map; 361 } 362 363 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 364 dma->dma_len, dma->dma_transfer_dir, 365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 366 if (!txdesc) { 367 dev_err(dev, "Not able to get desc for DMA xfer\n"); 368 goto err_desc; 369 } 370 371 txdesc->callback = i2c_imx_dma_callback; 372 txdesc->callback_param = i2c_imx; 373 if (dma_submit_error(dmaengine_submit(txdesc))) { 374 dev_err(dev, "DMA submit failed\n"); 375 goto err_submit; 376 } 377 378 dma_async_issue_pending(dma->chan_using); 379 return 0; 380 381 err_submit: 382 dmaengine_terminate_all(dma->chan_using); 383 err_desc: 384 dma_unmap_single(chan_dev, dma->dma_buf, 385 dma->dma_len, dma->dma_data_dir); 386 err_map: 387 return -EINVAL; 388 } 389 390 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 391 { 392 struct imx_i2c_dma *dma = i2c_imx->dma; 393 394 dma->dma_buf = 0; 395 dma->dma_len = 0; 396 397 dma_release_channel(dma->chan_tx); 398 dma->chan_tx = NULL; 399 400 dma_release_channel(dma->chan_rx); 401 dma->chan_rx = NULL; 402 403 dma->chan_using = NULL; 404 } 405 406 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 407 { 408 unsigned long orig_jiffies = jiffies; 409 unsigned int temp; 410 411 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 412 413 while (1) { 414 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 415 416 /* check for arbitration lost */ 417 if (temp & I2SR_IAL) { 418 temp &= ~I2SR_IAL; 419 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 420 return -EAGAIN; 421 } 422 423 if (for_busy && (temp & I2SR_IBB)) 424 break; 425 if (!for_busy && !(temp & I2SR_IBB)) 426 break; 427 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 428 dev_dbg(&i2c_imx->adapter.dev, 429 "<%s> I2C bus is busy\n", __func__); 430 return -ETIMEDOUT; 431 } 432 schedule(); 433 } 434 435 return 0; 436 } 437 438 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 439 { 440 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 441 442 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 443 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 444 return -ETIMEDOUT; 445 } 446 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 447 i2c_imx->i2csr = 0; 448 return 0; 449 } 450 451 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 452 { 453 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 454 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 455 return -ENXIO; /* No ACK */ 456 } 457 458 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 459 return 0; 460 } 461 462 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 463 unsigned int i2c_clk_rate) 464 { 465 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 466 unsigned int div; 467 int i; 468 469 /* Divider value calculation */ 470 if (i2c_imx->cur_clk == i2c_clk_rate) 471 return; 472 473 i2c_imx->cur_clk = i2c_clk_rate; 474 475 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 476 if (div < i2c_clk_div[0].div) 477 i = 0; 478 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 479 i = i2c_imx->hwdata->ndivs - 1; 480 else 481 for (i = 0; i2c_clk_div[i].div < div; i++) 482 ; 483 484 /* Store divider value */ 485 i2c_imx->ifdr = i2c_clk_div[i].val; 486 487 /* 488 * There dummy delay is calculated. 489 * It should be about one I2C clock period long. 490 * This delay is used in I2C bus disable function 491 * to fix chip hardware bug. 492 */ 493 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 494 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 495 496 #ifdef CONFIG_I2C_DEBUG_BUS 497 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 498 i2c_clk_rate, div); 499 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 500 i2c_clk_div[i].val, i2c_clk_div[i].div); 501 #endif 502 } 503 504 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 505 unsigned long action, void *data) 506 { 507 struct clk_notifier_data *ndata = data; 508 struct imx_i2c_struct *i2c_imx = container_of(&ndata->clk, 509 struct imx_i2c_struct, 510 clk); 511 512 if (action & POST_RATE_CHANGE) 513 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 514 515 return NOTIFY_OK; 516 } 517 518 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 519 { 520 unsigned int temp = 0; 521 int result; 522 523 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 524 525 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 526 /* Enable I2C controller */ 527 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 528 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 529 530 /* Wait controller to be stable */ 531 usleep_range(50, 150); 532 533 /* Start I2C transaction */ 534 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 535 temp |= I2CR_MSTA; 536 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 537 result = i2c_imx_bus_busy(i2c_imx, 1); 538 if (result) 539 return result; 540 i2c_imx->stopped = 0; 541 542 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 543 temp &= ~I2CR_DMAEN; 544 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 545 return result; 546 } 547 548 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 549 { 550 unsigned int temp = 0; 551 552 if (!i2c_imx->stopped) { 553 /* Stop I2C transaction */ 554 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 555 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 556 temp &= ~(I2CR_MSTA | I2CR_MTX); 557 if (i2c_imx->dma) 558 temp &= ~I2CR_DMAEN; 559 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 560 } 561 if (is_imx1_i2c(i2c_imx)) { 562 /* 563 * This delay caused by an i.MXL hardware bug. 564 * If no (or too short) delay, no "STOP" bit will be generated. 565 */ 566 udelay(i2c_imx->disable_delay); 567 } 568 569 if (!i2c_imx->stopped) { 570 i2c_imx_bus_busy(i2c_imx, 0); 571 i2c_imx->stopped = 1; 572 } 573 574 /* Disable I2C controller */ 575 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 576 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 577 } 578 579 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 580 { 581 struct imx_i2c_struct *i2c_imx = dev_id; 582 unsigned int temp; 583 584 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 585 if (temp & I2SR_IIF) { 586 /* save status register */ 587 i2c_imx->i2csr = temp; 588 temp &= ~I2SR_IIF; 589 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 590 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 591 wake_up(&i2c_imx->queue); 592 return IRQ_HANDLED; 593 } 594 595 return IRQ_NONE; 596 } 597 598 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 599 struct i2c_msg *msgs) 600 { 601 int result; 602 unsigned long time_left; 603 unsigned int temp = 0; 604 unsigned long orig_jiffies = jiffies; 605 struct imx_i2c_dma *dma = i2c_imx->dma; 606 struct device *dev = &i2c_imx->adapter.dev; 607 608 dma->chan_using = dma->chan_tx; 609 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 610 dma->dma_data_dir = DMA_TO_DEVICE; 611 dma->dma_len = msgs->len - 1; 612 result = i2c_imx_dma_xfer(i2c_imx, msgs); 613 if (result) 614 return result; 615 616 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 617 temp |= I2CR_DMAEN; 618 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 619 620 /* 621 * Write slave address. 622 * The first byte must be transmitted by the CPU. 623 */ 624 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 625 reinit_completion(&i2c_imx->dma->cmd_complete); 626 time_left = wait_for_completion_timeout( 627 &i2c_imx->dma->cmd_complete, 628 msecs_to_jiffies(DMA_TIMEOUT)); 629 if (time_left == 0) { 630 dmaengine_terminate_all(dma->chan_using); 631 return -ETIMEDOUT; 632 } 633 634 /* Waiting for transfer complete. */ 635 while (1) { 636 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 637 if (temp & I2SR_ICF) 638 break; 639 if (time_after(jiffies, orig_jiffies + 640 msecs_to_jiffies(DMA_TIMEOUT))) { 641 dev_dbg(dev, "<%s> Timeout\n", __func__); 642 return -ETIMEDOUT; 643 } 644 schedule(); 645 } 646 647 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 648 temp &= ~I2CR_DMAEN; 649 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 650 651 /* The last data byte must be transferred by the CPU. */ 652 imx_i2c_write_reg(msgs->buf[msgs->len-1], 653 i2c_imx, IMX_I2C_I2DR); 654 result = i2c_imx_trx_complete(i2c_imx); 655 if (result) 656 return result; 657 658 return i2c_imx_acked(i2c_imx); 659 } 660 661 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 662 struct i2c_msg *msgs, bool is_lastmsg) 663 { 664 int result; 665 unsigned long time_left; 666 unsigned int temp; 667 unsigned long orig_jiffies = jiffies; 668 struct imx_i2c_dma *dma = i2c_imx->dma; 669 struct device *dev = &i2c_imx->adapter.dev; 670 671 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 672 temp |= I2CR_DMAEN; 673 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 674 675 dma->chan_using = dma->chan_rx; 676 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 677 dma->dma_data_dir = DMA_FROM_DEVICE; 678 /* The last two data bytes must be transferred by the CPU. */ 679 dma->dma_len = msgs->len - 2; 680 result = i2c_imx_dma_xfer(i2c_imx, msgs); 681 if (result) 682 return result; 683 684 reinit_completion(&i2c_imx->dma->cmd_complete); 685 time_left = wait_for_completion_timeout( 686 &i2c_imx->dma->cmd_complete, 687 msecs_to_jiffies(DMA_TIMEOUT)); 688 if (time_left == 0) { 689 dmaengine_terminate_all(dma->chan_using); 690 return -ETIMEDOUT; 691 } 692 693 /* waiting for transfer complete. */ 694 while (1) { 695 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 696 if (temp & I2SR_ICF) 697 break; 698 if (time_after(jiffies, orig_jiffies + 699 msecs_to_jiffies(DMA_TIMEOUT))) { 700 dev_dbg(dev, "<%s> Timeout\n", __func__); 701 return -ETIMEDOUT; 702 } 703 schedule(); 704 } 705 706 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 707 temp &= ~I2CR_DMAEN; 708 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 709 710 /* read n-1 byte data */ 711 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 712 temp |= I2CR_TXAK; 713 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 714 715 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 716 /* read n byte data */ 717 result = i2c_imx_trx_complete(i2c_imx); 718 if (result) 719 return result; 720 721 if (is_lastmsg) { 722 /* 723 * It must generate STOP before read I2DR to prevent 724 * controller from generating another clock cycle 725 */ 726 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 727 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 728 temp &= ~(I2CR_MSTA | I2CR_MTX); 729 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 730 i2c_imx_bus_busy(i2c_imx, 0); 731 i2c_imx->stopped = 1; 732 } else { 733 /* 734 * For i2c master receiver repeat restart operation like: 735 * read -> repeat MSTA -> read/write 736 * The controller must set MTX before read the last byte in 737 * the first read operation, otherwise the first read cost 738 * one extra clock cycle. 739 */ 740 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 741 temp |= I2CR_MTX; 742 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 743 } 744 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 745 746 return 0; 747 } 748 749 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 750 { 751 int i, result; 752 753 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 754 __func__, i2c_8bit_addr_from_msg(msgs)); 755 756 /* write slave address */ 757 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 758 result = i2c_imx_trx_complete(i2c_imx); 759 if (result) 760 return result; 761 result = i2c_imx_acked(i2c_imx); 762 if (result) 763 return result; 764 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 765 766 /* write data */ 767 for (i = 0; i < msgs->len; i++) { 768 dev_dbg(&i2c_imx->adapter.dev, 769 "<%s> write byte: B%d=0x%X\n", 770 __func__, i, msgs->buf[i]); 771 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 772 result = i2c_imx_trx_complete(i2c_imx); 773 if (result) 774 return result; 775 result = i2c_imx_acked(i2c_imx); 776 if (result) 777 return result; 778 } 779 return 0; 780 } 781 782 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 783 { 784 int i, result; 785 unsigned int temp; 786 int block_data = msgs->flags & I2C_M_RECV_LEN; 787 788 dev_dbg(&i2c_imx->adapter.dev, 789 "<%s> write slave address: addr=0x%x\n", 790 __func__, i2c_8bit_addr_from_msg(msgs)); 791 792 /* write slave address */ 793 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 794 result = i2c_imx_trx_complete(i2c_imx); 795 if (result) 796 return result; 797 result = i2c_imx_acked(i2c_imx); 798 if (result) 799 return result; 800 801 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 802 803 /* setup bus to read data */ 804 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 805 temp &= ~I2CR_MTX; 806 807 /* 808 * Reset the I2CR_TXAK flag initially for SMBus block read since the 809 * length is unknown 810 */ 811 if ((msgs->len - 1) || block_data) 812 temp &= ~I2CR_TXAK; 813 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 814 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 815 816 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 817 818 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data) 819 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 820 821 /* read data */ 822 for (i = 0; i < msgs->len; i++) { 823 u8 len = 0; 824 825 result = i2c_imx_trx_complete(i2c_imx); 826 if (result) 827 return result; 828 /* 829 * First byte is the length of remaining packet 830 * in the SMBus block data read. Add it to 831 * msgs->len. 832 */ 833 if ((!i) && block_data) { 834 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 835 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 836 return -EPROTO; 837 dev_dbg(&i2c_imx->adapter.dev, 838 "<%s> read length: 0x%X\n", 839 __func__, len); 840 msgs->len += len; 841 } 842 if (i == (msgs->len - 1)) { 843 if (is_lastmsg) { 844 /* 845 * It must generate STOP before read I2DR to prevent 846 * controller from generating another clock cycle 847 */ 848 dev_dbg(&i2c_imx->adapter.dev, 849 "<%s> clear MSTA\n", __func__); 850 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 851 temp &= ~(I2CR_MSTA | I2CR_MTX); 852 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 853 i2c_imx_bus_busy(i2c_imx, 0); 854 i2c_imx->stopped = 1; 855 } else { 856 /* 857 * For i2c master receiver repeat restart operation like: 858 * read -> repeat MSTA -> read/write 859 * The controller must set MTX before read the last byte in 860 * the first read operation, otherwise the first read cost 861 * one extra clock cycle. 862 */ 863 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 864 temp |= I2CR_MTX; 865 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 866 } 867 } else if (i == (msgs->len - 2)) { 868 dev_dbg(&i2c_imx->adapter.dev, 869 "<%s> set TXAK\n", __func__); 870 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 871 temp |= I2CR_TXAK; 872 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 873 } 874 if ((!i) && block_data) 875 msgs->buf[0] = len; 876 else 877 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 878 dev_dbg(&i2c_imx->adapter.dev, 879 "<%s> read byte: B%d=0x%X\n", 880 __func__, i, msgs->buf[i]); 881 } 882 return 0; 883 } 884 885 static int i2c_imx_xfer(struct i2c_adapter *adapter, 886 struct i2c_msg *msgs, int num) 887 { 888 unsigned int i, temp; 889 int result; 890 bool is_lastmsg = false; 891 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 892 893 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 894 895 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 896 if (result < 0) 897 goto out; 898 899 /* Start I2C transfer */ 900 result = i2c_imx_start(i2c_imx); 901 if (result) { 902 if (i2c_imx->adapter.bus_recovery_info) { 903 i2c_recover_bus(&i2c_imx->adapter); 904 result = i2c_imx_start(i2c_imx); 905 } 906 } 907 908 if (result) 909 goto fail0; 910 911 /* read/write data */ 912 for (i = 0; i < num; i++) { 913 if (i == num - 1) 914 is_lastmsg = true; 915 916 if (i) { 917 dev_dbg(&i2c_imx->adapter.dev, 918 "<%s> repeated start\n", __func__); 919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 920 temp |= I2CR_RSTA; 921 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 922 result = i2c_imx_bus_busy(i2c_imx, 1); 923 if (result) 924 goto fail0; 925 } 926 dev_dbg(&i2c_imx->adapter.dev, 927 "<%s> transfer message: %d\n", __func__, i); 928 /* write/read data */ 929 #ifdef CONFIG_I2C_DEBUG_BUS 930 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 931 dev_dbg(&i2c_imx->adapter.dev, 932 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 933 __func__, 934 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 935 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 936 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 937 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 938 dev_dbg(&i2c_imx->adapter.dev, 939 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 940 __func__, 941 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 942 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 943 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 944 (temp & I2SR_RXAK ? 1 : 0)); 945 #endif 946 if (msgs[i].flags & I2C_M_RD) 947 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 948 else { 949 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 950 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 951 else 952 result = i2c_imx_write(i2c_imx, &msgs[i]); 953 } 954 if (result) 955 goto fail0; 956 } 957 958 fail0: 959 /* Stop I2C transfer */ 960 i2c_imx_stop(i2c_imx); 961 962 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 963 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 964 965 out: 966 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 967 (result < 0) ? "error" : "success msg", 968 (result < 0) ? result : num); 969 return (result < 0) ? result : num; 970 } 971 972 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 973 { 974 struct imx_i2c_struct *i2c_imx; 975 976 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 977 978 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 979 } 980 981 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 982 { 983 struct imx_i2c_struct *i2c_imx; 984 985 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 986 987 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 988 } 989 990 /* 991 * We switch SCL and SDA to their GPIO function and do some bitbanging 992 * for bus recovery. These alternative pinmux settings can be 993 * described in the device tree by a separate pinctrl state "gpio". If 994 * this is missing this is not a big problem, the only implication is 995 * that we can't do bus recovery. 996 */ 997 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 998 struct platform_device *pdev) 999 { 1000 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1001 1002 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1003 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1004 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1005 return PTR_ERR(i2c_imx->pinctrl); 1006 } 1007 1008 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1009 PINCTRL_STATE_DEFAULT); 1010 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1011 "gpio"); 1012 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1013 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH); 1014 1015 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1016 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1017 return -EPROBE_DEFER; 1018 } else if (IS_ERR(rinfo->sda_gpiod) || 1019 IS_ERR(rinfo->scl_gpiod) || 1020 IS_ERR(i2c_imx->pinctrl_pins_default) || 1021 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1022 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1023 return 0; 1024 } 1025 1026 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1027 rinfo->sda_gpiod ? ",sda" : ""); 1028 1029 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1030 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1031 rinfo->recover_bus = i2c_generic_scl_recovery; 1032 i2c_imx->adapter.bus_recovery_info = rinfo; 1033 1034 return 0; 1035 } 1036 1037 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1038 { 1039 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1040 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1041 } 1042 1043 static const struct i2c_algorithm i2c_imx_algo = { 1044 .master_xfer = i2c_imx_xfer, 1045 .functionality = i2c_imx_func, 1046 }; 1047 1048 static int i2c_imx_probe(struct platform_device *pdev) 1049 { 1050 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 1051 &pdev->dev); 1052 struct imx_i2c_struct *i2c_imx; 1053 struct resource *res; 1054 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1055 void __iomem *base; 1056 int irq, ret; 1057 dma_addr_t phy_addr; 1058 1059 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1060 1061 irq = platform_get_irq(pdev, 0); 1062 if (irq < 0) { 1063 dev_err(&pdev->dev, "can't get irq number\n"); 1064 return irq; 1065 } 1066 1067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1068 base = devm_ioremap_resource(&pdev->dev, res); 1069 if (IS_ERR(base)) 1070 return PTR_ERR(base); 1071 1072 phy_addr = (dma_addr_t)res->start; 1073 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1074 if (!i2c_imx) 1075 return -ENOMEM; 1076 1077 if (of_id) 1078 i2c_imx->hwdata = of_id->data; 1079 else 1080 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1081 platform_get_device_id(pdev)->driver_data; 1082 1083 /* Setup i2c_imx driver structure */ 1084 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1085 i2c_imx->adapter.owner = THIS_MODULE; 1086 i2c_imx->adapter.algo = &i2c_imx_algo; 1087 i2c_imx->adapter.dev.parent = &pdev->dev; 1088 i2c_imx->adapter.nr = pdev->id; 1089 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1090 i2c_imx->base = base; 1091 1092 /* Get I2C clock */ 1093 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1094 if (IS_ERR(i2c_imx->clk)) { 1095 dev_err(&pdev->dev, "can't get I2C clock\n"); 1096 return PTR_ERR(i2c_imx->clk); 1097 } 1098 1099 ret = clk_prepare_enable(i2c_imx->clk); 1100 if (ret) { 1101 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1102 return ret; 1103 } 1104 1105 /* Request IRQ */ 1106 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED, 1107 pdev->name, i2c_imx); 1108 if (ret) { 1109 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1110 goto clk_disable; 1111 } 1112 1113 /* Init queue */ 1114 init_waitqueue_head(&i2c_imx->queue); 1115 1116 /* Set up adapter data */ 1117 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1118 1119 /* Set up platform driver data */ 1120 platform_set_drvdata(pdev, i2c_imx); 1121 1122 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1123 pm_runtime_use_autosuspend(&pdev->dev); 1124 pm_runtime_set_active(&pdev->dev); 1125 pm_runtime_enable(&pdev->dev); 1126 1127 ret = pm_runtime_get_sync(&pdev->dev); 1128 if (ret < 0) 1129 goto rpm_disable; 1130 1131 /* Set up clock divider */ 1132 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 1133 ret = of_property_read_u32(pdev->dev.of_node, 1134 "clock-frequency", &i2c_imx->bitrate); 1135 if (ret < 0 && pdata && pdata->bitrate) 1136 i2c_imx->bitrate = pdata->bitrate; 1137 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1138 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1139 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1140 1141 /* Set up chip registers to defaults */ 1142 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1143 i2c_imx, IMX_I2C_I2CR); 1144 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1145 1146 /* Init optional bus recovery function */ 1147 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1148 /* Give it another chance if pinctrl used is not ready yet */ 1149 if (ret == -EPROBE_DEFER) 1150 goto clk_notifier_unregister; 1151 1152 /* Add I2C adapter */ 1153 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1154 if (ret < 0) 1155 goto clk_notifier_unregister; 1156 1157 pm_runtime_mark_last_busy(&pdev->dev); 1158 pm_runtime_put_autosuspend(&pdev->dev); 1159 1160 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1161 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1162 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1163 i2c_imx->adapter.name); 1164 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1165 1166 /* Init DMA config if supported */ 1167 i2c_imx_dma_request(i2c_imx, phy_addr); 1168 1169 return 0; /* Return OK */ 1170 1171 clk_notifier_unregister: 1172 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1173 rpm_disable: 1174 pm_runtime_put_noidle(&pdev->dev); 1175 pm_runtime_disable(&pdev->dev); 1176 pm_runtime_set_suspended(&pdev->dev); 1177 pm_runtime_dont_use_autosuspend(&pdev->dev); 1178 1179 clk_disable: 1180 clk_disable_unprepare(i2c_imx->clk); 1181 return ret; 1182 } 1183 1184 static int i2c_imx_remove(struct platform_device *pdev) 1185 { 1186 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1187 int ret; 1188 1189 ret = pm_runtime_get_sync(&pdev->dev); 1190 if (ret < 0) 1191 return ret; 1192 1193 /* remove adapter */ 1194 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1195 i2c_del_adapter(&i2c_imx->adapter); 1196 1197 if (i2c_imx->dma) 1198 i2c_imx_dma_free(i2c_imx); 1199 1200 /* setup chip registers to defaults */ 1201 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1202 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1203 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1204 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1205 1206 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1207 clk_disable_unprepare(i2c_imx->clk); 1208 1209 pm_runtime_put_noidle(&pdev->dev); 1210 pm_runtime_disable(&pdev->dev); 1211 1212 return 0; 1213 } 1214 1215 #ifdef CONFIG_PM 1216 static int i2c_imx_runtime_suspend(struct device *dev) 1217 { 1218 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1219 1220 clk_disable(i2c_imx->clk); 1221 1222 return 0; 1223 } 1224 1225 static int i2c_imx_runtime_resume(struct device *dev) 1226 { 1227 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1228 int ret; 1229 1230 ret = clk_enable(i2c_imx->clk); 1231 if (ret) 1232 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1233 1234 return ret; 1235 } 1236 1237 static const struct dev_pm_ops i2c_imx_pm_ops = { 1238 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1239 i2c_imx_runtime_resume, NULL) 1240 }; 1241 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops) 1242 #else 1243 #define I2C_IMX_PM_OPS NULL 1244 #endif /* CONFIG_PM */ 1245 1246 static struct platform_driver i2c_imx_driver = { 1247 .probe = i2c_imx_probe, 1248 .remove = i2c_imx_remove, 1249 .driver = { 1250 .name = DRIVER_NAME, 1251 .pm = I2C_IMX_PM_OPS, 1252 .of_match_table = i2c_imx_dt_ids, 1253 }, 1254 .id_table = imx_i2c_devtype, 1255 }; 1256 1257 static int __init i2c_adap_imx_init(void) 1258 { 1259 return platform_driver_register(&i2c_imx_driver); 1260 } 1261 subsys_initcall(i2c_adap_imx_init); 1262 1263 static void __exit i2c_adap_imx_exit(void) 1264 { 1265 platform_driver_unregister(&i2c_imx_driver); 1266 } 1267 module_exit(i2c_adap_imx_exit); 1268 1269 MODULE_LICENSE("GPL"); 1270 MODULE_AUTHOR("Darius Augulis"); 1271 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1272 MODULE_ALIAS("platform:" DRIVER_NAME); 1273