1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * This is i.MX low power i2c controller driver.
4  *
5  * Copyright 2016 Freescale Semiconductor, Inc.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/errno.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 
27 #define DRIVER_NAME "imx-lpi2c"
28 
29 #define LPI2C_PARAM	0x04	/* i2c RX/TX FIFO size */
30 #define LPI2C_MCR	0x10	/* i2c contrl register */
31 #define LPI2C_MSR	0x14	/* i2c status register */
32 #define LPI2C_MIER	0x18	/* i2c interrupt enable */
33 #define LPI2C_MCFGR0	0x20	/* i2c master configuration */
34 #define LPI2C_MCFGR1	0x24	/* i2c master configuration */
35 #define LPI2C_MCFGR2	0x28	/* i2c master configuration */
36 #define LPI2C_MCFGR3	0x2C	/* i2c master configuration */
37 #define LPI2C_MCCR0	0x48	/* i2c master clk configuration */
38 #define LPI2C_MCCR1	0x50	/* i2c master clk configuration */
39 #define LPI2C_MFCR	0x58	/* i2c master FIFO control */
40 #define LPI2C_MFSR	0x5C	/* i2c master FIFO status */
41 #define LPI2C_MTDR	0x60	/* i2c master TX data register */
42 #define LPI2C_MRDR	0x70	/* i2c master RX data register */
43 
44 /* i2c command */
45 #define TRAN_DATA	0X00
46 #define RECV_DATA	0X01
47 #define GEN_STOP	0X02
48 #define RECV_DISCARD	0X03
49 #define GEN_START	0X04
50 #define START_NACK	0X05
51 #define START_HIGH	0X06
52 #define START_HIGH_NACK	0X07
53 
54 #define MCR_MEN		BIT(0)
55 #define MCR_RST		BIT(1)
56 #define MCR_DOZEN	BIT(2)
57 #define MCR_DBGEN	BIT(3)
58 #define MCR_RTF		BIT(8)
59 #define MCR_RRF		BIT(9)
60 #define MSR_TDF		BIT(0)
61 #define MSR_RDF		BIT(1)
62 #define MSR_SDF		BIT(9)
63 #define MSR_NDF		BIT(10)
64 #define MSR_ALF		BIT(11)
65 #define MSR_MBF		BIT(24)
66 #define MSR_BBF		BIT(25)
67 #define MIER_TDIE	BIT(0)
68 #define MIER_RDIE	BIT(1)
69 #define MIER_SDIE	BIT(9)
70 #define MIER_NDIE	BIT(10)
71 #define MCFGR1_AUTOSTOP	BIT(8)
72 #define MCFGR1_IGNACK	BIT(9)
73 #define MRDR_RXEMPTY	BIT(14)
74 
75 #define I2C_CLK_RATIO	2
76 #define CHUNK_DATA	256
77 
78 #define I2C_PM_TIMEOUT		10 /* ms */
79 
80 enum lpi2c_imx_mode {
81 	STANDARD,	/* 100+Kbps */
82 	FAST,		/* 400+Kbps */
83 	FAST_PLUS,	/* 1.0+Mbps */
84 	HS,		/* 3.4+Mbps */
85 	ULTRA_FAST,	/* 5.0+Mbps */
86 };
87 
88 enum lpi2c_imx_pincfg {
89 	TWO_PIN_OD,
90 	TWO_PIN_OO,
91 	TWO_PIN_PP,
92 	FOUR_PIN_PP,
93 };
94 
95 struct lpi2c_imx_struct {
96 	struct i2c_adapter	adapter;
97 	int			num_clks;
98 	struct clk_bulk_data	*clks;
99 	void __iomem		*base;
100 	__u8			*rx_buf;
101 	__u8			*tx_buf;
102 	struct completion	complete;
103 	unsigned int		msglen;
104 	unsigned int		delivered;
105 	unsigned int		block_data;
106 	unsigned int		bitrate;
107 	unsigned int		txfifosize;
108 	unsigned int		rxfifosize;
109 	enum lpi2c_imx_mode	mode;
110 };
111 
112 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
113 			      unsigned int enable)
114 {
115 	writel(enable, lpi2c_imx->base + LPI2C_MIER);
116 }
117 
118 static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
119 {
120 	unsigned long orig_jiffies = jiffies;
121 	unsigned int temp;
122 
123 	while (1) {
124 		temp = readl(lpi2c_imx->base + LPI2C_MSR);
125 
126 		/* check for arbitration lost, clear if set */
127 		if (temp & MSR_ALF) {
128 			writel(temp, lpi2c_imx->base + LPI2C_MSR);
129 			return -EAGAIN;
130 		}
131 
132 		if (temp & (MSR_BBF | MSR_MBF))
133 			break;
134 
135 		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
136 			dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
137 			return -ETIMEDOUT;
138 		}
139 		schedule();
140 	}
141 
142 	return 0;
143 }
144 
145 static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
146 {
147 	unsigned int bitrate = lpi2c_imx->bitrate;
148 	enum lpi2c_imx_mode mode;
149 
150 	if (bitrate < I2C_MAX_FAST_MODE_FREQ)
151 		mode = STANDARD;
152 	else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ)
153 		mode = FAST;
154 	else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ)
155 		mode = FAST_PLUS;
156 	else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ)
157 		mode = HS;
158 	else
159 		mode = ULTRA_FAST;
160 
161 	lpi2c_imx->mode = mode;
162 }
163 
164 static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
165 			   struct i2c_msg *msgs)
166 {
167 	unsigned int temp;
168 
169 	temp = readl(lpi2c_imx->base + LPI2C_MCR);
170 	temp |= MCR_RRF | MCR_RTF;
171 	writel(temp, lpi2c_imx->base + LPI2C_MCR);
172 	writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
173 
174 	temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8);
175 	writel(temp, lpi2c_imx->base + LPI2C_MTDR);
176 
177 	return lpi2c_imx_bus_busy(lpi2c_imx);
178 }
179 
180 static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
181 {
182 	unsigned long orig_jiffies = jiffies;
183 	unsigned int temp;
184 
185 	writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
186 
187 	do {
188 		temp = readl(lpi2c_imx->base + LPI2C_MSR);
189 		if (temp & MSR_SDF)
190 			break;
191 
192 		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
193 			dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
194 			break;
195 		}
196 		schedule();
197 
198 	} while (1);
199 }
200 
201 /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
202 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
203 {
204 	u8 prescale, filt, sethold, clkhi, clklo, datavd;
205 	unsigned int clk_rate, clk_cycle;
206 	enum lpi2c_imx_pincfg pincfg;
207 	unsigned int temp;
208 
209 	lpi2c_imx_set_mode(lpi2c_imx);
210 
211 	clk_rate = clk_get_rate(lpi2c_imx->clks[0].clk);
212 	if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
213 		filt = 0;
214 	else
215 		filt = 2;
216 
217 	for (prescale = 0; prescale <= 7; prescale++) {
218 		clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
219 			    - 3 - (filt >> 1);
220 		clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
221 		clklo = clk_cycle - clkhi;
222 		if (clklo < 64)
223 			break;
224 	}
225 
226 	if (prescale > 7)
227 		return -EINVAL;
228 
229 	/* set MCFGR1: PINCFG, PRESCALE, IGNACK */
230 	if (lpi2c_imx->mode == ULTRA_FAST)
231 		pincfg = TWO_PIN_OO;
232 	else
233 		pincfg = TWO_PIN_OD;
234 	temp = prescale | pincfg << 24;
235 
236 	if (lpi2c_imx->mode == ULTRA_FAST)
237 		temp |= MCFGR1_IGNACK;
238 
239 	writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
240 
241 	/* set MCFGR2: FILTSDA, FILTSCL */
242 	temp = (filt << 16) | (filt << 24);
243 	writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
244 
245 	/* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */
246 	sethold = clkhi;
247 	datavd = clkhi >> 1;
248 	temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo;
249 
250 	if (lpi2c_imx->mode == HS)
251 		writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
252 	else
253 		writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
254 
255 	return 0;
256 }
257 
258 static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
259 {
260 	unsigned int temp;
261 	int ret;
262 
263 	ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent);
264 	if (ret < 0)
265 		return ret;
266 
267 	temp = MCR_RST;
268 	writel(temp, lpi2c_imx->base + LPI2C_MCR);
269 	writel(0, lpi2c_imx->base + LPI2C_MCR);
270 
271 	ret = lpi2c_imx_config(lpi2c_imx);
272 	if (ret)
273 		goto rpm_put;
274 
275 	temp = readl(lpi2c_imx->base + LPI2C_MCR);
276 	temp |= MCR_MEN;
277 	writel(temp, lpi2c_imx->base + LPI2C_MCR);
278 
279 	return 0;
280 
281 rpm_put:
282 	pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
283 	pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
284 
285 	return ret;
286 }
287 
288 static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx)
289 {
290 	u32 temp;
291 
292 	temp = readl(lpi2c_imx->base + LPI2C_MCR);
293 	temp &= ~MCR_MEN;
294 	writel(temp, lpi2c_imx->base + LPI2C_MCR);
295 
296 	pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
297 	pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
298 
299 	return 0;
300 }
301 
302 static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
303 {
304 	unsigned long timeout;
305 
306 	timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ);
307 
308 	return timeout ? 0 : -ETIMEDOUT;
309 }
310 
311 static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx)
312 {
313 	unsigned long orig_jiffies = jiffies;
314 	u32 txcnt;
315 
316 	do {
317 		txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
318 
319 		if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) {
320 			dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n");
321 			return -EIO;
322 		}
323 
324 		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
325 			dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n");
326 			return -ETIMEDOUT;
327 		}
328 		schedule();
329 
330 	} while (txcnt);
331 
332 	return 0;
333 }
334 
335 static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
336 {
337 	writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
338 }
339 
340 static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
341 {
342 	unsigned int temp, remaining;
343 
344 	remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
345 
346 	if (remaining > (lpi2c_imx->rxfifosize >> 1))
347 		temp = lpi2c_imx->rxfifosize >> 1;
348 	else
349 		temp = 0;
350 
351 	writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
352 }
353 
354 static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx)
355 {
356 	unsigned int data, txcnt;
357 
358 	txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
359 
360 	while (txcnt < lpi2c_imx->txfifosize) {
361 		if (lpi2c_imx->delivered == lpi2c_imx->msglen)
362 			break;
363 
364 		data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++];
365 		writel(data, lpi2c_imx->base + LPI2C_MTDR);
366 		txcnt++;
367 	}
368 
369 	if (lpi2c_imx->delivered < lpi2c_imx->msglen)
370 		lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE);
371 	else
372 		complete(&lpi2c_imx->complete);
373 }
374 
375 static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx)
376 {
377 	unsigned int blocklen, remaining;
378 	unsigned int temp, data;
379 
380 	do {
381 		data = readl(lpi2c_imx->base + LPI2C_MRDR);
382 		if (data & MRDR_RXEMPTY)
383 			break;
384 
385 		lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff;
386 	} while (1);
387 
388 	/*
389 	 * First byte is the length of remaining packet in the SMBus block
390 	 * data read. Add it to msgs->len.
391 	 */
392 	if (lpi2c_imx->block_data) {
393 		blocklen = lpi2c_imx->rx_buf[0];
394 		lpi2c_imx->msglen += blocklen;
395 	}
396 
397 	remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
398 
399 	if (!remaining) {
400 		complete(&lpi2c_imx->complete);
401 		return;
402 	}
403 
404 	/* not finished, still waiting for rx data */
405 	lpi2c_imx_set_rx_watermark(lpi2c_imx);
406 
407 	/* multiple receive commands */
408 	if (lpi2c_imx->block_data) {
409 		lpi2c_imx->block_data = 0;
410 		temp = remaining;
411 		temp |= (RECV_DATA << 8);
412 		writel(temp, lpi2c_imx->base + LPI2C_MTDR);
413 	} else if (!(lpi2c_imx->delivered & 0xff)) {
414 		temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1;
415 		temp |= (RECV_DATA << 8);
416 		writel(temp, lpi2c_imx->base + LPI2C_MTDR);
417 	}
418 
419 	lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE);
420 }
421 
422 static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx,
423 			    struct i2c_msg *msgs)
424 {
425 	lpi2c_imx->tx_buf = msgs->buf;
426 	lpi2c_imx_set_tx_watermark(lpi2c_imx);
427 	lpi2c_imx_write_txfifo(lpi2c_imx);
428 }
429 
430 static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx,
431 			   struct i2c_msg *msgs)
432 {
433 	unsigned int temp;
434 
435 	lpi2c_imx->rx_buf = msgs->buf;
436 	lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN;
437 
438 	lpi2c_imx_set_rx_watermark(lpi2c_imx);
439 	temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1;
440 	temp |= (RECV_DATA << 8);
441 	writel(temp, lpi2c_imx->base + LPI2C_MTDR);
442 
443 	lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE);
444 }
445 
446 static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
447 			  struct i2c_msg *msgs, int num)
448 {
449 	struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter);
450 	unsigned int temp;
451 	int i, result;
452 
453 	result = lpi2c_imx_master_enable(lpi2c_imx);
454 	if (result)
455 		return result;
456 
457 	for (i = 0; i < num; i++) {
458 		result = lpi2c_imx_start(lpi2c_imx, &msgs[i]);
459 		if (result)
460 			goto disable;
461 
462 		/* quick smbus */
463 		if (num == 1 && msgs[0].len == 0)
464 			goto stop;
465 
466 		lpi2c_imx->rx_buf = NULL;
467 		lpi2c_imx->tx_buf = NULL;
468 		lpi2c_imx->delivered = 0;
469 		lpi2c_imx->msglen = msgs[i].len;
470 		init_completion(&lpi2c_imx->complete);
471 
472 		if (msgs[i].flags & I2C_M_RD)
473 			lpi2c_imx_read(lpi2c_imx, &msgs[i]);
474 		else
475 			lpi2c_imx_write(lpi2c_imx, &msgs[i]);
476 
477 		result = lpi2c_imx_msg_complete(lpi2c_imx);
478 		if (result)
479 			goto stop;
480 
481 		if (!(msgs[i].flags & I2C_M_RD)) {
482 			result = lpi2c_imx_txfifo_empty(lpi2c_imx);
483 			if (result)
484 				goto stop;
485 		}
486 	}
487 
488 stop:
489 	lpi2c_imx_stop(lpi2c_imx);
490 
491 	temp = readl(lpi2c_imx->base + LPI2C_MSR);
492 	if ((temp & MSR_NDF) && !result)
493 		result = -EIO;
494 
495 disable:
496 	lpi2c_imx_master_disable(lpi2c_imx);
497 
498 	dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
499 		(result < 0) ? "error" : "success msg",
500 		(result < 0) ? result : num);
501 
502 	return (result < 0) ? result : num;
503 }
504 
505 static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
506 {
507 	struct lpi2c_imx_struct *lpi2c_imx = dev_id;
508 	unsigned int enabled;
509 	unsigned int temp;
510 
511 	enabled = readl(lpi2c_imx->base + LPI2C_MIER);
512 
513 	lpi2c_imx_intctrl(lpi2c_imx, 0);
514 	temp = readl(lpi2c_imx->base + LPI2C_MSR);
515 	temp &= enabled;
516 
517 	if (temp & MSR_RDF)
518 		lpi2c_imx_read_rxfifo(lpi2c_imx);
519 
520 	if (temp & MSR_TDF)
521 		lpi2c_imx_write_txfifo(lpi2c_imx);
522 
523 	if (temp & MSR_NDF)
524 		complete(&lpi2c_imx->complete);
525 
526 	return IRQ_HANDLED;
527 }
528 
529 static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
530 {
531 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
532 		I2C_FUNC_SMBUS_READ_BLOCK_DATA;
533 }
534 
535 static const struct i2c_algorithm lpi2c_imx_algo = {
536 	.master_xfer	= lpi2c_imx_xfer,
537 	.functionality	= lpi2c_imx_func,
538 };
539 
540 static const struct of_device_id lpi2c_imx_of_match[] = {
541 	{ .compatible = "fsl,imx7ulp-lpi2c" },
542 	{ },
543 };
544 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
545 
546 static int lpi2c_imx_probe(struct platform_device *pdev)
547 {
548 	struct lpi2c_imx_struct *lpi2c_imx;
549 	unsigned int temp;
550 	int irq, ret;
551 
552 	lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL);
553 	if (!lpi2c_imx)
554 		return -ENOMEM;
555 
556 	lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0);
557 	if (IS_ERR(lpi2c_imx->base))
558 		return PTR_ERR(lpi2c_imx->base);
559 
560 	irq = platform_get_irq(pdev, 0);
561 	if (irq < 0)
562 		return irq;
563 
564 	lpi2c_imx->adapter.owner	= THIS_MODULE;
565 	lpi2c_imx->adapter.algo		= &lpi2c_imx_algo;
566 	lpi2c_imx->adapter.dev.parent	= &pdev->dev;
567 	lpi2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
568 	strscpy(lpi2c_imx->adapter.name, pdev->name,
569 		sizeof(lpi2c_imx->adapter.name));
570 
571 	ret = devm_clk_bulk_get_all(&pdev->dev, &lpi2c_imx->clks);
572 	if (ret < 0) {
573 		dev_err(&pdev->dev, "can't get I2C peripheral clock, ret=%d\n", ret);
574 		return ret;
575 	}
576 	lpi2c_imx->num_clks = ret;
577 
578 	ret = of_property_read_u32(pdev->dev.of_node,
579 				   "clock-frequency", &lpi2c_imx->bitrate);
580 	if (ret)
581 		lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
582 
583 	ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
584 			       pdev->name, lpi2c_imx);
585 	if (ret) {
586 		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
587 		return ret;
588 	}
589 
590 	i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx);
591 	platform_set_drvdata(pdev, lpi2c_imx);
592 
593 	ret = clk_bulk_prepare_enable(lpi2c_imx->num_clks, lpi2c_imx->clks);
594 	if (ret)
595 		return ret;
596 
597 	pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
598 	pm_runtime_use_autosuspend(&pdev->dev);
599 	pm_runtime_get_noresume(&pdev->dev);
600 	pm_runtime_set_active(&pdev->dev);
601 	pm_runtime_enable(&pdev->dev);
602 
603 	temp = readl(lpi2c_imx->base + LPI2C_PARAM);
604 	lpi2c_imx->txfifosize = 1 << (temp & 0x0f);
605 	lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f);
606 
607 	ret = i2c_add_adapter(&lpi2c_imx->adapter);
608 	if (ret)
609 		goto rpm_disable;
610 
611 	pm_runtime_mark_last_busy(&pdev->dev);
612 	pm_runtime_put_autosuspend(&pdev->dev);
613 
614 	dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n");
615 
616 	return 0;
617 
618 rpm_disable:
619 	pm_runtime_put(&pdev->dev);
620 	pm_runtime_disable(&pdev->dev);
621 	pm_runtime_dont_use_autosuspend(&pdev->dev);
622 
623 	return ret;
624 }
625 
626 static int lpi2c_imx_remove(struct platform_device *pdev)
627 {
628 	struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev);
629 
630 	i2c_del_adapter(&lpi2c_imx->adapter);
631 
632 	pm_runtime_disable(&pdev->dev);
633 	pm_runtime_dont_use_autosuspend(&pdev->dev);
634 
635 	return 0;
636 }
637 
638 static int __maybe_unused lpi2c_runtime_suspend(struct device *dev)
639 {
640 	struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
641 
642 	clk_bulk_disable(lpi2c_imx->num_clks, lpi2c_imx->clks);
643 	pinctrl_pm_select_sleep_state(dev);
644 
645 	return 0;
646 }
647 
648 static int __maybe_unused lpi2c_runtime_resume(struct device *dev)
649 {
650 	struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
651 	int ret;
652 
653 	pinctrl_pm_select_default_state(dev);
654 	ret = clk_bulk_enable(lpi2c_imx->num_clks, lpi2c_imx->clks);
655 	if (ret) {
656 		dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
657 		return ret;
658 	}
659 
660 	return 0;
661 }
662 
663 static const struct dev_pm_ops lpi2c_pm_ops = {
664 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
665 				      pm_runtime_force_resume)
666 	SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
667 			   lpi2c_runtime_resume, NULL)
668 };
669 
670 static struct platform_driver lpi2c_imx_driver = {
671 	.probe = lpi2c_imx_probe,
672 	.remove = lpi2c_imx_remove,
673 	.driver = {
674 		.name = DRIVER_NAME,
675 		.of_match_table = lpi2c_imx_of_match,
676 		.pm = &lpi2c_pm_ops,
677 	},
678 };
679 
680 module_platform_driver(lpi2c_imx_driver);
681 
682 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
683 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus");
684 MODULE_LICENSE("GPL");
685